Re: [Intel-gfx] Critical regression in 4.7-rcX

On Fri, 2016-07-15 at 10:34 -0500, Larry Finger wrote: > On 07/15/2016 09:43 AM, Ville Syrjälä wrote: > > > > On Fri, Jul 15, 2016 at 04:27:27PM +0200, Daniel Vetter wrote: > > > > > > On Fri, Jul 15, 2016 at 8:55 AM, Linus Torvalds > > > wrote: > > > > > > > >

Re: [Intel-gfx] [PATCH v3 1/3] drm/i915/gen9: Clean up MOCS table definitions

like the cleanup.  Perhaps someday we will add more entries and have the user space consume them :) Jim On Fri, 2016-07-01 at 16:40 +0300, Imre Deak wrote: > Use named struct initializers for clarity. Also fix the target cache > definition to reflect its role in GEN9 onwards. On GEN8 a TC value

Re: [Intel-gfx] [PATCH] drm/i915: Try to fix MST for SKL

On Thu, 2015-11-19 at 22:28 +0100, Kenneth Johansson wrote: > On 2015-11-10 21:15, Jesse Barnes wrote: > > On 08/17/2015 08:46 AM, ville.syrj...@linux.intel.com wrote: > > > From: Ville Syrjälä > > > > > > Set up the DDI->PLL mapping on SKL also for MST links.

[Intel-gfx] [PATCH] Fix build issue with 15_10 config with amdgpu

From: Jim Bish Signed-off-by: Jim Bish --- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index 0587bb2..15dd6fd 100644 ---

Re: [Intel-gfx] [PATCH v7 11/25] drm/i915: Register color correction capabilities

On Tue, 2015-10-20 at 18:04 +0530, Shashank Sharma wrote: > From DRM color management: > > DRM color manager supports these color properties: > 1. "ctm": Color transformation matrix property, where a >color transformation matrix of 9 correction values gets >

Re: [Intel-gfx] [PATCH v6 14/23] drm/i915: CHV: Pipe level degamma correction

to block? I wanted to get this closed out this week but... I see your point Gary but need a reading on Daniel's last sentence. Jim > >> >> Thanks >> Gary >> >> -Original Message- >> From: Sharma, Shashank >> Sent: Friday, October 16, 2015 3

Re: [Intel-gfx] [PATCH] drm/i915/bdw: Check for slice, subslice and EU count for BDW

On Thu, 2015-08-13 at 14:38 +0200, Łukasz Daniluk wrote: Added checks for available slices, subslices and EUs for Broadwell. This information is filled in intel_device_info and is available to user with GET_PARAM. Added checks for enabled slices, subslices and EU for Broadwell. This

Re: [Intel-gfx] [PATCH 04/16] drm: Add structure for querying palette color capabilities

On 07/15/2015 06:09 AM, Kausal Malladi wrote: The DRM color management framework is targeting various hardware platforms and drivers. Different platforms can have different color correction and enhancement capabilities. A commom user space application can query these capabilities using the

Re: [Intel-gfx] [PATCH 03/16] drm/i915: Attach color properties to CRTC

On 07/15/2015 06:09 AM, Kausal Malladi wrote: This patch does the following: 1. Adds new files intel_color_manager(.c/.h) 2. Attaches color properties to CRTC while initialization Signed-off-by: Shashank Sharma shashank.sha...@intel.com Signed-off-by: Kausal Malladi

Re: [Intel-gfx] [PATCH] drm/i915: Adjust BXT HDMI port clock limits

On Mon, 2015-07-13 at 11:05 +0200, Daniel Vetter wrote: On Fri, Jul 10, 2015 at 02:27:48PM +0100, Damien Lespiau wrote: On Fri, Jul 10, 2015 at 04:21:27PM +0300, Ville Syrjälä wrote: On Fri, Jul 10, 2015 at 02:18:57PM +0100, Damien Lespiau wrote: On Fri, Jul 10, 2015 at 04:09:42PM +0300,

Re: [Intel-gfx] [PATCH v4] drm/i915 : Added Programming of the MOCS

On 06/17/2015 08:19 AM, Peter Antoine wrote: This change adds the programming of the MOCS registers to the gen 9+ platforms. This change set programs the MOCS register values to a set of values that are defined to be optimal. It creates a fixed register set that is programmed across the

Re: [Intel-gfx] how to do scaling for primary plane

take a look at the panel fitter. Jim On 12/30/2014 08:09 AM, hank peng wrote: There are scaler registers for video sprite, but I found no register for primary plane. Is there some way to do that? ___ Intel-gfx mailing list