Re: [Intel-gfx] [PATCH 6/8] drm/i915/guc: Rename desc_idx to ctx_id

2022-02-22 Thread Ceraolo Spurio, Daniele
: Daniele Ceraolo Spurio Daniele --- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 56 +-- 1 file changed, 28 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index aa74ec74194a

Re: [Intel-gfx] [PATCH 5/8] drm/i915/guc: Move lrc desc setup to where it is needed

2022-02-22 Thread Ceraolo Spurio, Daniele
On 2/17/2022 3:52 PM, john.c.harri...@intel.com wrote: From: John Harrison The LRC descriptor was being initialised early on in the context registration sequence. It could then be determined that the actual registration needs to be delayed and the descriptor would be wiped out. This is ineff

Re: [Intel-gfx] [PATCH 4/8] drm/i915/guc: Split guc_lrc_desc_pin apart

2022-02-22 Thread Ceraolo Spurio, Daniele
the place where the return values are actually ignored. Signed-off-by: John Harrison Reviewed-by: Daniele Ceraolo Spurio Daniele --- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 45 --- 1 file changed, 28 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/

Re: [Intel-gfx] [PATCH 3/8] drm/i915/guc: Better name for context id limit

2022-02-22 Thread Ceraolo Spurio, Daniele
something like "the desc pool is sized based on the maximum numbers of contexts supported by the GuC, so define that limit directly". While at it, also update a kzalloc(sizeof()*count) to be a kcalloc(count,size). Signed-off-by: John Harrison Reviewed-by: Daniele Ceraolo Spurio

Re: [Intel-gfx] [PATCH 1/3] drm/i915/guc: Limit scheduling properties to avoid overflow

2022-02-22 Thread Ceraolo Spurio, Daniele
d in the GuC interface. If I'm correct, IMO we need to ask the GuC team to add them in, because it shouldn't be our responsibility to convert from ms to GuC clocks, considering that the interface is in ms. Not a blocker for this patch. Reviewed-by: Daniele Ceraolo Spurio Daniele + struct guc_policies { u32 submission_queue_depth[GUC_MAX_ENGINE_CLASSES]; /* In micro seconds. How much time to allow before DPC processing is

Re: [Intel-gfx] [PATCH 2/8] drm/i915/guc: Add an explicit 'submission_initialized' flag

2022-02-18 Thread Ceraolo Spurio, Daniele
way, so: Reviewed-by: Daniele Ceraolo Spurio Daniele --- drivers/gpu/drm/i915/gt/uc/intel_guc.h| 2 ++ drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 8 +--- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers

Re: [Intel-gfx] [PATCH 1/8] drm/i915/guc: Do not conflate lrc_desc with GuC id for registration

2022-02-18 Thread Ceraolo Spurio, Daniele
helper functions for context id mappings to better reflect their purpose and to differentiate from other registration related helper functions. Signed-off-by: John Harrison Reviewed-by: Daniele Ceraolo Spurio Daniele --- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 69

Re: [Intel-gfx] [PATCH 01/15] drm/i915/dg2: Define GuC firmware version for DG2

2022-02-18 Thread Ceraolo Spurio, Daniele
On 2/18/2022 10:47 AM, Ramalingam C wrote: From: John Harrison First release of GuC for DG2. Signed-off-by: John Harrison CC: Tomasz Mistat CC: Ramalingam C CC: Daniele Ceraolo Spurio Reviewed-by: Daniele Ceraolo Spurio Daniele --- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 1

Re: [Intel-gfx] [PATCH] drm/i915/guc: Initialize GuC submission locks and queues early

2022-02-15 Thread Ceraolo Spurio, Daniele
On 2/15/2022 1:09 AM, Tvrtko Ursulin wrote: On 15/02/2022 01:11, Daniele Ceraolo Spurio wrote: Move initialization of submission-related spinlock, lists and workers to init_early. This fixes an issue where if the GuC init fails we might still try to get the lock in the context cleanup code.

Re: [Intel-gfx] [PATCH v3] drm/i915/gen11: Preempt-to-idle support in execlists.

2018-05-22 Thread Ceraolo Spurio, Daniele
On 5/21/2018 3:16 AM, Lis, Tomasz wrote: On 2018-05-18 23:08, Daniele Ceraolo Spurio wrote: On 11/05/18 08:45, Tomasz Lis wrote: The patch adds support of preempt-to-idle requesting by setting a proper bit within Execlist Control Register, and receiving preemption result from Context St

Re: [Intel-gfx] [PATCH v7 10/12] drm/i915/guc: Handle default action received over CT

2018-03-28 Thread Ceraolo Spurio, Daniele
On 3/27/2018 3:49 PM, Michel Thierry wrote: On 3/27/2018 2:41 PM, Michal Wajdeczko wrote: When running on platform with CTB based GuC communication enabled, GuC to Host event data will be delivered as CT request message. However, content of the data[1] of this CT message follows format of the

Re: [Intel-gfx] [PATCH 08/12] drm/i915/guc: Wait for doorbell to be inactive before deallocating

2017-03-21 Thread Ceraolo Spurio, Daniele
On 3/21/2017 2:02 AM, Oscar Mateo wrote: Doorbell release flow requires that we wait for GEN8_DRB_VALID bit to go to zero after updating db_status before we call the GuC to release the doorbell. Kudos to Daniele for finding this out. v2: WARN instead of DRM_ERROR (Joonas) Cc: Joonas Lahtinen

Re: [Intel-gfx] [PATCH 12/12] drm/i915/guc: Move guc_interrupts_release next to guc_interrupts_capture

2017-03-21 Thread Ceraolo Spurio, Daniele
On 3/21/2017 2:02 AM, Oscar Mateo wrote: They go better together. I agree :) Reviewed-by: Daniele Ceraolo Spurio Thanks, Daniele ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 11/12] drm/i915/guc: Split out the mmio_white_list struct

2017-03-21 Thread Ceraolo Spurio, Daniele
On 3/21/2017 2:02 AM, Oscar Mateo wrote: We are going to need it for future platforms. Cc: Daniele Ceraolo Spurio Cc: Joonas Lahtinen Signed-off-by: Oscar Mateo Reviewed-by: Daniele Ceraolo Spurio Thanks, Daniele ___ Intel-gfx mailing list Int

Re: [Intel-gfx] [PATCH 07/12] drm/i915/guc: Improve the GuC documentation & comments about proxy submissions

2017-03-21 Thread Ceraolo Spurio, Daniele
On 3/21/2017 2:02 AM, Oscar Mateo wrote: While at it, fix a typo (s/ring_lcra/ring_lrca) and improve the naming of one firware interface field (s/ring_tail/submit_element_info, since it can contain more than just the ring tail). No change in functionality. v2: - Remove reference to "unique

Re: [Intel-gfx] [PATCH 04/12] drm/i915/guc: The Additional Data Struct (ADS) should get enabled together with GuC submission

2017-03-21 Thread Ceraolo Spurio, Daniele
On 3/21/2017 2:02 AM, Oscar Mateo wrote: It's mandatory and it gets created if and only if GuC submission is enabled, so that should be the condition for informing the GuC about it. This is true now, but GuC might actually require the ADS even if GuC submission is disabled, depending on the

Re: [Intel-gfx] [PATCH] drm/i915/skl: Do not write the replay bit of the ring mode register for Gen 9

2017-02-20 Thread Ceraolo Spurio, Daniele
On 2/17/2017 3:43 PM, Kelvin Gardiner wrote: The reply bit of the ring mode register is only valid on Gen 8. s/reply/replay. Also, from the specs it looks like this bit is reserved in Gen8 production steppings, so we should be able to drop it entirely. Thanks, Daniele Therefore do not wr

Re: [Intel-gfx] [PATCH] drm/i915/guc: fix mmio whitelist mmio_start offset and add reminder

2017-01-02 Thread Ceraolo Spurio, Daniele
On 1/2/2017 4:18 AM, MichaƂ Winiarski wrote: On Thu, Dec 29, 2016 at 05:32:47PM -0800, daniele.ceraolospu...@intel.com wrote: From: Daniele Ceraolo Spurio The mmio_start offset for the whitelist is the first FORCE_TO_NONPRIV register the GuC can use to restore the provided whitelist when an

Re: [Intel-gfx] [PATCH] drm/i915/guc: Assert that all GGTT offsets used by the GuC are mappable

2016-12-24 Thread Ceraolo Spurio, Daniele
On 12/24/2016 1:22 PM, Chris Wilson wrote: On Sat, Dec 24, 2016 at 12:52:37PM -0800, Ceraolo Spurio, Daniele wrote: On 12/24/2016 11:31 AM, Chris Wilson wrote: Add an assertion to the plain i915_ggtt_offset() to double check that any offset we hand to the GuC is outside of its unmappable

Re: [Intel-gfx] [PATCH] drm/i915/guc: Assert that all GGTT offsets used by the GuC are mappable

2016-12-24 Thread Ceraolo Spurio, Daniele
On 12/24/2016 11:31 AM, Chris Wilson wrote: Add an assertion to the plain i915_ggtt_offset() to double check that any offset we hand to the GuC is outside of its unmappable ranges. Signed-off-by: Chris Wilson Cc: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/i915_guc_submission.c | 14 ++

Re: [Intel-gfx] [PATCH 2/2] drm/i915: re-use computed offset bias for context pin

2016-12-24 Thread Ceraolo Spurio, Daniele
On 12/24/2016 2:12 AM, Chris Wilson wrote: On Fri, Dec 23, 2016 at 03:56:22PM -0800, daniele.ceraolospu...@intel.com wrote: From: Daniele Ceraolo Spurio The context has to obey the same offset requirements as the ring, so we can re-use the same bias value we computed for the ring instead of

Re: [Intel-gfx] [PATCH] drm/i915: Store device pointer in contexts for late tracepoint usafe

2015-07-09 Thread Ceraolo Spurio, Daniele
raolo Spurio Reviewed-by: Daniele Ceraolo Spurio Daniele -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] NULL pointer dereference in trace_i915_context_free

2015-07-09 Thread Ceraolo Spurio, Daniele
Hi, I'm hitting a NULL pointer dereference when I enable the i915_context_free tracepoint (call trace attached). This is caused by the fact that the trace tries to access ctx->file_priv, which however may have already been deleted (even if the pointer is != NULL). I've used that trace extensi

Re: [Intel-gfx] [PATCH v3] [i-g-t] tests/gem_ppgtt: Check for vm leaks with flink and ppgtt

2015-04-23 Thread Ceraolo Spurio, Daniele
On 4/23/2015 12:36 PM, Chris Wilson wrote: On Thu, Apr 23, 2015 at 12:23:17PM +0100, daniele.ceraolospu...@intel.com wrote: From: Tvrtko Ursulin Using imported objects should not leak i915 vmas (and vms). In practice this simulates Xorg importing fbcon and leaking (or not) one vma per Xorg st

Re: [Intel-gfx] [PATCH v2] [i-g-t] tests/gem_ppgtt: Check for vm leaks with flink and ppgtt

2015-04-23 Thread Ceraolo Spurio, Daniele
On 4/23/2015 10:43 AM, Chris Wilson wrote: On Thu, Apr 23, 2015 at 10:30:01AM +0100, daniele.ceraolospu...@intel.com wrote: From: Daniele Ceraolo Spurio From: Tvrtko Ursulin Using imported objects should not leak i915 vmas (and vms). In practice this simulates Xorg importing fbcon and leaki

Re: [Intel-gfx] [PATCH v6] drm/i915: Add tracepoints to track a vm during its lifetime

2014-11-10 Thread Ceraolo Spurio, Daniele
On 11/10/2014 11:54 AM, Chris Wilson wrote: On Mon, Nov 10, 2014 at 11:40:40AM +, Ceraolo Spurio, Daniele wrote: On 11/8/2014 8:44 AM, Chris Wilson wrote: On Fri, Nov 07, 2014 at 05:45:01PM +, daniele.ceraolospu...@intel.com wrote: +/** + * DOC: execlist_submit_context tracepoint

Re: [Intel-gfx] [PATCH v6] drm/i915: Add tracepoints to track a vm during its lifetime

2014-11-10 Thread Ceraolo Spurio, Daniele
On 11/10/2014 11:40 AM, Ceraolo Spurio, Daniele wrote: On 11/8/2014 8:44 AM, Chris Wilson wrote: On Fri, Nov 07, 2014 at 05:45:01PM +, daniele.ceraolospu...@intel.com wrote: +/** + * DOC: execlist_submit_context tracepoint + * + * These tracepoint are used to track the contexts that are

Re: [Intel-gfx] [PATCH v5] drm/i915: Add ppgtt create/release trace points

2014-10-27 Thread Ceraolo Spurio, Daniele
On 10/27/2014 8:49 AM, Chris Wilson wrote: On Fri, Oct 24, 2014 at 04:30:52PM +0100, daniele.ceraolospu...@intel.com wrote: From: Daniele Ceraolo Spurio These tracepoints are useful for observing the creation and destruction of Full PPGTTs. v4: add DOC information v5: pull the DOC in drm.tmpl

Re: [Intel-gfx] [RFC v2 2/3] drm/i915: duplicate i915_gem_ring_dispatch trace and add ctx parameter

2014-07-30 Thread Ceraolo Spurio, Daniele
I would also like a better ctx identifier than its pointer. Using the pointer for tracking objects makes it more difficult to read traces (although it is easy for scripts). I use the VM pointer to track the ppgtt; that pointer is also printed by several other traces, including the ppgtt init/rel

Re: [Intel-gfx] [RFC v2 2/3] drm/i915: duplicate i915_gem_ring_dispatch trace and add ctx parameter

2014-07-18 Thread Ceraolo Spurio, Daniele
On 7/17/2014 5:25 PM, Chris Wilson wrote: On Wed, Jul 16, 2014 at 05:22:38PM +0100, daniele.ceraolospu...@intel.com wrote: From: Daniele Ceraolo Spurio The context used to execute a batchbuffer is becoming increasingly important. Duplicating to avoid modifications to the original trace. I am

<    1   2   3   4