From: Maarten Lankhorst
In case of legacy cursor update, the cursor VMA needs to be unpinned
only after vblank. This exceeds the lifetime of the whole atomic commit.
Any trick I attempted to keep the atomic commit alive didn't work, as
drm_atomic_helper_setup_commit() force throttles on any old
(), therefore, wait one vblank
if there are pending vblank workers.
This patch is slightly reworked by Maarten.
Cc: Maarten Lankhorst
Signed-off-by: Ville Syrjälä
Signed-off-by: Maarten Lankhorst
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/i915/display/intel_cursor.c | 26
Add helper to check if there are pending vblank work for a crtc
which are yet to be scheduled.
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/drm_vblank_work.c | 24
include/drm/drm_vblank_work.h | 1 +
2 files changed, 25 insertions(+)
diff --git
From: Maarten Lankhorst
In some cases we want to flush all vblank work, right before vblank_off
for example. Add a simple function to make this possible.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/drm_vblank_work.c | 22 ++
include/drm/drm_vblank_work.h | 2
-a-2.html
Chaitanya Kumar Borah (1):
drm: Add helper to check if there are pending vblank work
Maarten Lankhorst (2):
drm: Add drm_vblank_work_flush_all().
drm/i915: Use the same vblank worker for atomic unpin
Ville Syrjälä (1):
drm/i915: Use vblank worker to unpin old legacy cursor fb
the Maud and Naud SDPs on it's own.
Cc: sta...@vger.kernel.org # v5.17
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8097
Co-developed-by: Kai Vehmanen
Signed-off-by: Kai Vehmanen
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/i915/display/intel_audio.c | 113
the Maud and Naud SDPs on it's own.
Cc: sta...@vger.kernel.org # v5.17
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8097
Co-developed-by: Kai Vehmanen
Signed-off-by: Kai Vehmanen
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/i915/display/intel_audio.c | 111
the Maud and Naud SDPs on it's own.
Fixes: 6014ac122ed0 ("drm/i915/audio: set proper N/M in modeset")
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8097
Co-developed-by: Kai Vehmanen
Signed-off-by: Kai Vehmanen
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/i9
/0x350
[ 278.750452] ? __pfx_worker_thread+0x10/0x10
[ 278.750455] kthread+0xfe/0x130
[ 278.750460] ? __pfx_kthread+0x10/0x10
[ 278.750464] ret_from_fork+0x2c/0x50
[ 278.750468] ? __pfx_kthread+0x10/0x10
[ 278.750472] ret_from_fork_asm+0x1b/0x30
Signed-off-by: Chaitanya Kumar
The plane destroy hook can be called asynchronously even when vblank
worker responsible for unpinning the cursor fb is scheduled. Since
the vblank worker destroys the plane state, do not destroy the plane
state if it is scheduled.
Signed-off-by: Chaitanya Kumar Borah
---
.../gpu/drm/i915
Now that cursor plane fb unpinning can be deferred to vblank work
access the fb object only when vblank unpin worker is not scheduled.
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/i915/display/intel_atomic_plane.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git
From: Ville Syrjälä
The cursor hardware only does sync updates, and thus the hardware
will be scanning out from the old fb until the next start of vblank.
So in order to make the legacy cursor fastpath actually safe we
should not unpin the old fb until we're sure the hardware has
ceased
From: Maarten Lankhorst
In case of legacy cursor update, the cursor VMA needs to be unpinned
only after vblank. This exceeds the lifetime of the whole atomic commit.
Any trick I attempted to keep the atomic commit alive didn't work, as
drm_atomic_helper_setup_commit() force throttles on any old
a discussion to arrive at one.
[1] https://patchwork.freedesktop.org/series/126934/
v2: Add missing patch
v3: Remove misleading error log
Change condition to access fb object
v4: Remove unused variables
Chaitanya Kumar Borah (3):
drm/i915: do not destroy plane state if cursor unpin worker
From: Maarten Lankhorst
In some cases we want to flush all vblank work, right before vblank_off
for example. Add a simple function to make this possible.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/drm_vblank_work.c | 22 ++
include/drm/drm_vblank_work.h | 2
/0x350
[ 278.750452] ? __pfx_worker_thread+0x10/0x10
[ 278.750455] kthread+0xfe/0x130
[ 278.750460] ? __pfx_kthread+0x10/0x10
[ 278.750464] ret_from_fork+0x2c/0x50
[ 278.750468] ? __pfx_kthread+0x10/0x10
[ 278.750472] ret_from_fork_asm+0x1b/0x30
Signed-off-by: Chaitanya Kumar
Now that cursor plane fb unpinning can be deferred to vblank work
access the fb object only when vblank unpin worker is not scheduled.
v2: - Remove misleading error log
- Change condition for accessing fb object
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/i915/display
The plane destroy hook can be called asynchronously even when vblank
worker responsible for unpinning the cursor fb is scheduled. Since
the vblank worker destroys the plane state, do not destroy the plane
state if it is scheduled.
Signed-off-by: Chaitanya Kumar Borah
---
.../gpu/drm/i915
From: Maarten Lankhorst
In case of legacy cursor update, the cursor VMA needs to be unpinned
only after vblank. This exceeds the lifetime of the whole atomic commit.
Any trick I attempted to keep the atomic commit alive didn't work, as
drm_atomic_helper_setup_commit() force throttles on any old
From: Ville Syrjälä
The cursor hardware only does sync updates, and thus the hardware
will be scanning out from the old fb until the next start of vblank.
So in order to make the legacy cursor fastpath actually safe we
should not unpin the old fb until we're sure the hardware has
ceased
From: Maarten Lankhorst
In some cases we want to flush all vblank work, right before vblank_off
for example. Add a simple function to make this possible.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/drm_vblank_work.c | 22 ++
include/drm/drm_vblank_work.h | 2
a discussion to arrive at one.
[1] https://patchwork.freedesktop.org/series/126934/
v2: Add missing patch
v3: Remove misleading error log
Change condition to access fb object
Chaitanya Kumar Borah (3):
drm/i915: do not destroy plane state if cursor unpin worker is
scheduled
drm/i915
a discussion to arrive at one.
[1] https://patchwork.freedesktop.org/series/126934/
v2: Add missing patch
Chaitanya Kumar Borah (3):
drm/i915: do not destroy plane state if cursor unpin worker is
scheduled
drm/i915: Add sanity checks before accessing fb buffer object
drm/i915: do
/0x350
[ 278.750452] ? __pfx_worker_thread+0x10/0x10
[ 278.750455] kthread+0xfe/0x130
[ 278.750460] ? __pfx_kthread+0x10/0x10
[ 278.750464] ret_from_fork+0x2c/0x50
[ 278.750468] ? __pfx_kthread+0x10/0x10
[ 278.750472] ret_from_fork_asm+0x1b/0x30
Signed-off-by: Chaitanya Kumar
From: Ville Syrjälä
The cursor hardware only does sync updates, and thus the hardware
will be scanning out from the old fb until the next start of vblank.
So in order to make the legacy cursor fastpath actually safe we
should not unpin the old fb until we're sure the hardware has
ceased
The plane destroy hook can be called asynchronously even when vblank
worker responsible for unpinning the cursor fb is scheduled. Since
the vblank worker destroys the plane state, do not destroy the plane
state if it is scheduled.
Signed-off-by: Chaitanya Kumar Borah
---
.../gpu/drm/i915
Now that cursor plane fb unpinning can be deferred to vblank work
check if plane state and corresponding fb pointers are still valid
before cleanup.
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/i915/display/intel_atomic_plane.c | 8 +++-
1 file changed, 7 insertions(+), 1
From: Maarten Lankhorst
In some cases we want to flush all vblank work, right before vblank_off
for example. Add a simple function to make this possible.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/drm_vblank_work.c | 22 ++
include/drm/drm_vblank_work.h | 2
From: Maarten Lankhorst
In case of legacy cursor update, the cursor VMA needs to be unpinned
only after vblank. This exceeds the lifetime of the whole atomic commit.
Any trick I attempted to keep the atomic commit alive didn't work, as
drm_atomic_helper_setup_commit() force throttles on any old
From: Maarten Lankhorst
In case of legacy cursor update, the cursor VMA needs to be unpinned
only after vblank. This exceeds the lifetime of the whole atomic commit.
Any trick I attempted to keep the atomic commit alive didn't work, as
drm_atomic_helper_setup_commit() force throttles on any old
/0x350
[ 278.750452] ? __pfx_worker_thread+0x10/0x10
[ 278.750455] kthread+0xfe/0x130
[ 278.750460] ? __pfx_kthread+0x10/0x10
[ 278.750464] ret_from_fork+0x2c/0x50
[ 278.750468] ? __pfx_kthread+0x10/0x10
[ 278.750472] ret_from_fork_asm+0x1b/0x30
Signed-off-by: Chaitanya Kumar
Now that cursor plane fb unpinning can be deferred to vblank work
check if plane state and corresponding fb pointers are still valid
before cleanup.
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/i915/display/intel_atomic_plane.c | 8 +++-
1 file changed, 7 insertions(+), 1
The plane destroy hook can be called asynchronously even when vblank
worker responsible for unpinning the cursor fb is scheduled. Since
the vblank worker destroys the plane state, do not destroy the plane
state if it is scheduled.
Signed-off-by: Chaitanya Kumar Borah
---
.../gpu/drm/i915
a discussion to arrive at one.
[1] https://patchwork.freedesktop.org/series/126934/
Chaitanya Kumar Borah (3):
drm/i915: do not destroy plane state if cursor unpin worker is
scheduled
drm/i915: Add sanity checks before accessing fb buffer object
drm/i915: do not defer cleanup work
From: Ville Syrjälä
The cursor hardware only does sync updates, and thus the hardware
will be scanning out from the old fb until the next start of vblank.
So in order to make the legacy cursor fastpath actually safe we
should not unpin the old fb until we're sure the hardware has
ceased
From: Johannes Berg
This reverts commit f4acfcd4deb1 ("debugfs: annotate debugfs handlers
vs. removal with lockdep"), it appears to have false positives and
really shouldn't have been in the -rc series with the fixes anyway.
From: Johannes Berg
This reverts commit f4acfcd4deb1 ("debugfs: annotate debugfs handlers
vs. removal with lockdep"), it appears to have false positives and
really shouldn't have been in the -rc series with the fixes anyway.
topic/core-for-CI note: cherry-picked from
eDP specification supports HBR3 link rate since v1.4a. Moreover,
C10 phy can support HBR3 link rate for both DP and eDP. Therefore,
do not clamp the supported rates for eDP at 6.75Gbps.
Cc:
BSpec: 70073 74224
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/i915/display/intel_dp.c
Add a wrapper around intel_step_name that takes in driver data as an
argument. This wrapper will help maintain compatibility with the
proposed xe driver.
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dmc.c | 2 +-
drivers/gpu/drm/i915
Add newly added PCI-IDs for RPL
BSpec: 55376
Signed-off-by: Chaitanya Kumar Borah
---
include/drm/i915_pciids.h | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 1661f9e552d2..1256770d3827 100644
for upscaling values
v3: Fix multi line comment style (Uma)
v4: Remove extra line(Ankit)
Signed-off-by: Chaitanya Kumar Borah
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers
For MTL and beyond, convert back the 24 bit lut values
read from HW to 16 bit values to maintain parity with
userspace values. This way we avoid pipe config mismatch
for pre-csc lut values.
v2: Add helper function to downscale values (Jani)
Signed-off-by: Chaitanya Kumar Borah
Reviewed-by: Uma
for upscaling values
v3: Fix multi line comment style (Uma)
Signed-off-by: Chaitanya Kumar Borah
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c | 20 +++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display
to continue supporting degamma on MTL.
To avoid pipe config mismatch between 24 bit HW lut values and 16 bit
userspace sent values, convert back the 24 bit lut values read from HW
to 16 bit values.
Chaitanya Kumar Borah (2):
drm/i915/color: Upscale degamma values for MTL
drm/i915/color: Downscale
For MTL and beyond, convert back the 24 bit lut values
read from HW to 16 bit values to maintain parity with
userspace values. This way we avoid pipe config mismatch
for pre-csc lut values.
v2: Add helper function to downscale values (Jani)
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu
for upscaling values
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/i915/display/intel_color.c | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index
to continue supporting degamma on MTL.
To avoid pipe config mismatch between 24 bit HW lut values and 16 bit
userspace sent values, convert back the 24 bit lut values read from HW
to 16 bit values.
Chaitanya Kumar Borah (2):
drm/i915/color: Upscale degamma values for MTL
drm/i915/color: Downscale
Chaitanya Kumar Borah
---
drivers/gpu/drm/i915/display/intel_display_power.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
b/drivers/gpu/drm/i915/display/intel_display_power.h
index be1a87bde0c9..0ba268e566b0 100644
--- a/drivers/gpu/drm/i9
With change [1], visibility of struct seq_file is lost in
intel_display_power.h leading to build errors. Add header
file explicitly to restore visibility.
[1] ef104443bffa ("procfs: consolidate arch_report_meminfo declaration")
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gp
to continue supporting degamma on MTL.
To avoid pipe config mismatch between 24 bit HW lut values and 16 bit
userspace sent values, convert back the 24 bit lut values read from HW
to 16 bit values.
Chaitanya Kumar Borah (2):
drm/i915/color: Add function to load degamma LUT in MTL
drm/i915/color
For MTL and beyond, convert back the 24 bit lut values
read from HW to 16 bit values to maintain parity with
userspace values. This way we avoid pipe config mismatch
for pre-csc lut values.
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/i915/display/intel_color.c | 8
1 file
to continue supporting degamma on MTL.
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/i915/display/intel_color.c | 42 --
1 file changed, 40 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
ave, particularly with the "Fix me"
comment which indicates a bigger underlying problem. Hence, the
RFC.
[1] 3b0fb6ab25("fbcon: Use delayed work for cursor")
[2]
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13243/shard-glk2/igt@kms_fbcon_...@fbc-suspend.html
Signed-off-by
According to Bspec, the voltage level for 480MHz is to be set as 1
instead of 2.
BSpec: 49208
Fixes: 06f1b06dc5b7 ("drm/i915/display: Add 480 MHz CDCLK steps for RPL-U")
v2: rebase
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/i915/display/intel_cd
Replace _PLANE_INPUT_CSC_RY_GY_2_* with _PLANE_CSC_RY_GY_2_*
for Plane CSC
Fixes: 6eba56f64d5d ("drm/i915/pxp: black pixels on pxp disabled")
Cc:
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/i915/i915_reg.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
According to Bspec, the voltage level for 480MHz is to be set as 1
instead of 2.
BSpec: 49208
Fixes: 06f1b06dc5b7 ("drm/i915/display: Add 480 MHz CDCLK steps for RPL-U")
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 30 +++-
)
- Add RPL-U ids to RPL-P platform
- Remove redundant comment
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_device_info.c | 7 +++
drivers/gpu/drm/i915/intel_device_info.h | 1 +
include/drm/i915_pciids.h
: - Revert to RPL-U subplatform (Jani)
v4: - Remove Bspec reference from code (Jani)
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers
a decision if this particular part needs
to be upstreamed.(see comments on revision 2)
Chaitanya Kumar Borah (2):
drm/i915: Add RPL-U sub platform
drm/i915/display: Add 480 MHz CDCLK steps for RPL-U
drivers/gpu/drm/i915/display/intel_cdclk.c | 26 ++
drivers/gpu/drm/i915
-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/intel_device_info.c | 8
drivers/gpu/drm/i915/intel_device_info.h | 2 ++
include/drm/i915_pciids.h| 11 +++
5 files
: - Revert to RPL-U subplatform
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 27 ++
1 file changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 0c107a38f9d0
a decision if this particular part needs
to be upstreamed.(see comments on revision 2)
Chaitanya Kumar Borah (2):
drm/i915: Add RPL-U sub platform
drm/i915/display: Add 480 MHz CDCLK steps for RPL-U
drivers/gpu/drm/i915/display/intel_cdclk.c | 27 ++
drivers/gpu/drm/i915
Fix typo for reference clock from 24400 to 24000
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index
-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 0c107a38f9d0..ba365ef17abc 100644
--- a/drivers
RPL-U part of RPL subplatform
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/intel_device_info.c | 8
drivers/gpu/drm/i915/intel_device_info.h | 2 ++
include/drm
a decision if this particular part needs
to be upstreamed.(see comments on revision 2)
Chaitanya Kumar Borah (2):
drm/i915: Add sub platform for 480MHz CDCLK step
drm/i915/display: Add 480 MHz CDCLK steps for RPL-U
drivers/gpu/drm/i915/display/intel_cdclk.c | 26 ++
drivers
A new step of 480MHz has been added on SKUs that have a RPL-U
device id to support 120Hz displays more efficiently. Use a
new quirk to identify the machine for which this change needs
to be applied.
BSpec: 55409
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/i915/display
Adding RPL-U as a sub platform. In RPL-U a new CDCLK step has
been added so we need to make a distinction between RPL-P
and RPL-U while CDCLK initialization.
Adding a sub-platform, enables us to make this differentiation
in the code.
Signed-off-by: Chaitanya Kumar Borah
---
arch/x86/kernel
a decision if this particular part needs
to be upstreamed.(see comments on previous versions)
Chaitanya Kumar Borah (2):
drm/i915: Add rplu sub platform
drm/i915/display: Add 480 MHz CDCLK steps for RPL-U
arch/x86/kernel/early-quirks.c | 1 +
drivers/gpu/drm/i915/display/intel_cdclk.c
n Intel(R) Core(TM) i5-1345U"
BSpec: 55409
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/i915/display/intel_quirks.c | 32 +++--
1 file changed, 29 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_quirks.c
b/drivers/gpu/drm/i915/di
With addition of new quirk QUIRK_480MHZ_CDCLK_STEP, it is imperative
that quirks should be initialized before CDCLK initialization. Refactor
the code accordingly.
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/i915/display/intel_display.c | 2 --
drivers/gpu/drm/i915/i915_driver.c
A new step of 480MHz has been added on SKUs that have a RPL-U
device id to support 120Hz displays more efficiently. Use a
new quirk to identify the machine for which this change needs
to be applied.
BSpec: 55409
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/i915/display
. Therefore, quirks
are a good way to achieve the same.
BSpec: 55409
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/i915/display/intel_quirks.c | 14 ++
drivers/gpu/drm/i915/display/intel_quirks.h | 1 +
2 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915
recated in future. Feedbacks are welcome.
Chaitanya Kumar Borah (4):
drm/i915/quirks: Add quirk for 480MHz CDCLK step
drm/i915/display: Add 480 MHz CDCLK steps for RPL-U
drm/i915: Initialize intel quirks before CDCLK initialization
drm/i915: Apply CDCLK quirk only on QS parts
drivers/g
writing into the HW to continue supporting degamma on
MTL.
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/i915/display/intel_color.c | 42 --
1 file changed, 40 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm
A new step of 480MHz has been added on SKUs that have a RPL-U
device id. Add a new table which include this new CDCLK step.
BSpec: 55409
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 39 ++
1 file changed, 39 insertions(+)
diff --git
Chaitanya Kumar Borah
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 9bfeb1abba47..1890e5135cfc 100644
--- a/drivers/gp
are adding this
distinction since they are currently in use. However, here the question
arises if we keep this change in upstream or not as this could just be dead
code down the line. Feedbacks are appreciated on this.
Chaitanya Kumar Borah (2):
drm/i915: Add RPL-U CDCLK table
drm/i915: Add additional check
Remove force probe protection from DG1 platform as testing suggests
that the platform is stable enough.
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/i915/i915_pci.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
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