Re: [Intel-gfx] [PATCH 2/3] drm/i915/gt: Wait for CSB entries on Tigerlake

2020-08-14 Thread Chang, Bruce
On 8/14/2020 5:36 PM, Chang, Bruce wrote: @@ -2498,9 +2498,22 @@ invalidate_csb_entries(const u64 *first, const u64 *last)     */    static inline bool gen12_csb_parse(const u64 *csb)    { - u64 entry = READ_ONCE(*csb); - bool ctx_away_valid = GEN12_CSB_CTX_VALID(upper_32_bits(entry

Re: [Intel-gfx] [PATCH 2/3] drm/i915/gt: Wait for CSB entries on Tigerlake

2020-08-14 Thread Chang, Bruce
@@ -2498,9 +2498,22 @@ invalidate_csb_entries(const u64 *first, const u64 *last) */ static inline bool gen12_csb_parse(const u64 *csb) { - u64 entry = READ_ONCE(*csb); - bool ctx_away_valid = GEN12_CSB_CTX_VALID(upper_32_bits(entry)); - bool new_queue = + bool

Re: [Intel-gfx] [PATCH 3/3] drm/i915/gt: Apply the CSB w/a for all

2020-08-14 Thread Chang, Bruce
On 8/14/2020 8:57 AM, Chris Wilson wrote: Since we expect to inline the csb_parse() routines, the w/a for the stale CSB data on Tigerlake will be pulled into process_csb(), and so we might as well simply reuse the logic for all, and so will hopefully avoid any strange behaviour on Icelake that

Re: [Intel-gfx] [PATCH 2/3] drm/i915/gt: Wait for CSB entries on Tigerlake

2020-08-14 Thread Chang, Bruce
On 8/14/2020 8:57 AM, Chris Wilson wrote: On Tigerlake, we are seeing a repeat of commit d8f505311717 ("drm/i915/icl: Forcibly evict stale csb entries") where, presumably, due to a missing Global Observation Point synchronisation, the write pointer of the CSB ringbuffer is updated _prior_ to the

Re: [Intel-gfx] [PATCH] drm/i915/gt: Incrementally check for rewinding

2020-06-09 Thread Chang, Bruce
On 6/9/2020 8:17 AM, Chris Wilson wrote: In commit 5ba32c7be81e ("drm/i915/execlists: Always force a context reload when rewinding RING_TAIL"), we placed the check for rewinding a context on actually submitting the next request in that context. This was so that we only had to check once, and