gt_tlb, and thus igt_cs_tlb
> is obsolete and should be removed.
gt_tlb supersedes igt_cs_tlb, that I can agree on,
Acked-by: Chris Wilson
-Chris
iary table invalidation is done only for the
> engine executing the request. And the mmio address for the aux_inv
> register is set after the engine instance becomes certain.
>
> Signed-off-by: Chris Wilson
> Signed-off-by: Fei Yang
> ---
> drivers/gpu/drm/i915/gt/gen8_eng
Quoting Janusz Krzysztofik (2022-02-18 17:08:41)
> Hi Chris,
>
> On Friday, 18 February 2022 17:03:01 CET Chris Wilson wrote:
> > Quoting Janusz Krzysztofik (2022-02-18 15:19:35)
> > > @@ -206,15 +229,19 @@ static struct pci_device
> > > *_
Quoting Janusz Krzysztofik (2022-02-18 15:19:35)
> @@ -206,15 +229,19 @@ static struct pci_device
> *__igt_device_get_pci_device(int fd)
> igt_warn("Couldn't find PCI device %04x:%02x:%02x:%02x\n",
> pci_addr.domain, pci_addr.bus,
>
y the series of
individual patches.
Reviewed-by: Chris Wilson
-Chris
Quoting Andi Shyti (2021-11-17 13:34:56)
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index 089fb4658b216..0bbf8c0c42eac 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++
Quoting Ville Syrjälä (2021-03-22 14:48:44)
> On Sun, Mar 21, 2021 at 04:30:32PM +0000, Chris Wilson wrote:
> > Quoting Chris Wilson (2021-03-21 16:28:07)
> > > Quoting Ville Syrjala (2021-03-21 16:10:38)
> > > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
Quoting Chris Wilson (2021-03-21 16:30:32)
> Quoting Chris Wilson (2021-03-21 16:28:07)
> > Quoting Ville Syrjala (2021-03-21 16:10:38)
> > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> > > b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> > > ind
Quoting Chris Wilson (2021-03-21 16:28:07)
> Quoting Ville Syrjala (2021-03-21 16:10:38)
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> > b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> > index ec28a6cde49b..0b2434e29d00 100644
> > --- a/drivers/gpu/d
on my 85x.
NOEVICT will make it much less eager to remove older bindings, with the
preference then to use smaller views of objects. The theory being that
the workingset is less than the whole object, so we can fit more active
pages in and cause less thrashing when moving the unused pages aro
Quoting Zbigniew Kempczyński (2021-03-11 11:44:32)
> On Wed, Mar 10, 2021 at 03:50:07PM -0600, Jason Ekstrand wrote:
> > The Vulkan driver in Mesa for Intel hardware never uses relocations if
> > it's running on a version of i915 that supports at least softpin which
> > all versions of i915
Quoting Daniel Vetter (2021-03-11 16:01:46)
> On Fri, Mar 05, 2021 at 11:05:46AM -0600, Jason Ekstrand wrote:
> > This reverts commit 9e31c1fe45d555a948ff66f1f0e3fe1f83ca63f7. Ever
> > since that commit, we've been having issues where a hang in one client
> > can propagate to another. In
Quoting Tvrtko Ursulin (2021-03-10 10:19:12)
>
> Hi,
>
> On 08/03/2021 17:32, Chiou, Cooper wrote:
> > I've tested on GLK, KBL, CFL Intel NUC devices and got the following
> > performance results, there is no performance regression per my testing.
> >
> > Patch: [v5] drm/i915: Enable
Quoting Jia-Ju Bai (2021-03-08 08:59:52)
> When i915_random_order() returns NULL to order, no error return code of
> igt_buddy_alloc_smoke() is assigned.
> To fix this bug, err is assigned with -EINVAL in this case.
It would not be EINVAL since that is used for a reference failure, but
in this
Quoting Jia-Ju Bai (2021-03-08 09:07:22)
> When kcalloc() returns NULL to tsk or thread, no error code of
> igt_threaded_blt() is returned.
> To fix this bug, -ENOMEM is returned as error code.
Because we decided to skip the test if it could not be run due to
insufficient memory, as opposed to
Quoting Jason Ekstrand (2021-03-05 17:05:46)
> This reverts commit 9e31c1fe45d555a948ff66f1f0e3fe1f83ca63f7. Ever
> since that commit, we've been having issues where a hang in one client
> can propagate to another. In particular, a hang in an app can propagate
> to the X server which causes the
Quoting Chris Wilson (2021-03-05 12:20:45)
> Quoting Tvrtko Ursulin (2021-03-05 09:23:02)
> > I am not sure if PC8 and DMC could also be involved from what Cooper was
> > saying in a different thread. Maybe another CI run without the DMC, both
> > ffs and fls. Another
Quoting Tvrtko Ursulin (2021-03-05 09:23:02)
> I am not sure if PC8 and DMC could also be involved from what Cooper was
> saying in a different thread. Maybe another CI run without the DMC, both
> ffs and fls. Another for limiting cstates.
Disabling the dmc leaves the display code in an
Quoting Jani Nikula (2021-02-24 08:46:55)
> On Tue, 23 Feb 2021, Lucas De Marchi wrote:
> > On Tue, Feb 23, 2021 at 05:35:11PM +0200, Jani Nikula wrote:
> >>Matter of taste. STEP matches the enums.
> >>
> >>Signed-off-by: Jani Nikula
> >>---
> >>
Quoting Chris Wilson (2021-03-04 11:56:16)
> Quoting Chris Wilson (2021-03-04 09:19:24)
> > Quoting Tvrtko Ursulin (2021-03-04 09:12:26)
> > >
> > > On 02/03/2021 06:27, Cooper Chiou wrote:
> > > > WaProgramMgsrForCorrectSliceSpecificMmioReads applies f
Quoting Chris Wilson (2021-03-04 09:19:24)
> Quoting Tvrtko Ursulin (2021-03-04 09:12:26)
> >
> > On 02/03/2021 06:27, Cooper Chiou wrote:
> > > WaProgramMgsrForCorrectSliceSpecificMmioReads applies for Gen9 to
> > > resolve VP8 hardware encoding system hang u
Quoting Lionel Landwerlin (2021-03-04 09:45:47)
> On 04/03/2021 10:58, Chris Wilson wrote:
> > Quoting Lionel Landwerlin (2021-03-04 08:28:59)
> >> On 04/03/2021 02:09, Chris Wilson wrote:
> >>> Quoting Umesh Nerlige Ramappa (2021-03-03 21:28:00)
> >>>
t;
> > Reference: HSD#1508045018,1405586840, BSID#0575
> >
> > Cc: Ville Syrjälä
> > Cc: Rodrigo Vivi
> > Cc: Jani Nikula
> > Cc: Chris Wilson
> > Cc: Tvrtko Ursulin
> > Cc: William Tseng
> > Cc: Lee Shawn C
> >
> > Signed-off
Quoting Lionel Landwerlin (2021-03-04 08:28:59)
> On 04/03/2021 02:09, Chris Wilson wrote:
> > Quoting Umesh Nerlige Ramappa (2021-03-03 21:28:00)
> >> Perf measurements rely on CPU and engine timestamps to correlate
> >> events of interest across these time doma
Quoting Umesh Nerlige Ramappa (2021-03-03 21:28:00)
> Perf measurements rely on CPU and engine timestamps to correlate
> events of interest across these time domains. Current mechanisms get
> these timestamps separately and the calculated delta between these
> timestamps lack enough accuracy.
>
>
>
> v2: split context changes, fix defines and improve documentation (Chris),
> add object invalidation logic
>
> Signed-off-by: Bommu Krishnaiah
> Signed-off-by: Daniele Ceraolo Spurio
> Cc: Telukuntla Sreedhar
> Cc: Kondapally Kalyan
> Cc: Gupta Anshuman
> C
added to the RESET_STATS ioctl to report the
> invalidation to userspace.
>
> v2: split to its own patch and improve doc (Chris), invalidate contexts
> on teardown
>
> Signed-off-by: Daniele Ceraolo Spurio
> Cc: Chris Wilson
> Signed-off-by: Daniele Ceraolo Spurio
>
Quoting Daniele Ceraolo Spurio (2021-03-01 19:31:54)
> +int intel_pxp_runtime_resume(struct intel_pxp *pxp)
> +{
> + struct intel_gt *gt = pxp_to_gt(pxp);
> + int ret;
> +
> + if (!intel_pxp_is_enabled(pxp))
> + return 0;
> +
> + intel_pxp_irq_enable(pxp);
> +
Quoting Daniele Ceraolo Spurio (2021-03-01 19:31:53)
> +static int pxp_terminate(struct intel_pxp *pxp)
> +{
> + int ret = 0;
> +
> + mutex_lock(>mutex);
> +
> + pxp->global_state_attacked = true;
global_state_attacked is serialised by pxp->work
> +
> + ret =
enerate another interrupt, at
> which point it is safe to re-create the session.
Why do we do the auto recreation after the teardown interrupt?
>
> v2: use struct completion instead of bool (Chris)
>
> Signed-off-by: Huang, Sean Z
> Signed-off-by: Daniele Ceraolo Spurio
> C
Quoting Daniele Ceraolo Spurio (2021-03-01 19:31:48)
> @@ -232,6 +235,13 @@ ktime_t intel_engine_get_busy_time(struct
> intel_engine_cs *engine,
>
> u32 intel_engine_context_size(struct intel_gt *gt, u8 class);
>
> +struct intel_context *
> +intel_engine_pinned_context_create(struct
Quoting Daniele Ceraolo Spurio (2021-03-01 19:31:51)
> +static inline bool intel_pxp_is_active(const struct intel_pxp *pxp)
> +{
> + return pxp->arb_is_in_play;
> +}
> +static bool intel_pxp_session_is_in_play(struct intel_pxp *pxp, u32 id)
> +{
> + struct intel_gt *gt =
want to emit a
> teardown operation to make sure we're clean on boot and resume
>
> v2: emit in the ring, use high prio request (Chris)
>
> Signed-off-by: Huang, Sean Z
> Signed-off-by: Daniele Ceraolo Spurio
> Cc: Chris Wilson
> ---
> drivers/gpu/drm/i915/Makefil
enerate another interrupt, at
> which point it is safe to re-create the session.
>
> v2: use struct completion instead of bool (Chris)
>
> Signed-off-by: Huang, Sean Z
> Signed-off-by: Daniele Ceraolo Spurio
> Cc: Chris Wilson
> ---
> drivers/gpu/drm/i915/Makefi
Quoting Piorkowski, Piotr (2021-02-24 15:29:25)
> From: Piotr Piórkowski
>
> Until now, the gen8_ggtt_pte_encode function, responsible for the preparation
> of GGTT PTE, has not verified in any way whether the address given as the
> parameter is correct.
> By adding a GGTT address mask, we can
ikely but for
> correctness should still be handled.
>
> Signed-off-by: Tvrtko Ursulin
> Fixes: 311a50e76a33 ("drm/i915: Add support for mandatory cmdparsing")
> Cc: Jon Bloomfield
> Cc: Joonas Lahtinen
> Cc: Chris Wilson
> ---
> To catchup with referenced
the vma is included with the guard.
Signed-off-by: Chris Wilson
Cc: Ville Syrjälä
Cc: Matthew Auld
Cc: Imre Deak
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_domain.c | 13 +++
drivers/gpu/drm/i915/gt/intel_ggtt.c | 25 +-
drivers/gpu/drm
the vma is included with the guard.
Signed-off-by: Chris Wilson
Cc: Ville Syrjälä
Cc: Matthew Auld
Cc: Imre Deak
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_domain.c | 13 +++
drivers/gpu/drm/i915/gt/intel_ggtt.c | 25 +-
drivers/gpu/drm
d intel_plane_disable_noatomic(struct
> intel_crtc *crtc,
> intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe,
> false);
>
> intel_disable_plane(plane, crtc_state);
> + intel_wait_for_vblank(dev_priv, crtc->pipe);
I could only find paths here from sanitize, so it looks safe from the
p
Quoting Tvrtko Ursulin (2021-02-16 15:59:33)
>
> On 16/02/2021 12:49, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2021-02-16 10:50:50)
> >> From: Tvrtko Ursulin
> >>
> >> Test that periodic reads of engine busyness against a constant 100% load
>
not be populated on pre-g4x machines,
> in which case we just fall back to max_bpc==8 and let .compute_config()
> limit the resulting pipe_bpp further if necessary.
>
> Cc: Daniel Vetter
> Reported-by: Chris Wilson
> Signed-off-by: Ville Syrjälä
Tested-by: Chris Wilso
In light of the VT-d workarounds, we may introduce padding around the
scanout vma. This should not affect relocations referencing the scanout
on !full-ppgtt where we leak the GGTT address of scanout to users.
Signed-off-by: Chris Wilson
Cc: Matthew Auld
Reviewed-by: Matthew Auld
---
tests
Quoting Matthew Auld (2021-02-16 16:49:28)
> On Tue, 16 Feb 2021 at 14:32, Chris Wilson wrote:
> >
> > In light of the VT-d workarounds, we may introduce padding around the
> > scanout vma. This should not affect relocations referencing the scanout
> > on !full-p
In light of the VT-d workarounds, we may introduce padding around the
scanout vma. This should not affect relocations referencing the scanout
on !full-ppgtt where we leak the GGTT address of scanout to users.
Signed-off-by: Chris Wilson
Cc: Matthew Auld
---
tests/i915/gem_exec_reloc.c | 102
Quoting Tvrtko Ursulin (2021-02-16 10:50:50)
> From: Tvrtko Ursulin
>
> Test that periodic reads of engine busyness against a constant 100% load
> are within the 5000ppm tolerance when comparing perf timestamp versus
> counter values.
>
> Signed-off-by: Tvrtko Ursulin
> ---
>
Quoting Tvrtko Ursulin (2021-02-16 10:50:50)
> From: Tvrtko Ursulin
>
> Test that periodic reads of engine busyness against a constant 100% load
> are within the 5000ppm tolerance when comparing perf timestamp versus
> counter values.
>
> Signed-off-by: Tvrtko Ursulin
> ---
>
Quoting Ram Moon, AnandX (2021-02-16 12:05:23)
> Hi Chris,
>
> -Original Message-
> From: dri-devel On Behalf Of Chris
> Wilson
> Sent: Monday, February 15, 2021 6:10 PM
> To: Auld, Matthew ; Ram Moon, AnandX
> ; Surendrakumar Upadhyay, TejaskumarX
> ; Ursul
Quoting Tvrtko Ursulin (2021-02-16 10:50:50)
> From: Tvrtko Ursulin
>
> Test that periodic reads of engine busyness against a constant 100% load
> are within the 5000ppm tolerance when comparing perf timestamp versus
> counter values.
We've previously only included the accuracy tests on
checks and placement
restrictions.
v3: Fix the check on the placement upper bound. The request user offset
is relative to the guard offset (not the node.start) and so we should
not include the initial guard offset again when computing the upper
bound of the node.
Signed-off-by: Chris Wilson
Cc
Quoting Matthew Auld (2021-02-15 19:31:39)
> On Mon, 15 Feb 2021 at 18:15, Chris Wilson wrote:
> >
> > Quoting Matthew Auld (2021-02-15 18:04:08)
> > > On Mon, 15 Feb 2021 at 15:56, Chris Wilson
> > > wrote:
> > > >
> > > > Introduce th
Quoting Matthew Auld (2021-02-15 18:04:08)
> On Mon, 15 Feb 2021 at 15:56, Chris Wilson wrote:
> >
> > Introduce the concept of padding the i915_vma with guard pages before
> > and aft. The major consequence is that all ordinary uses of i915_vma
> > must use i9
Quoting Dan Carpenter (2021-02-15 15:58:27)
> If the igt_request_alloc() call fails then this should return a
> negative error code, but currently it returns success.
>
> Fixes: 85fddf0b0027 ("drm/i915: Introduce a context barrier callback")
> Signed-off-by: Dan Carpe
which is still used
by the drm_mm itself, into an adjustment of node.start at the point of
use.
v3: Pass the requested guard padding from the caller, so we can drop the
VT-d w/a knowledge from the i915_vma allocator.
Signed-off-by: Chris Wilson
Cc: Ville Syrjälä
Cc: Matthew Auld
Reviewed
otable exceptions are the selftests that are testing exact
behaviour of i915_vma_pin/i915_vma_insert.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/display/intel_fbdev.c| 6 +--
.../gpu/drm/i915/gem/i915_gem_client_blt.c| 3 +-
.../gpu/drm/i9
checks and placement
restrictions.
Signed-off-by: Chris Wilson
Cc: Matthew Auld
---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 12 ++--
drivers/gpu/drm/i915/i915_vma.c | 28 ++-
drivers/gpu/drm/i915/i915_vma.h | 5 +++--
drivers/gpu/drm/i915/i915_vma_types.h
Quoting Ram Moon, AnandX (2021-02-15 12:29:17)
> Hi Chris,
>
> -Original Message-
> From: dri-devel On Behalf Of Chris
> Wilson
> Sent: Wednesday, February 10, 2021 4:15 PM
> To: Ram Moon, AnandX ; Jani Nikula
> ; Auld, Matthew ;
> Surendrakumar Upadhya
rchi
And patch 2 answered the question of what about intel_audio_init().
Reviewed-by: Chris Wilson
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Quoting Emil Velikov (2021-02-12 15:45:04)
> On Fri, 12 Feb 2021 at 15:16, Chris Wilson wrote:
> >
> > Quoting Emil Velikov (2021-02-12 14:57:56)
> > > Hi Chris,
> > >
> > > On Thu, 4 Feb 2021 at 12:11, Chris Wilson
> > > wrote:
> >
Quoting Chris Wilson (2021-02-12 15:22:13)
> Quoting Kai Vehmanen (2021-02-12 14:53:02)
> > This reverts commit 3632610d38316bca9b0cd9d649ce3cefab58520a.
> >
> > DG1 has been supported in upstream since v5.10 with commit
> > 69b08bdfa818 ("ALSA: hda
Quoting Kai Vehmanen (2021-02-12 14:53:02)
> This reverts commit 3632610d38316bca9b0cd9d649ce3cefab58520a.
>
> DG1 has been supported in upstream since v5.10 with commit
> 69b08bdfa818 ("ALSA: hda - add Intel DG1 PCI and HDMI ids").
Exactly, otherwise this patch wouldn't have been required to
Quoting Emil Velikov (2021-02-12 14:57:56)
> Hi Chris,
>
> On Thu, 4 Feb 2021 at 12:11, Chris Wilson wrote:
> >
> > Register with /proc/gpu to provide the client runtimes for generic
> > top-like overview, e.g. gnome-system-monitor can use this information to
> &g
Since we only run test_readonly for a single sync-flag, place it in the
common block.
Signed-off-by: Chris Wilson
---
tests/i915/gem_userptr_blits.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/tests/i915/gem_userptr_blits.c b/tests/i915/gem_userptr_blits.c
index
Since we only run test_readonly for a single sync-flag, place it in the
common block.
Signed-off-by: Chris Wilson
---
tests/i915/gem_userptr_blits.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/tests/i915/gem_userptr_blits.c b/tests/i915/gem_userptr_blits.c
index
Quoting Matthew Auld (2021-02-12 13:43:46)
> On Fri, 12 Feb 2021 at 10:22, Chris Wilson wrote:
> >
> > Introduce the concept of padding the i915_vma with guard pages before
> > and aft. The major consequence is that all ordinary uses of i915_vma
> > must use i9
of a successful heartbeat. Remove it, but then put it back to handle
large mismatches between the sysfs properties and reality.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2853
Suggested-by: CQ Tang
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/gt/intel_engine_heartbeat.c | 107
which is still used
by the drm_mm itself, into an adjustment of node.start at the point of
use.
Signed-off-by: Chris Wilson
Cc: Ville Syrjälä
Cc: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_domain.c | 3 +++
drivers/gpu/drm/i915/gt/intel_ggtt.c | 25 +-
drivers/gpu
ure that the
execobj.offset is transparent and excludes the guards. (On such platforms,
without full-ppgtt, userspace has to use relocations so the presence of
more untouchable regions within its GTT such be of no further issue.)
Signed-off-by: Chris Wilson
Cc: Matthew Auld
---
drivers/gpu/drm/i915/gt/intel_ggt
otable exceptions are the selftests that are testing exact
behaviour of i915_vma_pin/i915_vma_insert.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/display/intel_fbdev.c| 6 ++--
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 29 ++-
drivers/gpu/drm/i915/gem/i915_gem_
-by: CQ Tang
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/gt/intel_engine_heartbeat.c | 92 +++---
drivers/gpu/drm/i915/gt/intel_engine_types.h | 7 ++
.../drm/i915/gt/selftest_engine_heartbeat.c | 93 ---
drivers/gpu/drm/i915/gt/selftest_execlists.c | 5 +-
4
and detection of
false/unexpected hang reports.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2853
Suggested-by: CQ Tang
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/gt/intel_engine_heartbeat.c | 107 +++---
drivers/gpu/drm/i915/gt/intel_engine_types.h | 8 ++
.../drm
Quoting Matthew Auld (2021-02-11 17:00:20)
> Throwing some color_adjust at it might be another option to consider.
> Maybe something like:
>
> +static void i915_ggtt_color_adjust_vdt(const struct drm_mm_node *node,
> + unsigned long color,
> +
Quoting Ville Syrjälä (2021-02-11 16:05:59)
> On Wed, Feb 10, 2021 at 11:39:46PM +0000, Chris Wilson wrote:
> > @@ -637,6 +642,13 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64
> > alignment, u64 flags)
> > alignment,
Quoting Matthew Auld (2021-02-11 14:25:41)
> On 10/02/2021 23:39, Chris Wilson wrote:
> > VT-d may cause overfetch of the scanout PTE, both before and after the
> > vma (depending on the scanout orientation). bspec recommends that we
> > provide a tile-row in either direction
Quoting Matthew Auld (2021-02-11 12:27:56)
> On 11/02/2021 11:20, Chris Wilson wrote:
> > If we want to track system/stolen as memory regions, we need to setup
> > our bookkeeping *before* we want to start allocating and reserving
> > objects in those regions. In particular,
and detection of
false/unexpected hang reports.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2853
Suggested-by: CQ Tang
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/gt/intel_engine_heartbeat.c | 104 +++---
drivers/gpu/drm/i915/gt/intel_engine_types.h | 8 ++
.../drm
/libyaml/blob/master/src/emitter.c
under a permissive MIT licence.
Signed-off-by: Chris Wilson
Cc: Jani Nikula
Cc: Joonas Lahtinen
---
Converting to kerneldoc is about the last major task. It uses an
opencoded stack struct which might be nice to convert to a library,
maybe just use XArray?
It has
Rather than try and allocate objects as we perform our early HW probes,
defer the allocation for GGTT objects (such as the scratch page) to later
in the initialisation.
Signed-off-by: Chris Wilson
Cc: Matthew Auld
---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 38 +++-
1
-stolen memory region beforehand.
Signed-off-by: Chris Wilson
Cc: Matthew Auld
---
drivers/gpu/drm/i915/i915_drv.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index b708517d3972..139cea4443fd 100644
Quoting Hans de Goede (2021-02-11 10:36:13)
> Hi,
>
> On 2/10/21 1:48 PM, Chris Wilson wrote:
> > Quoting Hans de Goede (2021-02-10 10:37:19)
> >> Hi,
> >>
> >> On 2/10/21 12:07 AM, Chris Wilson wrote:
> >>> Quoting Hans de Goede (2021-02-09
Quoting Rodrigo Vivi (2021-02-11 04:25:17)
> On Wed, Feb 10, 2021 at 10:19:50PM +0000, Chris Wilson wrote:
> > After calling intel_gt_suspend_prepare(), the driver starts to turn off
> > various subsystems, such as clearing the GGTT, before calling
> > intel_gt_suspend_late()
Quoting Rodrigo Vivi (2021-02-11 04:28:41)
> On Wed, Feb 10, 2021 at 10:19:51PM +0000, Chris Wilson wrote:
> > Call intel_gt_suspend_late() to disable the GT before hibernation.
> >
> > Signed-off-by: Chris Wilson
> > ---
> > drivers/gpu/drm/i915/gem/i915_gem_p
Quoting Hans de Goede (2021-02-10 10:37:19)
> Hi,
>
> On 2/10/21 12:07 AM, Chris Wilson wrote:
> > Quoting Hans de Goede (2021-02-09 11:46:46)
> >> Hi,
> >>
> >> On 2/9/21 12:27 AM, Chris Wilson wrote:
> >>> Quoting Hans de Goede (2021-02-08 2
pages around scanout, we can
avoid touching the whole GGTT. To avoid having to introduce extra nodes
around each scanout vma, we adjust the scanout drm_mm_node to be smaller
than the allocated space, and fixup the extra PTE during dma binding.
Signed-off-by: Chris Wilson
Cc: Ville Syrjälä
Cc
Check that the address we are about to write into maps into the object
to avoid stray writes into the scratch page.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm
As we mock the suspend routines to exercise suspending driver and
manipulating backing storage across the suspend, declare the suspend
target as we do.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/i915_gem.c | 40 +--
1 file changed, 30 insertions(+), 10
Periodically check, for example when idling and upon closing user
contexts, whether or not some client has written into unallocated PTE in
their ppGTT.
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
.../drm/i915/gem/selftests/i915_gem_context.c | 24 +++---
.../drm/i915/gem
Remove or hide unused debug functions from clang, or else it moans.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_sw_fence.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_sw_fence.c
b/drivers/gpu/drm/i915/i915_sw_fence.c
index
Call intel_gt_suspend_late() to disable the GT before hibernation.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_pm.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
index 000e1cd8e920
internal state to the residual GGTT addresses that
are now pointing into scratch. Let's reset the GPU to clear that
internal state as soon we have idled the GPU in prepare-to-suspend.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 5 -
1 file changed, 4 insertions(+), 1
Quoting Hans de Goede (2021-02-10 10:37:19)
> Hi,
>
> On 2/10/21 12:07 AM, Chris Wilson wrote:
> > Quoting Hans de Goede (2021-02-09 11:46:46)
> >> Hi,
> >>
> >> On 2/9/21 12:27 AM, Chris Wilson wrote:
> >>> Quoting Hans de Goede (2021-02-08 2
The surface_state_base is an offset into the batch, so we need to pass
the correct batch address for STATE_BASE_ADDRESS.
Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Prathap Kumar Valsan
Cc: Akeem G Abo
Quoting Mika Kuoppala (2021-02-10 10:50:18)
> Chris Wilson writes:
>
> > The surface_state_base is an offset into the batch, so we need to pass
> > the correct batch address for STATE_BASE_ADDRESS.
> >
> > Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3
Quoting Mika Kuoppala (2021-02-10 10:49:55)
> Chris Wilson writes:
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c
> > b/drivers/gpu/drm/i915/gt/intel_gtt.c
> > index d34770ae4c9a..5ac9eb4a3a92 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gtt.c
> &
; + return sort_clients(clients, client_cmp);
Still two calls to return sort_clients(foo, client_cmp) in this function
:) [a clients = aggregated; after processing would merge the two paths].
Reviewed-by: Chris Wilson
-Chris
___
Intel-gf
Quoting Tvrtko Ursulin (2021-02-10 10:55:44)
>
> On 10/02/2021 10:35, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2021-02-10 09:37:55)
> > Ok, that works very well. Hmm. The sort order does seem a little jumpy
> > though. May I suggest ac->id = -c->pid; instead o
Quoting Anand Moon (2021-02-10 07:59:29)
> Add check for object size to return appropriate error -E2BIG or -EINVAL
> to avoid WARM_ON and sucessfull return for some testcase.
No. You miss the point of having those warnings. We need to inspect the
code to remove the last remaining "int pagenum",
.
I'm not fond of this layout, but that's just a personal preference.
Reviewed-by: Chris Wilson
-Chris
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Quoting Tvrtko Ursulin (2021-02-10 09:37:56)
> From: Tvrtko Ursulin
>
> Show a list of supported interactive commands when pressing 'h'.
>
> Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
-Chris
___
Intel-gfx mailing
Quoting Tvrtko Ursulin (2021-02-10 09:37:55)
> +static struct clients *aggregated_clients(struct clients *clients)
> +{
> + struct client *ac, *c, *cp = NULL;
> + struct clients *aggregated;
> + int tmp, num = 0;
> +
> + /* Sort by pid first to make it easy to aggregate
The surface_state_base is an offset into the batch, so we need to pass
the correct batch address for STATE_BASE_ADDRESS.
Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Prathap Kumar Valsan
Cc: Akeem G
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