n
>; Bloomfield, Jon ;
>Charles, Daniel ; Rogozhkin, Dmitry V
>; Mateo Lozano, Oscar ;
>Gong, Zhipeng ; intel-vaapi-me...@lists.01.org;
>mesa-...@lists.freedesktop.org
Subject: [RFC 1/2] drm/i915: Engine discovery uAPI
>+u8 user_class_map[DRM_I915_ENGINE_CLASS_MAX] = {
>+ [
We have two kinds of GT4e machines:
One has the maximum frequency of 800MHZ and the actual freq only hits 600MHZ.
The other has maximum frequency of 950MHZ and the actual freq only hits only
hits 800MHZ.
Even if the gt_min_freq_mhz is set to the same value as gt_max_freq_mhz, the
actual freq cann
> On Fri, Jan 15, 2016 at 03:12:50PM +, Tvrtko Ursulin wrote:
> > From: Tvrtko Ursulin
> > + if (user_ring_id == I915_EXEC_BSD && HAS_BSD2(dev_priv)) {
> > + unsigned int bsd_idx = args->flags & I915_EXEC_BSD_MASK;
> > +
> > + if (bsd_idx == I915_EXEC_BSD_DEFAULT) {
> > +
> -Original Message-
> From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
> Sent: Thursday, January 07, 2016 3:43 PM
>
> On Thu, Jan 07, 2016 at 05:35:13AM +, Gong, Zhipeng wrote:
> > Hello
> >
> > Intel MOCS/WA registers got initialized when LR
Hello
Intel MOCS/WA registers got initialized when LR context of RCS ring is created.
When one context uses only VCS ring and LR context of RCS ring is not created,
what will the value of Intel MOCS/WA registers be? Undefined?
___
Intel-gfx mailing lis
> From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
> On Tue, Nov 03, 2015 at 01:31:22PM +, Gong, Zhipeng wrote:
> >
> > > From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
> > >
> > > Do you also have a relative perf statistics like op/s we can co
> From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
>
> Do you also have a relative perf statistics like op/s we can compare to make
> sure we aren't just stalling the whole system?
>
Could you please provide the commands about how to check it?
>
> How much cpu time is left in the i915_wait_
patch
--
BDW async 1 | 116% | 95%
BDW async 5 | 111% | 91%
> -Original Message-
> From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
> Sent: Tuesday, November 03, 2015 4:59 AM
> To: Gong, Zhipeng; intel-gfx@lis
> -Original Message-
> From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
> Sent: Monday, November 02, 2015 5:59 PM
> To: Gong, Zhipeng
> Cc: intel-gfx@lists.freedesktop.org; Rogozhkin, Dmitry V
> Subject: Re: [PATCH] RFC drm/i915: Slaughter the thundering
> i
> Sent: Saturday, October 31, 2015 6:35 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Chris Wilson; Rogozhkin, Dmitry V; Gong, Zhipeng
> Subject: [PATCH] RFC drm/i915: Slaughter the thundering i915_wait_request
> herd
>
> One particularly stressful scenario consists of
> -Original Message-
> From: Rodrigo Vivi [mailto:rodrigo.v...@gmail.com]
> Sent: Wednesday, January 21, 2015 5:49 AM
> To: Gong, Zhipeng
> Cc: intel-gfx; Vivi, Rodrigo
> Subject: Re: [Intel-gfx] [PATCH 3/3] test/gem_dummy_reloc_loop: add tests for
> dual bsd rin
> -Original Message-
> From: Rodrigo Vivi [mailto:rodrigo.v...@gmail.com]
> Sent: Wednesday, January 21, 2015 5:44 AM
> To: Gong, Zhipeng
> Cc: intel-gfx; Vivi, Rodrigo
> Subject: Re: [Intel-gfx] [PATCH 2/3] tests/gem_exec_params: check the invalid
> flags for
On Tue, 2014-12-09 at 10:46 +0100, Daniel Vetter wrote:
> On Mon, Dec 08, 2014 at 01:55:56PM -0800, Rodrigo Vivi wrote:
> > On Tue, Nov 25, 2014 at 5:04 AM, Daniel Vetter wrote:
> > > On Mon, Nov 24, 2014 at 08:29:40AM -0800, Rodrigo Vivi wrote:
> > >> From: Zhipeng Gong
> > >>
> > >> On Broadwel
>
> On Tue, Aug 05, 2014 at 03:54:04PM +0800, Zhipeng Gong wrote:
> > On Broadwell GT3 we have 2 Video Command Streamers (VCS), but
> > userspace has no control when using VCS1 or VCS2. This patch
> > introduces a mechanism to avoid the default ping-pong mode and use one
> > specific ring throu
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