[Intel-gfx] [PATCH 1/1] drm/i915: use the original Wa_14010685332 for PCH_ADP

: b8441b288d60 ("drm/i915: Tweaked Wa_14010685332 for all PCHs") Signed-off-by: James Xiong --- drivers/gpu/drm/i915/display/intel_display_power.c | 14 ++ 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/d

[Intel-gfx] [PATCH libdrm 1/1] intel: allocate the requested size when reuse is disabled

From: "Xiong, James" 1) fixed a bug: a bucket size instead of the requested was allocated even when reuse is disabled. 2) set bo_reuse explicitly Signed-off-by: Xiong, James --- intel/intel_bufmgr_gem.c | 6 +- 1 file changed, 5 insertions(+),

[Intel-gfx] [PATCH libdrm 2/5] intel: reorganize internal function

From: "Xiong, James" split drm_intel_gem_bo_alloc_internal, and add a function to search for a suitable buffer for given size for reuse. Signed-off-by: Xiong, James --- intel/intel_bufmgr_gem.c | 141 ---

[Intel-gfx] [PATCH libdrm 1/5] drm: add a macro DRMLISTFOREACHENTRYREVERSE

From: "Xiong, James" it goes through DRMLIST in a reverse order Signed-off-by: Xiong, James --- libdrm_lists.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/libdrm_lists.h b/libdrm_lists.h index 8926d8d..400c731 100644 ---

[Intel-gfx] [PATCH libdrm 0/5] improve reuse implementation

From: "Xiong, James" With gem_reuse enabled, when a buffer size is different than the sizes of buckets, it is aligned to the next bucket's size, which means about 25% more memory than the requested is allocated in the worst senario. For example: Orignal sizeActual

[Intel-gfx] [PATCH libdrm 4/5] intel: get a cached buffer by size for reuse

From: "Xiong, James" Previously all cached buffers in a given bucket were same sized, when reusing, the MRU buffer at the tail was poped out. With the new implementation, we go through the buffer list in a reverse order to search for a MRU buffer with a suitable size.

[Intel-gfx] [PATCH libdrm 5/5] intel: purge cached bucket when its cached buffer is evicted

From: "Xiong, James" Previously when a cached MRU buffer was found to be evicted by kernel, the bucket was emptied. The new implementation purged these buffers that were freed before the evicted one. Signed-off-by: Xiong, James ---

[Intel-gfx] [PATCH libdrm 3/5] intel: get a cached bucket by size

From: "Xiong, James" cached buckets are sorted by size in increasing order, each now contains cached buffers with different sizes. A buffer with size >= buckets[n].size and < buckets[n+1].size is put in bucket n for future reuse. Signed-off-by: Xiong, James

[Intel-gfx] [PATCH libdrm 1/1] intel: allocate buffer with the requested size when reuse is disabled

From: "Xiong, James" Previously a bucket size was used for buffer allocation whether bo_reuse is false or true. This patch returns NULL in function drm_intel_gem_bo_bucket_for_size() when bo_reuse is false, the original requested size is used instead. Signed-off-by:

[Intel-gfx] [PATCH 1/1] intel: align reuse buffer's size on page size instead

From: "Xiong, James" With gem_reuse enabled, when a buffer size is different than the sizes of buckets, it is aligned to the next bucket's size, which means about 25% more memory than the requested is allocated in the worst senario. For example: Orignal sizeActual

[Intel-gfx] [PATCH libdrm 2/2] intel: allocate buffer with the requested size when reuse is disabled

From: "Xiong, James" Previously a bucket size was used for buffer allocation whether bo_reuse is false or true. This patch returns NULL in function drm_intel_gem_bo_bucket_for_size() when bo_reuse is false, the original requested size is used instead. Signed-off-by:

[Intel-gfx] [PATCH libdrm 1/2] intel: align reuse buffer's size on page size instead

From: "Xiong, James" With gem_reuse enabled, when a buffer size is different than the sizes of buckets, it is aligned to the next bucket's size, which means about 25% more memory than the requested is allocated in the worst senario. For example: Orignal sizeActual

[Intel-gfx] [PATCH libdrm 0/2] improve reuse implementation

From: "Xiong, James" This series 1) align the reuse buffer size to page size instead. The goal is to reduce memory penalty (up to 25% when reuse is enabled ) while maintain similar performance. A potential overhead is: since a bucket now contains cached buffers with

[Intel-gfx] [PATCH 1/1] drm/i915: gracefully reject mmap of huge tiled objects

From: "Xiong, James" currently mmap of a tiled object that is larger than mappable aperture is rejected in fault handler, and causes sigbus error and application crash. This commit rejects it in mmap instead so that the client has chance to handle the failure.

[Intel-gfx] [PATCH 1/1] change the order to cleanup drm_property_blob after drm_crtc

From: "Xiong, James" Previously drm_mode_config_cleanup freed drm_property_blob first, then the drm_crtc which triggered unref calls to its associated drm_propery_blob, and could potentially cause memory corruption. Signed-off-by: Xiong, James ---