intel_adjusted_rate() didn't take into account src rectangle
can be less than 1 in width or height.
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/display/intel_atomic_plane.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/di
Hi Drew,
this is good find. I went looking where the problem is in and saw what
you probably also saw earlier.
I was wondering if diff below would be better fix? I assume this would
end up with einval or erange in your case but code flow otherwise would
stay as is while fixing all future cal
const struct intel_device_info adl_p_info = {
.has_3d_pipeline = 1, \
.has_64bit_reloc = 1, \
.has_flat_ccs = 1, \
+ .has_4tile = 1, \
Order look wrong, should be between has_3d_pipeline and has_64bit_reloc.
With that fixed:
Reviewed-by: Juha-Pekka Heikkila
On 20.12.2022 18.29, Stanislav Lisovskiy wrote:
We have some Tile4 tests now skipping, which were
supposed to be working. So lets make them work, by
adding display_ver 14 as supported.
v2: - Remove "14" for Tile 4 CCS formats, as they
seem to be not supported by DG2(Juha-Pekk
Hi Stan,
On 19.12.2022 15.50, Stanislav Lisovskiy wrote:
We have some Tile4 tests now skipping, which were
supposed to be working. So lets make them work, by
adding display_ver 14 as supported.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_fb.c | 8
1 fi
On 30.9.2022 14.31, Ville Syrjälä wrote:
On Fri, Sep 30, 2022 at 02:22:08PM +0300, Juha-Pekka Heikkila wrote:
I had earlier this patch which look like it does mostly the same
https://patchwork.freedesktop.org/patch/444010/?series=92491&rev=4
With exception to mc ccs, earlier Imre said mc
I had earlier this patch which look like it does mostly the same
https://patchwork.freedesktop.org/patch/444010/?series=92491&rev=4
With exception to mc ccs, earlier Imre said mc ccs must not be
considered here.
/Juha-Pekka
On 30.9.2022 13.43, Ville Syrjala wrote:
From: Ville Syrjälä
Repl
Reviewed-by: Juha-Pekka Heikkila
On 7.7.2022 15.23, Matthew Auld wrote:
This reverts commit 3cf110f8dcd1f4f02cf84339664b413abdaebf7d.
This is too big of a hammer it seems, since we can't really support
flat-CCS with lmem + smem objects, and here adding the flag means we
also attach the
Hi,
On 5.7.2022 13.28, Murthy, Arun R wrote:
On 5.7.2022 12.49, Karthik B S wrote:
On 7/5/2022 3:08 PM, Murthy, Arun R wrote:
On 6/28/2022 4:34 PM, Arun R Murthy wrote:
In oder to trigger the async flip, a dummy flip is required after
sync flip so as to update the watermarks for async in KMD
On 21.6.2022 13.53, Matthew Auld wrote:
On Mon, 20 Jun 2022 at 10:38, Juha-Pekka Heikkila
wrote:
On 10.6.2022 20.43, Matthew Auld wrote:
On Fri, 10 Jun 2022 at 15:53, Matthew Auld
wrote:
On Fri, 10 Jun 2022 at 13:12, Juha-Pekka Heikkila
wrote:
From: CQ Tang
Display might allocate a
On 10.6.2022 20.43, Matthew Auld wrote:
On Fri, 10 Jun 2022 at 15:53, Matthew Auld
wrote:
On Fri, 10 Jun 2022 at 13:12, Juha-Pekka Heikkila
wrote:
From: CQ Tang
Display might allocate a smem object and call
i915_vma_pin_iomap(), the existing code will fail.
This fix was suggested by
Hi Lakshmi,
here would be another false positive from ci. My changes are not
affecting this error with busyness on skl with igt@kms_flip@busy-flip@a-edp1
/Juha-Pekka
On 17.6.2022 13.19, Patchwork wrote:
*Patch Details*
*Series:* series starting with [1/3] drm/i915/display: Add smem fallback
Don't leak lmem mapping in vma_evict, move __i915_vma_iounmap outside
i915_vma_is_map_and_fenceable
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/i915_vma.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gp
Add fallback smem allocation for dpt if stolen memory
allocation failed.
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/display/intel_dpt.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c
b/drivers/gpu
i915_gem_object_pin_map
Signed-off-by: CQ Tang
Signed-off-by: Juha-Pekka Heikkila
Cc: Chris Wilson
Cc: Jari Tahvanainen
---
drivers/gpu/drm/i915/i915_vma.c | 33 ++---
1 file changed, 22 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_vma.c b
From: CQ Tang
Display might allocate a smem object and call
i915_vma_pin_iomap(), the existing code will fail.
This fix was suggested by Chris P Wilson, that we pin
the smem with i915_gem_object_pin_map_unlocked().
Signed-off-by: CQ Tang
Signed-off-by: Juha-Pekka Heikkila
Cc: Chris Wilson
Add fallback smem allocation for dpt if stolen memory allocation failed.
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/display/intel_dpt.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c
b/drivers/gpu
Reviewed-by: Juha-Pekka Heikkila
On 4.4.2022 16.38, Imre Deak wrote:
From: Mika Kahola
DG2 clear color render compression uses Tile4 layout. Therefore, we need
to define a new format modifier for uAPI to support clear color rendering.
v2:
Display version is fixed. [Imre]
KDoc is
Reviewed-by: Juha-Pekka Heikkila
On 4.4.2022 16.38, Imre Deak wrote:
From: Matt Roper
Add support for DG2 render and media compression, for the description of
buffer layouts see the previous patch adding the corresponding
frame buffer modifiers.
v2:
Display version fix [Imre]
v3
On 22.3.2022 17.53, Matthew Auld wrote:
On Tue, 22 Mar 2022 at 12:06, Juha-Pekka Heikkila
wrote:
On 22.3.2022 12.45, Matthew Auld wrote:
On Mon, 21 Mar 2022 at 18:36, Juha-Pekka Heikkila
wrote:
On 21.3.2022 14.29, Matthew Auld wrote:
On Fri, 18 Mar 2022 at 09:22, Juha-Pekka Heikkila
On 22.3.2022 12.45, Matthew Auld wrote:
On Mon, 21 Mar 2022 at 18:36, Juha-Pekka Heikkila
wrote:
On 21.3.2022 14.29, Matthew Auld wrote:
On Fri, 18 Mar 2022 at 09:22, Juha-Pekka Heikkila
wrote:
On 17.3.2022 13.55, Matthew Auld wrote:
On Wed, 16 Mar 2022 at 22:23, Juha-Pekka Heikkila
On 21.3.2022 14.29, Matthew Auld wrote:
On Fri, 18 Mar 2022 at 09:22, Juha-Pekka Heikkila
wrote:
On 17.3.2022 13.55, Matthew Auld wrote:
On Wed, 16 Mar 2022 at 22:23, Juha-Pekka Heikkila
wrote:
Add fallback smem allocation for dpt if stolen memory
allocation failed.
Signed-off-by: Juha
Hi Lakshmi,
here would be again false positive on glk, glk doesn't use dpt which is
changed on my patch.
/Juha-Pekka
On 17.3.2022 4.31, Patchwork wrote:
*Patch Details*
*Series:* drm/i915/display: Add smem fallback allocation for dpt
*URL:* https://patchwork.freedesktop.org/series/1014
On 17.3.2022 13.55, Matthew Auld wrote:
On Wed, 16 Mar 2022 at 22:23, Juha-Pekka Heikkila
wrote:
Add fallback smem allocation for dpt if stolen memory
allocation failed.
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/display/intel_dpt.c | 18 ++
1 file
Add fallback smem allocation for dpt if stolen memory
allocation failed.
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/display/intel_dpt.c | 18 ++
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c
b/drivers
This patch set look all ok. That failed cursor test in ci run seem to be
flip flopping on other runs too on same icl box.
Reviewed-by: Juha-Pekka Heikkila
On 2.2.2022 13.16, Ville Syrjala wrote:
From: Ville Syrjälä
We don't want any RMWs in the part of the commit that happens
under v
On 15.2.2022 20.24, Chery, Nanley G wrote:
-Original Message-
From: Juha-Pekka Heikkila
Sent: Tuesday, February 15, 2022 9:32 AM
To: Chery, Nanley G ; Nanley Chery
; C, Ramalingam
Cc: intel-gfx ; Auld, Matthew
; dri-devel
Subject: Re: [Intel-gfx] [PATCH v5 16/19] uapi/drm/dg2
On 15.2.2022 18.44, Chery, Nanley G wrote:
-Original Message-
From: Juha-Pekka Heikkila
Sent: Tuesday, February 15, 2022 8:15 AM
To: Chery, Nanley G ; Nanley Chery
; C, Ramalingam
Cc: intel-gfx ; Auld, Matthew
; dri-devel
Subject: Re: [Intel-gfx] [PATCH v5 16/19] uapi/drm/dg2
On 15.2.2022 17.02, Chery, Nanley G wrote:
-Original Message-
From: Juha-Pekka Heikkila
Sent: Tuesday, February 15, 2022 6:56 AM
To: Nanley Chery ; C, Ramalingam
Cc: intel-gfx ; Chery, Nanley G
; Auld, Matthew ; dri-
devel
Subject: Re: [Intel-gfx] [PATCH v5 16/19] uapi/drm/dg2
On 12.2.2022 3.19, Nanley Chery wrote:
On Tue, Feb 1, 2022 at 2:42 AM Ramalingam C wrote:
From: Mika Kahola
DG2 clear color render compression uses Tile4 layout. Therefore, we need
to define a new format modifier for uAPI to support clear color rendering.
v2:
Display version is fixed. [I
On 12.2.2022 3.17, Nanley Chery wrote:
On Tue, Feb 1, 2022 at 2:42 AM Ramalingam C wrote:
From: Matt Roper
DG2 unifies render compression and media compression into a single
format for the first time. The programming and buffer layout is
supposed to match compression on older gen12 platform
I didn't notice anything nag worthy, entire set look ok to me.
Reviewed-by: Juha-Pekka Heikkila
On 27.10.2021 1.50, Imre Deak wrote:
This patchset removes the CCS FB stride restrictions on ADLP. This makes
the uAPI for these FBs (via CCS modifiers) match the TGL one.
It also fixes
look ok to me.
Reviewed-by: Juha-Pekka Heikkila
On 26.10.2021 19.15, Imre Deak wrote:
To simplify the handling of modifiers on DG2 and future platforms it
makes sense to fold the modifier tiling and CCS type attributes to the
plane capabilities mask. This patchset does that, also including
On 21.10.2021 17.35, Ville Syrjälä wrote:
On Thu, Oct 21, 2021 at 07:56:24PM +0530, Ramalingam C wrote:
From: Matt Roper
DG2 unifies render compression and media compression into a single
format for the first time. The programming and buffer layout is
supposed to match compression on older ge
I did prefer v2 bit field graphics version comparison over this {from,
until} for the simple reason it had runtime just one AND instead of two
separate CMP but either way also for v3
Reviewed-by: Juha-Pekka Heikkila
On 15.10.2021 1.09, Imre Deak wrote:
Add a table describing all the
Set look all ok to me, including v2 patches.
Reviewed-by: Juha-Pekka Heikkila
On 7.10.2021 23.35, Imre Deak wrote:
This patchset adds a descriptor table for all modifiers used by i915,
which deduplicates the listing of supported modifiers during plane
initialization and during checking for a
Hi Imre,
other than that one question for this patch and one missing static
declaration what kernel test bot said about gen12_ccs_aux_stride(..)
changes look ok to me.
with those checked this series is
Reviewed-by: Juha-Pekka Heikkila
On 27.8.2021 18.09, Imre Deak wrote:
Add support for
Maybe that TODO comment could be moved into the code instead of leaving
it just into commit message?
Either way, patch look ok to me.
Reviewed-by: Juha-Pekka Heikkila
On 2.7.2021 23.46, Ville Syrjala wrote:
From: Ville Syrjälä
There's some kind of weird corner cases in FBC which req
Look ok to me.
Reviewed-by: Juha-Pekka Heikkila
On 2.7.2021 23.46, Ville Syrjala wrote:
From: Ville Syrjälä
Apply the same 512 byte FBC segment alignment to glk+ as we use
on skl+. The only real difference is that we now have a dedicated
register for the FBC override stride. Not 100% sure
skl_compute_wm_params() didn't take into account ccs modifiers
on graphics ver >= 12
v2 (Imre): Don't set rc_surface flag for mc ccs.
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/intel_pm.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git
skl_compute_plane_wm_params() didn't take into account ccs
modifiers on graphics ver >= 12
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/intel_pm.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/
CH i-g-t] [RFC] tests/kms_big_fb: Wait
for vblank before collecting CRC
Hello Juha-Pekka and Bhanu
Thank you for the review comments. Apologies Juha-Pekka, I will incorporate
your review comments and try out.
Regards
Vidya
-Original Message-----
From: Juha-Pekka Heikkila
Sent: Tuesday, June 8, 2
On 8.6.2021 10.01, Modem, Bhanuprakash wrote:
From: Intel-gfx On Behalf Of Vidya
Srinivas
Sent: Friday, May 28, 2021 9:57 AM
To: intel-gfx@lists.freedesktop.org; igt-...@lists.freedesktop.org
Cc: markyac...@chromium.org; Lin, Charlton
Subject: [Intel-gfx] [PATCH i-g-t] [RFC] tests/kms_big_fb: W
On 27.5.2021 17.31, Vidya Srinivas wrote:
Without wait for vblank, CRC mismatch is seen
between big and small CRC on some intel Gen11 platforms.
Change-Id: I3bec931aa901130997e693ac1cacf389e2a8100f
Signed-off-by: Vidya Srinivas
---
tests/kms_big_fb.c | 10 +++---
1 file changed, 7 insert
Hi Vidya,
on which machines this would help? I see there's many vblanks already
being waited. There's igt_display_commit2 which probably will block and
even if it didn't there's igt_pipe_crc_collect_crc(..) where crc
calculation is started after flip and then get one crc before disabling
crc
Reviewed-by: Juha-Pekka Heikkila
On 1.5.2021 3.28, Imre Deak wrote:
Make sure that the XYUV format is handled correctly when it's used
with a MC_CCS modifier framebuffer. Besides this format not working, the
driver will also return an incorrect error value when trying to use it,
indic
look ok to me.
Reviewed-by: Juha-Pekka Heikkila
On 21.4.2021 20.32, Imre Deak wrote:
We can handle the surface alignment of CCS and UV color planes for all
modifiers at one place, so do this. An AUX color plane can be a CCS or a
UV plane, use only the more specific query functions and remove
On 9.2.2021 17.21, Ville Syrjälä wrote:
On Tue, Feb 09, 2021 at 09:22:09AM +, Chris Wilson wrote:
Quoting Ville Syrjala (2021-02-09 02:19:16)
From: Ville Syrjälä
ilk+ planes get notably unhappy when the plane x+w exceeds
the stride. This wasn't a problem previously because we
always align
Reviewed-by: Juha-Pekka Heikkila
On 14.5.2020 18.40, Jani Nikula wrote:
Only support runtime changes through the debugfs.
i915.verbose_state_checks remains an exception, and is not exposed via
debugfs.
This depends on IGT having been updated to use the debugfs for modifying
the parameters
Reviewed-by: Juha-Pekka Heikkila
On 14.5.2020 18.40, Jani Nikula wrote:
The parameter only makes sense as a module parameter only.
Fixes: c43c5a8818d4 ("drm/i915/params: add i915 parameters to debugfs")
Cc: Juha-Pekka Heikkilä
Cc: Venkata Sandeep Dhanalakota
Signed-off-by: J
Testing part is left with TODO comment for anything older than gen5
Resend because IGT part failed.
Test-with: 20200319193644.7417-1-juhapekka.heikk...@gmail.com
Juha-Pekka Heikkila (1):
drm/i915: Allow gen11 to use over 32k long strides
drivers/gpu/drm/i915/display/intel_sprite.c | 30
The stride in bytes must not exceed the size of 8K pixels.
Linear 64 bpp pixel format maximum stride in tiles is 1024
which would mean gen11 support 64k long stride.
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/display/intel_sprite.c | 30 -
1 file changed, 24
The stride in bytes must not exceed the size of 8K pixels.
Linear 64 bpp pixel format maximum stride in tiles is 1024
which would mean gen11 support 64k long stride.
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/display/intel_sprite.c | 30 -
1 file changed, 24
Testing part is left with TODO comment for anything older than gen5
Test-with: 20200319180322.5451-1-juhapekka.heikk...@gmail.com
Juha-Pekka Heikkila (1):
drm/i915: Allow gen11 to use over 32k long strides
drivers/gpu/drm/i915/display/intel_sprite.c | 30 -
1 file changed
Reviewed-by: Juha-Pekka Heikkila
On 4.12.2019 20.05, Ville Syrjala wrote:
From: Ville Syrjälä
It's easy to confuse the drm_connector->encoder (legacy state
adjusted during modeset) and intel_connector->encoder (the statically
(sans. MST) attached encoder of the connector). For
Reviewed-by: Juha-Pekka Heikkila
On 4.12.2019 20.05, Ville Syrjala wrote:
From: Ville Syrjälä
Use the standard naming convention and rename conn_to_dig_port()
to intel_attached_dig_port().
@@
@@
- conn_to_dig_port
+ intel_attached_dig_port
(...)
{
...
}
@@
expression C
Reviewed-by: Juha-Pekka Heikkila
On 4.12.2019 20.05, Ville Syrjala wrote:
From: Ville Syrjälä
Replace the hand rolled intel_attached_dp() with the real thing.
@@
identifier F !~ "^intel_attached_dp$";
expression C;
@@
F(...)
{
<...
- enc_to_intel_dp(intel_attac
On 10.1.2020 20.32, Ville Syrjala wrote:
From: Ville Syrjälä
intel_prepare_plane_fb() will always pin plane_state->hw.fb whenever
it is present. We copy that from the master plane to the slave plane,
but we fail to copy the corresponding ggtt view. Thus when it comes time
to pin the slave plane
Look ok to me.
Reviewed-by: Juha-Pekka Heikkila
On 4.12.2019 20.05, Ville Syrjala wrote:
From: Ville Syrjälä
Lots of enc_to_foo(&encoder->base) around. Simplify by passing
in the intel_encoder instead.
@find@
identifier F =~ "^enc_to_.*";
identifier E;
@@
F(stru
On 4.11.2019 18.32, Matt Roper wrote:
On Mon, Nov 04, 2019 at 01:50:09PM +0200, Juha-Pekka Heikkila wrote:
WA2006604312 is listed for devices from Icelake onward.
The "Project" column on bspec #33450 does list EHL, however I don't see
it actually listed on the dedicated EHL
WA2006604312 is listed for devices from Icelake onward.
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display
From this set patches 2,5,6 look all ok to me.
Reviewed-by: Juha-Pekka Heikkila
On 2.10.2019 19.25, Ville Syrjala wrote:
From: Ville Syrjälä
We don't need to special case PCH vs. gen4 when setting up the LVDS
crtc_mask. Just claim pipes A|B|C work and
intel_encoder_possible_crtcs()
Reviewed-by: Juha-Pekka Heikkila
On 8.10.2019 19.14, Ville Syrjala wrote:
From: Ville Syrjälä
SNB-BDW support 10:10:10 formats on the sprite planes. Let's expose
them.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_sprite.c | 16
1 file change
Reviewed-by: Juha-Pekka Heikkila
On 8.10.2019 19.14, Ville Syrjala wrote:
From: Ville Syrjälä
ICL+ again supports alpha blending with 10bpc pixel formats.
Expose them.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_sprite.c | 6 ++
1 file changed, 6 insertions
Reviewed-by: Juha-Pekka Heikkila
On 8.10.2019 19.14, Ville Syrjala wrote:
From: Ville Syrjälä
Let's try to keep the pixel format arrays somewhat sorted:
1. RGB before YUV
2. smaller bpp before larger bpp
3. X before A
4. RGB before BGR
Signed-off-by: Ville Syrjälä
---
drivers/gp
Reviewed-by: Juha-Pekka Heikkila
On 8.10.2019 19.14, Ville Syrjala wrote:
From: Ville Syrjälä
Lots of redundant assignments inside intel_primary_plane_create().
Get rid of them.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 43 +++-
1
Reviewed-by: Juha-Pekka Heikkila
On 15.10.2019 18.27, Ville Syrjala wrote:
From: Ville Syrjälä
Unlike other planes the cursor currently handles 180 degree rotation
adjustment during the hardware programming phase. Let's move that
stuff into intel_cursor_check_surface() to match how
Reviewed-by: Juha-Pekka Heikkila
On 2.10.2019 19.25, Ville Syrjala wrote:
From: Ville Syrjälä
Replace the hand rolled stuff with drm_encoder_mask() when populating
possible_clones, and rename the function to
intel_encoder_possible_clones() to make it clear what it's used for.
Signed-o
The stride in bytes must not exceed the size of 8K pixels.
Linear 64 bpp pixel format maximum stride in tiles is 1024
which would mean gen11 support 64k long stride.
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/display/intel_sprite.c | 30 +++--
1 file
This is to test if sagv affects rotation test failures.
---
drivers/gpu/drm/i915/intel_display.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 8576a7f..c073b91 100644
--- a/drivers/gpu/drm
This patch is to test if sagv affect rotation tests. Trybot didn't
seem to honor test with tag.
Test-with: 1554056300-23473-1-git-send-email-juhapekka.heikk...@gmail.com
Juha-Pekka Heikkila (1):
drm/i915: Test. Disable sagv for testing on icl
drivers/gpu/drm/i915/intel_display.c | 5 +++
piece of code so I guess it's ok.
Reviewed-by: Juha-Pekka Heikkila
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Please ignore this. This patch is all wrong.
/Juha-Pekka
On 22.1.2019 14.41, Juha-Pekka Heikkila wrote:
Using visible plane width for testing NV12 source suitability may fail
randomly when plane is clipped.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109381
Signed-off-by: Juha
Using visible plane width for testing NV12 source suitability may fail
randomly when plane is clipped.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109381
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/intel_sprite.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion
d to me. There will be collision with my Pxxx patches if those
ever go upstream but it is issue of that time. I guess these patches
will also wait for IGT support?
Reviewed-by: Juha-Pekka Heikkila
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(1 << 21)
#define PLANE_CTL_KEY_ENABLE_DESTINATION(2 << 21)
Reviewed-by: Juha-Pekka Heikkila
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On 11.1.2019 7.30, swati2.sha...@intel.com wrote:
From: Swati Sharma
The following pixel formats are packed format that follows 4:2:2
chroma sampling. For memory represenation each component is
allocated 16 bits each. Thus each pixel occupies 32bit.
Y210: For each component, valid data occup
Primary and sprite plane enable on ILK-IVB may take two frames to complete
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103925
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/intel_display.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers
This seems to fix some DRM_FORMAT_RGB565 (up-)scaling IGT tests on on my
KBL.
Tested-by: Juha-Pekka Heikkila
On 29.10.2018 20:18, Ville Syrjala wrote:
From: Ville Syrjälä
To get the initial phase correct we need to account for the scale
factor as well. I forgot this initially and was
How is this going on, anything holding it back from getting merged ?
I'm interested in adding/using P010, [1]
Thank you,
Alex Gheorghe
[1] https://lists.freedesktop.org/archives/dri-devel/2018-August/186963.html
On Thu, Aug 30, 2018 at 03:41:11PM +0300, Juha-Pekka Heikkila wrote:
On 25.09.2018 16:35, Maarten Lankhorst wrote:
Op 05-09-18 om 16:58 schreef Ville Syrjälä:
On Mon, Aug 27, 2018 at 03:37:53PM +0300, Juha-Pekka Heikkila wrote:
From gen11 onwards RGB565 90/270 plane rotation is supported on hardware.
IGT: https://patchwork.freedesktop.org/series/48756/
Signed
On 17.09.2018 11:25, Lisovskiy, Stanislav wrote:
On Fri, 2018-09-14 at 20:05 +0300, Juha-Pekka Heikkilä wrote:
Lisovskiy, Stanislav kirjoitti 14.9.2018 klo 17.30:
On Fri, 2018-09-14 at 16:47 +0300, Ville Syrjälä wrote:
On Fri, Sep 14, 2018 at 01:36:32PM +, Lisovskiy, Stanislav
wrote:
On
On 12.09.2018 13:32, Swati Sharma wrote:
From: Vidya Srinivas
In this patch, a list for icl specific pixel formats is created
in which Y210, Y212 and Y216 pixel formats are added along with
legacy pixel formats for primary and sprite plane.
Signed-off-by: Swati Sharma
Signed-off-by: Vidya Sri
On 12.09.2018 13:32, Swati Sharma wrote:
From: Vidya Srinivas
The following pixel formats are packed format that follows 4:2:2
chroma sampling. For memory represenation each component is
allocated 16 bits each. Thus each pixel occupies a DWORD.
Just to be clear I wouldn't use 'DWORD' here but
(5 << 23)
#define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21)
#define PLANE_CTL_KEY_ENABLE_SOURCE (1 << 21)
#define PLANE_CTL_KEY_ENABLE_DESTINATION (2 << 21)
Reviewed-by: Juha-Pekka Heikkila
__
Enabling of P010, P012 and P016 formats. These formats will
extend NV12 for larger bit depths.
(Sharma, Swati2) Rename glk format table to follow similar style as on skl.
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/intel_display.c | 24 +++-
drivers/gpu/drm
Preparations for enabling P010, P012 and P016 formats. These
formats will extend NV12 for larger bit depths.
(Sharma, Swati2): removed unnecessary checks, changed debug error message
to be more generic.
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/intel_atomic.c | 3
Add needed plane control flag definitions for P010, P012 and
P016 formats.
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f232178..2c959c8
come Y plane [12:4]
followed by 2x2 subsampled Cr:Cb plane [12:4:12:4]
Add P016 definition, semi-planar yuv format where each component
is 16 bits. First come Y plane followed by 2x2 subsampled Cr:Cb
plane [16:16]
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/drm_fourcc.c | 3
On 28.08.2018 13:53, Stanislav Lisovskiy wrote:
v5: This is YUV444 packed format same as AYUV, but without alpha,
as supported by i915.
v6: Removed unneeded initializer for new XYUV format.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/drm_fourcc.c | 1 +
include/uapi/drm/drm
On 27.08.2018 14:28, Maarten Lankhorst wrote:
Op 16-08-18 om 14:55 schreef Juha-Pekka Heikkila:
Preparations for enabling P010, P012 and P016 formats. These
formats will extend NV12 for larger bit depths.
Signed-off-by: Juha-Pekka Heikkila
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm
From gen11 onwards RGB565 90/270 plane rotation is supported on hardware.
IGT: https://patchwork.freedesktop.org/series/48756/
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/intel_atomic_plane.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers
These patches enable RGB565 format to be rotated 90 and 270 degrees
on gen11 and later.
Related changes to IGT here:
https://patchwork.freedesktop.org/series/48756/
/Juha-Pekka
Juha-Pekka Heikkila (2):
drm/i915: Move 90/270 rotation validity check into its own function
drm/i915: Enable
This makes intel_plane_atomic_check_with_state() generally shorter.
v2: (Ville Syrjälä) move all rotation related checks into new function and
don't pass dev_priv pointer around.
v3: (Ville Syljälä) rename new function.
v4: rebase
Signed-off-by: Juha-Pekka Heikkila
---
driver
On 21.08.2018 17:26, Sharma, Swati2 wrote:
On 16-Aug-18 6:25 PM, Juha-Pekka Heikkila wrote:
Preparations for enabling P010, P012 and P016 formats. These
formats will extend NV12 for larger bit depths.
Signed-off-by: Juha-Pekka Heikkila
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm
Preparations for enabling P010, P012 and P016 formats. These
formats will extend NV12 for larger bit depths.
Signed-off-by: Juha-Pekka Heikkila
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_atomic.c | 3 +-
drivers/gpu/drm/i915/intel_atomic_plane.c | 2 +-
drivers/gpu
Enabling of P010, P012 and P016 formats. These formats will
extend NV12 for larger bit depths.
Signed-off-by: Juha-Pekka Heikkila
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_display.c | 24 +-
drivers/gpu/drm/i915/intel_sprite.c | 39
Add needed plane control flag definitions for P010, P012 and
P016 formats.
Signed-off-by: Juha-Pekka Heikkila
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915
come Y plane [12:4]
followed by 2x2 subsampled Cr:Cb plane [12:4:12:4]
Add P016 definition, semi-planar yuv format where each component
is 16 bits. First come Y plane followed by 2x2 subsampled Cr:Cb
plane [16:16]
Signed-off-by: Juha-Pekka Heikkila
Reviewed-by: Maarten Lankhorst
---
drivers
On 02.07.2018 17:16, StanLis wrote:
From: Stanislav Lisovskiy
PLANE_CTL_FORMAT_AYUV is already supported, according to hardware
specification.
v2: Edited commit message, removed redundant whitespaces.
v3: Fixed fallthrough logic for the format switch cases.
Signed-off-by: Stanislav Lisovskiy
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