On Tue, Sept. 15, 2020, 1:35 p.m. Ville Syrjälä wrote:
>On Tue, Sep 15, 2020 at 01:18:13PM +0000, Lee, Shawn C wrote:
>> On Fri, Sept. 11, 2020, 2:21 p.m. Ville Syrjälä wrote:
>> >On Thu, Aug 27, 2020 at 01:51:29PM +0800, Lee Shawn C wrote:
>> >> Customer repor
On Fri, Sept. 11, 2020, 2:21 p.m. Ville Syrjälä wrote:
>On Thu, Aug 27, 2020 at 01:51:29PM +0800, Lee Shawn C wrote:
>> Customer report random display flicker issue on Nightfury board.
>> And we found this problem might be caused by VT-d and FBC are both
>> enabled. Accordi
information
to disable FBC.
Cc: Ville Syrjälä
Cc: Rodrigo Vivi
Cc: Mika Kuoppala
Cc: Jani Nikula
Cc: William Tseng
Cc: Cooper Chiou
Signed-off-by: Lee Shawn C
v2: fix typo.
---
drivers/gpu/drm/i915/display/intel_fbc.c | 22 ++
1 file changed, 22 insertions(+)
diff --git
: Mika Kuoppala
Cc: Jani Nikula
Cc: William Tseng
Cc: Cooper Chiou
Signed-off-by: Lee Shawn C
---
drivers/gpu/drm/i915/display/intel_fbc.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display
Cc: Mika Kuoppala
Cc: Jani Nikula
Cc: William Tseng
Signed-off-by: Lee Shawn C
---
drivers/gpu/drm/i915/display/intel_fbc.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
index
Both VT-d and FBC enabled that caused display flicker
issue very randomly. According to sighting report,
it recommend to disable FBC to workaround this issue.
Cc: Ville Syrjälä
Cc: Rodrigo Vivi
Cc: Mika Kuoppala
Cc: Jani Nikula
Cc: William Tseng
Signed-off-by: Lee Shawn C
---
drivers/gpu
On Fri, 2020-05-22, 06:35 p.m, Lyude Paul wrote:
>On Fri, 2020-05-22 at 14:35 -0400, Lyude Paul wrote:
>>
>> On Tue, 2020-05-19 at 11:56 +0800, Lee Shawn C wrote:
>> > So far, max dot clock rate for MST mode rely on physcial bandwidth
>> > limitation. It
full_pbn.
v3: Add ctx lock.
Cc: Manasi Navare
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Cooper Chiou
Cc: Lyude Paul
Signed-off-by: Lee Shawn C
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 30 -
1 file changed, 29 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm
On Thu, May 11, 2020, Ville Syrjälä wrote:
>On Thu, May 07, 2020 at 06:46:17PM -0400, Lyude Paul wrote:
>> On Thu, 2020-04-30 at 02:37 +0000, Lee, Shawn C wrote:
>> > On Sat, 2020-04-25, Lyude Paul wrote:
>> > > Hi! Sorry this took me a little while to get back to
full_pbn.
Cc: Manasi Navare
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Cooper Chiou
Cc: Lyude Paul
Signed-off-by: Lee Shawn C
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 24 -
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/inte
On Thu, 2020-05-07, Lyude Paul wrote:
>On Thu, 2020-04-30 at 02:37 +0000, Lee, Shawn C wrote:
>> On Sat, 2020-04-25, Lyude Paul wrote:
>> > Hi! Sorry this took me a little while to get back to, I had a couple of
>> > MST regressions that I had to look into
>> &g
On Sat, 2020-04-25, Lyude Paul wrote:
>
>Hi! Sorry this took me a little while to get back to, I had a couple of MST
>regressions that I had to look into
>
>On Sat, 2020-04-18 at 05:24 +0800, Lee Shawn C wrote:
>> So far, max dot clock rate for MST mode rely on physcial ban
Cc: Ville Syrjala
Cc: Cooper Chiou
Cc: Lyude Paul
Signed-off-by: Lee Shawn C
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 24 -
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/inte
On Wed, 2020-03-11, Lyude Paul wrote:
>On Tue, 2020-01-07 at 01:41 +0800, Lee Shawn C wrote:
>> Driver report physcial bandwidth for max dot clock rate.
>> It would caused compatibility issue sometimes when physical bandwidth
>> exceed MST hub output ability.
>>
&g
ignore the bpp when its required
output bandwidth already over HDMI 2.0 or 1.4 spec.
v2: convert info->max_tmds_clock to byte clock for comparison.
Cc: Imre Deak
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Cc: Jani Nikula
Cc: Cooper Chiou
Cc: Sam McNally
Signed-off-by: Lee Shawn C
---
drivers/
ignore the bpp when its required
output bandwidth already over HDMI 2.0 or 1.4 spec.
Cc: Imre Deak
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Cc: Jani Nikula
Cc: Cooper Chiou
Cc: Sam McNally
Signed-off-by: Lee Shawn C
---
drivers/gpu/drm/i915/display/intel_dp.c | 18 ++
drivers
On Wed, 05 Feb 2020, Lee Shawn C wrote:
>While mode setting, driver would calculate mode rate based on resolution and
>bpp. And choose the best bpp that did not exceed DP bandwidtd.
>
>But LSPCON had more restriction due to it convert DP to HDMI.
>Driver should respect H
ignore the bpp when its required
output bandwidth already over HDMI 2.0 or 1.4 spec.
Cc: Imre Deak
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Cc: Jani Nikula
Cc: Cooper Chiou
Cc: Sam McNally
Signed-off-by: Lee Shawn C
---
drivers/gpu/drm/i915/display/intel_dp.c | 18 ++
drivers
to the latest available PBN. Driver will ignore the mode that over
current clock rate. And external display can works normally.
Cc: Manasi Navare
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Cooper Chiou
Signed-off-by: Lee Shawn C
v2: Add missing mutex lock.
---
drivers/gpu/drm/i915/display
On Tue, 21 Jan 2020, Jani Nikula wrote:
>On Tue, 21 Jan 2020, Lee Shawn C wrote:
>> According to chapter 5.1.1.2 in DP spec. When the Sink device
>> capability is unknown, for example due to corruption of an EDID. The
>> Source device may fall back to a set of fall-back
ignore the bpp when its required
output bandwidth already over HDMI 2.0 or 1.4 spec.
Cc: Imre Deak
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Cc: Jani Nikula
Cc: Cooper Chiou
Cc: Sam McNally
Signed-off-by: Lee Shawn C
v2: move lspcon_max_rate() into intel_lspcon.c.
v3: fix typo.
---
drivers/gpu
ignore the bpp when its required
output bandwidth already over HDMI 2.0 or 1.4 spec.
Cc: Imre Deak
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Cc: Jani Nikula
Cc: Cooper Chiou
Cc: Sam McNally
Signed-off-by: Lee Shawn C
v2: move lspcon_max_rate() into intel_lspcon.c.
---
drivers/gpu/drm/i915/display
Nikula
Cc: Cooper Chiou
Signed-off-by: Lee Shawn C
---
drivers/gpu/drm/i915/display/intel_dp.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index c27d3e7ac219..7e072db4a
On Fri, Jan 17, 2020, Ville Syrjälä wrote:
>On Fri, Jan 17, 2020 at 09:47:17PM +0800, Lee Shawn C wrote:
>> While mode setting, driver would calculate mode rate based on
>> resolution and bpp. And choose the best bpp that did not exceed DP
>> bandwidtd.
>>
>>
On Fri, 17 Jan 2020, Jani Nikula wrote:
>On Fri, 17 Jan 2020, Lee Shawn C wrote:
>> While mode setting, driver would calculate mode rate based on
>> resolution and bpp. And choose the best bpp that did not exceed DP
>> bandwidtd.
>>
>> But LSPCON had more
ignore the bpp when its required
output bandwidth already over HDMI 2.0 or 1.4 spec.
Cc: Imre Deak
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Cc: Jani Nikula
Cc: Cooper Chiou
Cc: Sam McNally
Signed-off-by: Lee Shawn C
---
drivers/gpu/drm/i915/display/intel_dp.c | 45
On Jan. 8, 2020, 3:15 p.m, Ville Syrjala wrote:
>On Tue, Jan 07, 2020 at 01:41:56AM +0800, Lee Shawn C wrote:
>> Driver report physcial bandwidth for max dot clock rate.
>> It would caused compatibility issue sometimes when physical
>> bandwidth exceed MST hub output abilit
this calculation, source calcualte max dot clock according
to available PBN. Driver will remove the mode that over current
clock rate. And external display can works normally.
Cc: Manasi Navare
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Cooper Chiou
Signed-off-by: Lee Shawn C
---
drivers/gpu/drm
dd debugfs test control
files for Displayport compliance testing")
v2: Add "Fixes" comment.
Cc: Manasi Navare
Cc: Jani Nikula
Cc: Daniel Vetter
Cc: Ville Syrjala
Cc: Cooper Chiou
Signed-off-by: Lee Shawn C
---
drivers/gpu/drm/i915/i915_debugfs.c | 4 ++--
1 file changed, 2 inser
iel Vetter
Cc: Ville Syrjala
Cc: Cooper Chiou
Signed-off-by: Lee Shawn C
---
drivers/gpu/drm/i915/i915_debugfs.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 0ac98e39eb75..74180158a
U series device need different DDI buffer setup for eDP
and DP. If driver did not recognize ULT id proerply.
The setting for H and S series would be used.
Cc: Rodrigo Vivi
Cc: Jani Nikula
Cc: Anusha Srivatsa
Cc: Cooper Chiou
Signed-off-by: Lee Shawn C
---
drivers/gpu/drm/i915/i915_pci.c
commit 'a7b4deeb02b9 ("drm/i915/cml: Add CML PCI IDS)'
introduced new PCI ID that CML support. But some PCI
IDs were removed in BSpec for CML. This patch is used
to eliminate the unsed ID.
Cc: Rodrigo Vivi
Cc: Jani Nikula
Cc: Anusha Srivatsa
Cc: Cooper Chiou
Signed-off-by: Lee Sh
.
Reported-by: Shawn Lee
Cc: Shawn Lee
Cc: Ville Syrjala
Signed-off-by: Jani Nikula
Signed-off-by: Lee Shawn C
---
drivers/gpu/drm/i915/display/intel_display_power.c | 6 ++
drivers/gpu/drm/i915/i915_drv.c| 3 ---
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git
Signed-off-by: Jani Nikula
Signed-off-by: Lee Shawn C
---
drivers/gpu/drm/i915/display/intel_display_power.c | 6 ++
drivers/gpu/drm/i915/i915_drv.c| 3 ---
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b
On Thu, Oct 31, 2019, Ville Syrjala wrote:
>On Thu, Oct 31, 2019 at 01:14:07PM +0200, Jani Nikula wrote:
>> Since CNP it's possible for rawclk to have two different values, 19.2
>> and 24 MHz. If the value indicated by SFUSE_STRAP register is
>> different from the power on default for
Cc: Lucas De Marchi
Cc: Anusha Srivatsa
Cc: Cooper Chiou
Signed-off-by: Lee Shawn C
---
drivers/gpu/drm/i915/i915_pci.c | 2 ++
drivers/gpu/drm/i915/intel_device_info.c | 2 ++
include/drm/i915_pciids.h| 20 +---
3 files changed, 17 insertions(+), 7
i
Cc: Jani Nikula
Cc: Lucas De Marchi
Cc: Anusha Srivatsa
Cc: Cooper Chiou
Signed-off-by: Lee Shawn C
---
include/drm/i915_pciids.h | 4
1 file changed, 4 deletions(-)
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index a70c982ddff9..56e823cdc717 100644
--- a/includ
Cc: Lucas De Marchi
Cc: Anusha Srivatsa
Cc: Cooper Chiou
Signed-off-by: Lee Shawn C
---
drivers/gpu/drm/i915/i915_pci.c | 2 ++
drivers/gpu/drm/i915/intel_device_info.c | 2 ++
include/drm/i915_pciids.h| 20 +---
3 files changed, 17 insertions(+), 7
i
Cc: Jani Nikula
Cc: Lucas De Marchi
Cc: Anusha Srivatsa
Cc: Cooper Chiou
Signed-off-by: Lee Shawn C
---
include/drm/i915_pciids.h | 4
1 file changed, 4 deletions(-)
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index a70c982ddff9..56e823cdc717 100644
--- a/includ
nusha Srivatsa
Cc: Cooper Chiou
Signed-off-by: Lee Shawn C
---
include/drm/i915_pciids.h | 4
1 file changed, 4 deletions(-)
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index a70c982ddff9..56e823cdc717 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pci
Chiou
Signed-off-by: Lee Shawn C
---
include/drm/i915_pciids.h | 4
1 file changed, 4 deletions(-)
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index a70c982ddff9..56e823cdc717 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -448,9 +448,7 @@
#d
Chiou
Signed-off-by: Lee Shawn C
---
drivers/gpu/drm/i915/i915_pci.c | 2 ++
drivers/gpu/drm/i915/intel_device_info.c | 2 ++
include/drm/i915_pciids.h| 20 +---
3 files changed, 17 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c
v2: remove some inaccurate descriptions.
Cc: Rodrigo Vivi
Cc: Jani Nikula
Cc: Lucas De Marchi
Cc: Anusha Srivatsa
Cc: Cooper Chiou
Signed-off-by: Lee Shawn C
---
include/drm/i915_pciids.h | 4
1 file changed, 4 deletions(-)
diff --git a/include/drm/i915_pciids.h b/include/drm
On Fri, 25 Oct 2019, Jani Nikula wrote:
>On Fri, 25 Oct 2019, Lee Shawn C wrote:
>> commit 'a7b4deeb02b9 ("drm/i915/cml: Add CML PCI IDS)'
>> introduced new PCI ID that CML support. But some sku is not support
>> yet so remove them avoid unexpected issue.
>
&g
U series device need different DDI buffer setup for eDP
and DP. If driver did not recognize ULT id proerply.
The setting for H and S series would be used.
Cc: Rodrigo Vivi
Cc: Jani Nikula
Cc: Lucas De Marchi
Cc: Anusha Srivatsa
Cc: Cooper Chiou
Signed-off-by: Lee Shawn C
---
drivers/gpu
commit 'a7b4deeb02b9 ("drm/i915/cml: Add CML PCI IDS)'
introduced new PCI ID that CML support. But some sku
is not support yet so remove them avoid unexpected issue.
Cc: Rodrigo Vivi
Cc: Jani Nikula
Cc: Lucas De Marchi
Cc: Anusha Srivatsa
Cc: Cooper Chiou
Signed-off-by: Lee Sh
On Tue, 08 Oct 2019, Jani Nikula wrote:
>On Mon, 07 Oct 2019, Adam Jackson wrote:
>> On Mon, 2019-10-07 at 12:08 +0300, Jani Nikula wrote:
>>
>>> The problem with the EDID quirks is that exposing the quirks sticks out
>>> like a sore thumb. Thus far all of it has been contained in drm_edid.c
>>>
V2: To check sink OUI instead of EDID quirk.
According to TCON's capability to decide to enable this
method for brightness control.
Cc: Jani Nikula
Cc: Adam Jackson
Cc: Maarten Lankhorst
Cc: Gustavo Padovan
Cc: Cooper Chiou
Signed-off-by: Lee Shawn C
---
drivers/gpu/drm
On Mon, 07 Oct 2019, "Jani Nikula"
mailto:jani.nik...@intel.com>> wrote:
>On Mon, 07 Oct 2019, "Lee, Shawn C"
>mailto:shawn.c@intel.com>> wrote:
>> On Fri, 04 Oct 2019, Jani Nikula
>> mailto:jani.nik...@intel.com>> wrote:
>
On Mon, 07 Oct 2019, "Jani Nikula" wrote:
>On Mon, 07 Oct 2019, "Lee, Shawn C" wrote:
>> On Fri, 04 Oct 2019, Jani Nikula wrote:
>>>On Fri, 04 Oct 2019, Adam Jackson wrote:
>>>> On Sat, 2019-10-05 at 05:58 +0800, Lee Shawn C wrote:
>>&
On Fri, 04 Oct 2019, Jani Nikula wrote:
>On Fri, 04 Oct 2019, Adam Jackson wrote:
>> On Sat, 2019-10-05 at 05:58 +0800, Lee Shawn C wrote:
>>> This panel (manufacturer is SDC, product ID is 0x4141) used
>>> manufacturer defined DPCD register to control brightness t
Cc: Jani Nikula
Cc: Maarten Lankhorst
Cc: Gustavo Padovan
Cc: Cooper Chiou
Signed-off-by: Lee Shawn C
---
drivers/gpu/drm/drm_edid.c| 6 +-
drivers/gpu/drm/i915/display/intel_dp.c | 7 +
.../drm/i915/display/intel_dp_aux_backlight.c | 143
On Tue, 25 Jun 2019, Jani Nikula wrote:
>On Mon, 17 Jun 2019, Furquan Shaikh wrote:
>> Max backlight value for the panel was being calculated using byte
>> count i.e. 0x if 2 bytes are supported for backlight brightness
>> and 0xff if 1 byte is supported. However, EDP_PWMGEN_BIT_COUNT
>>
On Tue, 25 Jun 2019, Jani Nikula wrote:
>On Tue, 25 Jun 2019, Lee Shawn C wrote:
>> Modify aux backlight enable/disable sequence just like what we did for
>> genernal eDP panel. Setup PWM freq and brightness level before enable
>> display backlight.
>&g
.
Cc: Ville Syrjälä
Cc: Jani Nikula
Cc: Jose Roberto de Souza
Cc: Cooper Chiou
Signed-off-by: Lee Shawn C
---
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
b
On Tue, 25 Jun 2019, Jani Nikula wrote:
>On Thu, 20 Jun 2019, Lee Shawn C wrote:
>> Modify aux backlight enable/disable sequence just like what we did for
>> genernal eDP panel.
>> 1. Setup PWM freq and brightness level before enable display backlight.
>> 2. Set PWM
On Tue, 25 Jun 2019, Jani Nikula wrote:
>On Thu, 20 Jun 2019, Lee Shawn C wrote:
>> If LFP backlight type setting from VBT was "VESA eDP AUX Interface".
>> Driver should check panel capability and try to initialize aux backlight.
>> No matter i915_modparams.en
Signed-off-by: Lee Shawn C
---
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 6b0b73479fb8..bbc579734238
On Fri, 21 Jun 2019, Lee Shawn C wrote:
>
>Modify aux backlight enable/disable sequence just like what we did for
>genernal eDP panel.
>1. Setup PWM freq and brightness level before enable display backlight.
>2. Set PWM to 0 after backlight enable was off.
>
>v2: Code
Syrjälä
Cc: Jani Nikula
Cc: Jose Roberto de Souza
Cc: Cooper Chiou
Signed-off-by: Lee Shawn C
---
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
b/drivers/gpu/drm
nction.
v3: 1. Modify i915.enable_dpcd_backlight type from bool to int and give default
value as 0 (disable).
2. Add a judgement to check LFP backlight type was aux interface or not.
Cc: Ville Syrjälä
Cc: Jani Nikula
Cc: Jose Roberto de Souza
Cc: Cooper Chiou
Signed-off-by: Lee Shawn C
On Wed, 19 Jun 2019, Jani Nikula wrote:
>On Wed, 19 Jun 2019, Lee Shawn C wrote:
>> If LFP backlight type setting from VBT was "VESA eDP AUX Interface".
>> Driver should check panel capability and try to initialize aux backlight.
>> No matter i915_modparams.en
n.
Cc: Ville Syrjälä
Cc: Jani Nikula
Cc: Jose Roberto de Souza
Cc: Cooper Chiou
Signed-off-by: Lee Shawn C
---
drivers/gpu/drm/i915/display/intel_bios.h | 1 +
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c | 4 +++-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --
oper Chiou
Signed-off-by: Lee, Shawn C
---
drivers/gpu/drm/i915/display/intel_bios.h | 1 +
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c | 11 ++-
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.h
b/drivers/gpu/drm/i9
On Fri, 14 Jun 2019, Jani Nikula wrote:
>On Thu, 13 Jun 2019, "Lee, Shawn C" wrote:
>> Follow generla eDP backlight enable control sequence. Add T8 (valid
>> video data to backlight enable) delay before turn backlight_enable on.
>> And T9 (backlight disable to
: Cooper Chiou
Signed-off-by: Lee, Shawn C
---
drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
index 98210ae17285..b008e887f4e9 100644
Signed-off-by: Lee, Shawn C
---
drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
index 7ded95a334db..98210ae17285 100644
--- a/drivers/gpu
On Thu, 13 Jun 2019, Jani Nikula wrote:
>On Thu, 13 Jun 2019, Ville Syrjälä wrote:
>> On Wed, Jun 12, 2019 at 10:47:22PM -0700, Lee, Shawn C wrote:
>>> Modify aux backlight enable sequence just like what we did for
>>> genernal eDP panel.
>>> 1. Setup
Modify aux backlight enable sequence just like what we
did for genernal eDP panel.
1. Setup PWM freq and brightness level before enable display backlight.
2. Add T8 (valid data to backlight enable) delay.
Cc: Jani Nikula
Cc: Jose Roberto de Souza
Cc: Cooper Chiou
Signed-off-by: Lee, Shawn C
The latest VBT support backlight control via aux. We have to
check VBT's setting before doing backlight initialization.
Then Driver will assign correct callback function for eDP
backlight control.
Cc: Jani Nikula
Cc: Jose Roberto de Souza
Cc: Cooper Chiou
Signed-off-by: Lee, Shawn C
On Wed, 21 Nov 2018, "Jani Nikula" wrote:
>On Wed, 21 Nov 2018, "Lee, Shawn C" wrote:
>> On Tue, 20 Nov 2018, "Jani Nikula" wrote:
>>>On Wed, 21 Nov 2018, "Lee, Shawn C" wrote:
>>>> On Tue, 20 Nov 2018, "J
On Tue, 20 Nov 2018, "Jani Nikula" wrote:
>On Wed, 21 Nov 2018, "Lee, Shawn C" wrote:
>> On Tue, 20 Nov 2018, "Jani Nikula" wrote:
>>>> Driver obtain power well at intel_csr_ucode_init().
>>>> And release it after load DMC firmware
firmware %s."
> " Disabling runtime power management.\n",
> csr->fw_path);
>
>We don't support runtime pm without dmc on platforms with dmc.
>
>BR,
>Jani.
>
>>
>> Cc: Jani Nikula
>> Cc: Rodrigo Vivi
>> Cc: Jose
balance.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Jose Roberto de Souza
Cc: Cooper Chiou
Signed-off-by: Lee, Shawn C
---
drivers/gpu/drm/i915/intel_csr.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index
driver to apply KBL-Y's DDI table
for AML devices to avoid unexpected eDP/DP signal quality issue.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Jose Roberto de Souza
Signed-off-by: Lee, Shawn C
---
drivers/gpu/drm/i915/intel_ddi.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
According to patch "drm/i915/aml: Introducing Amber Lake platform"
(e364672477a1). Add a new marco for AML ULX GT2 devices.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Jose Roberto de Souza
Signed-off-by: Lee, Shawn C
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
1 file changed, 2 insertion
one.
>>>
>>
>> Yes, it depends on https://patchwork.kernel.org/patch/10613643/.
>
>You need to send them together, or have that one merged first.
>
>BR,
>Jani.
>
Thanks for reminding! I will send them together in a new series later.
>>
>>>> Signe
de Souza
>
>Reviewed-by: Jose Roberto de Souza
>
>But I guess CI will fail in this patch as looks like you send the first one
>separated from this one.
>
Yes, it depends on https://patchwork.kernel.org/patch/10613643/.
>> Signed-off-by: Lee, Shawn C
>> ---
;
>> Cc: Jani Nikula
>> Cc: Rodrigo Vivi
>> Cc: Jose Roberto de Souza
>> Signed-off-by: Lee, Shawn C
>> ---
>> drivers/gpu/drm/i915/i915_drv.h | 2 ++
>> 1 file changed, 2 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
&
driver to apply KBL-Y's DDI table
for AML devices to avoid unexpected eDP/DP signal quality issue.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Jose Roberto de Souza
Signed-off-by: Lee, Shawn C
---
drivers/gpu/drm/i915/intel_ddi.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
According to patch "drm/i915/aml: Introducing Amber Lake platform"
(e364672477a1). Add a new marco for AML ULX GT2 devices.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Jose Roberto de Souza
Signed-off-by: Lee, Shawn C
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
1 file changed, 2 insertion
H/S series for AML system.
The change will lead driver to apply translation table for KBL Y for
AML device to avoid unexpected eDP/DP signal quality issue.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Jose Roberto de Souza
Signed-off-by: Lee, Shawn C
---
drivers/gpu/drm/i915/i915_drv.h | 4 +++-
1 fi
issue.
Cc: Jani Nikula
Cc: Cooper Chiou
Cc: Matt Atwood
Cc: Maarten Lankhorst
Cc: Dhinakaran Pandiyan
Cc: Clint Taylor
Lee, Shawn C (3):
drm: Add support for device_id based detection.
drm: Change limited M/N quirk to constant N quirk.
drm: add LG eDP panel to quirk database
drivers
for issue description and fix typo.
v3: add lost commit messages back for version 2
v4: send patch to both intel-gfx and dri-devel
Cc: Jani Nikula
Cc: Cooper Chiou
Cc: Matt Atwood
Cc: Maarten Lankhorst
Cc: Dhinakaran Pandiyan
Cc: Clint Taylor
Signed-off-by: Lee, Shawn C
---
drivers/gpu/drm
instead of hard coded '6'
v3: add lost commit messages back for version 2
v4: send patch to both intel-gfx and dri-devel
Cc: Jani Nikula
Cc: Cooper Chiou
Cc: Matt Atwood
Cc: Maarten Lankhorst
Cc: Dhinakaran Pandiyan
Cc: Clint Taylor
Signed-off-by: Lee, Shawn C
---
drivers/gpu/drm
Taylor
Signed-off-by: Lee, Shawn C
---
drivers/gpu/drm/drm_dp_helper.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index f3a7563eb8a1..67d683453f1c 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm
n implement some changes for branch/sink device that
>> really need additional WA.
>>
>> Cc: Jani Nikula
>> Cc: Cooper Chiou
>> Cc: Matt Atwood
>> Cc: Maarten Lankhorst
>> Cc: Dhinakaran Pandiyan
>> Cc: Clint Taylor
>> Signed-off-by: Lee,
this panel into quirk database and give particular N value when
calculate M/N divider.
Cc: Jani Nikula
Cc: Cooper Chiou
Cc: Matt Atwood
Cc: Maarten Lankhorst
Cc: Dhinakaran Pandiyan
Cc: Clint Taylor
Signed-off-by: Lee, Shawn C
---
drivers/gpu/drm/drm_dp_helper.c | 2 ++
1 file changed, 2
: Cooper Chiou
Cc: Matt Atwood
Cc: Maarten Lankhorst
Cc: Dhinakaran Pandiyan
Cc: Clint Taylor
Signed-off-by: Lee, Shawn C
---
drivers/gpu/drm/drm_dp_helper.c | 2 +-
drivers/gpu/drm/i915/intel_display.c | 26 +++---
drivers/gpu/drm/i915/intel_display.h | 2 +-
drivers
Nikula
Cc: Cooper Chiou
Cc: Matt Atwood
Cc: Maarten Lankhorst
Cc: Dhinakaran Pandiyan
Cc: Clint Taylor
Signed-off-by: Lee, Shawn C
---
drivers/gpu/drm/drm_dp_helper.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu
issue.
Cc: Jani Nikula
Cc: Cooper Chiou
Cc: Matt Atwood
Cc: Maarten Lankhorst
Cc: Dhinakaran Pandiyan
Cc: Clint Taylor
Lee, Shawn C (3):
drm: Add support for device_id based detection.
drm: Change limited M/N quirk to constant N quirk.
drm: add LG eDP panel to quirk database
drivers
tead of LIMITED_M_N and set N as 0x8000 for particular
>> branch/sink device.
>> - Fix typo.
>>
>> Cc: Jani Nikula
>> Cc: Cooper Chiou
>> Cc: Matt Atwood
>> Signed-off-by: Lee, Shawn C
>> ---
>> drivers/gpu/drm/drm_dp_helper.c | 14
this panel into quirk database and give particular N value when
calculate M/N divider.
v2:
- Use CONSTANT_N instead of LIMITED_M_N and set N as 0x8000 for particular
branch/sink device.
- Fix typo.
Cc: Jani Nikula
Cc: Cooper Chiou
Cc: Matt Atwood
Signed-off-by: Lee, Shawn C
---
drivers/gpu/drm
or said they
don't have similar issue before.
>> With the other N value, Tcon will enter BITS mode and display black screen.
>> Add this panel into quirk database and give particular N value when
>> calculate M/N divider.
>>
>> Cc: Jani Nikula
> Cc: Cooper Chiou
this panel into quirk database and give particular N value when
calculate M/N divider.
Cc: Jani Nikula
Cc: Cooper Chiou
Cc: Matt Atwood
Signed-off-by: Lee, Shawn C
---
drivers/gpu/drm/drm_dp_helper.c | 10 +-
drivers/gpu/drm/i915/intel_display.c | 16 ++--
drivers/gpu/drm
.
Cc: Matt Atwood
Signed-off-by: Lee, Shawn C
---
drivers/gpu/drm/i915/intel_dp.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 436c22de33b6..903d640fe712 100644
--- a/drivers/gpu/drm/i915
>On Tue, 26 Sep 2017, "Lee, Shawn C" <shawn.c@intel.com> wrote:
>> DP v1.3 spec reserved DPCD TRAINING_AUX_RD_INTERVAL (Eh)
>> bit7 to indicate Extended Receiver Capability. A DPRX with DPCD Rev.
>> 1.4 (or higher) must have an Extended Receiver Capa
DP v1.3 spec reserved DPCD TRAINING_AUX_RD_INTERVAL (Eh)
bit7 to indicate Extended Receiver Capability. A DPRX with DPCD
Rev. 1.4 (or higher) must have an Extended Receiver Capability field.
Driver have to clear bit7 when retrieve interval value and avoid to
wait for needless delay.
Cc: Jani
Min brightness value from vbt was missing for CNP platform.
This setting have to refer backlight ic spec to restrict
min backlight output. Without this restriction, driver would
allow to configure lower brightness value and violate
backlight ic requirement.
Fixes: 4c9f7086ac6d ("drm/i915/cnp:
No problem! I will commit a patch for CNP later.
On Tue, 12 Sep 2017, "Lee, Shawn C" <shawn.c@intel.com> wrote:
> Min brightness value from vbt was missing for BXT platform.
> This setting have to refer backlight ic spec to restrict min backlight
> output. Without
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