be over the required amount of
time (according to HW architects).
v2: Don't forget to save/restore registers used for the wait (Chris)
v3: Name used CS_GPR registers (Chris)
Fix compile issue due to rebase (Lionel)
v4: Fix save/restore helpers (Umesh)
Signed-off-by: Lionel Landw
: Use priorities to avoid preemption rather than the HW mechanism
v4: Just modify the port priority reporting function
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 8 +
drivers/gpu/drm/i915/i915_drv.h | 8 +
driver
BIT_ULL (Chris)
v6: Fix issue with already signaled timeline points,
dma_fence_chain_find_seqno() setting fence to NULL (Chris)
Signed-off-by: Lionel Landwerlin
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 297 ++
drivers/gpu/drm/i915/i915_drv.c | 4
lobal
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h | 7 +
drivers/gpu/drm/i915/i915_perf.c | 248 ---
2 files changed, 166 insertions(+), 89 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
h cpu mapping of OA config (Chris)
v3: Properly deal with the perf_metric lock (Chris/Lionel)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 +
drivers/gpu/drm/i915/i915_drv.h | 24 ++-
drivers/gpu/drm/i915/i915_p
We're planning to use this for a couple of new feature where we need
to provide additional parameters to execbuf.
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 32 ++-
include/uapi/drm/i915_
On 11/07/2019 09:29, Chris Wilson wrote:
Quoting Umesh Nerlige Ramappa (2019-07-11 00:43:21)
On Tue, Jul 09, 2019 at 03:33:44PM +0300, Lionel Landwerlin wrote:
+static u32 *save_register(struct drm_i915_private *i915, u32 *cs,
+i915_reg_t reg, u32 offset, u32
On 10/07/2019 13:55, Chris Wilson wrote:
From: Lionel Landwerlin
This was dropped from the original patch series, we weren't sure
whether it was needed at the time. More recent tests show it's
definitely needed to have acurate performance data.
Signed-off-by: Lionel Landwer
On 09/07/2019 23:30, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-07-09 13:33:38)
drm/i915/perf: ensure we keep a reference on the driver
drm/i915: enumerate scratch fields
drm/i915: add infrastructure to hold off preemption on a request
These 3 looked to be standalone, so
On 09/07/2019 15:33, Lionel Landwerlin wrote:
+static int eb_oa_config(struct i915_execbuffer *eb)
+{
+ int ret;
+
+ if (!eb->oa_config)
+ return 0;
+
+ ret = i915_mutex_lock_interruptible(&eb->i915->drm);
+ if (ret)
+ return r
uAPI.
v2: Fix sparse warnings (Lionel)
Add support to query configuration using uuid (Lionel)
v3: Fix some inconsistency in uapi header (Lionel)
Fix unlocking when not locked issue (Lionel)
Add debug messages (Lionel)
v4: Fix missing unlock (Dan)
Signed-off-by: Lionel Landw
This also allows us to significantly reduce the amount of time we hold
the main lock.
v2: Drop the global lock as much as possible
v3: Take global lock to pin global
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h | 7 +
drivers/gpu/drm/i915/i915_perf.c
Chris)
Signed-off-by: Lionel Landwerlin
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 131 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +
drivers/gpu/drm/i915/gt/intel_engine_types.h | 9 ++
drivers/gpu/drm/i915/gt/intel_lrc.c | 1 +
drivers/gpu/drm/i9
We want to set this flag in the next commit on requests containing
perf queries so that the result of the perf query can just be a delta
of global counters, rather than doing post processing of the OA
buffer.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 7
We're planning to use this for a couple of new feature where we need
to provide additional parameters to execbuf.
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 32 ++-
include/uapi/drm/i915_
BIT_ULL (Chris)
v6: Fix issue with already signaled timeline points,
dma_fence_chain_find_seqno() setting fence to NULL (Chris)
Signed-off-by: Lionel Landwerlin
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 297 ++
drivers/gpu/drm/i915/i915_drv.c | 4
: Use priorities to avoid preemption rather than the HW mechanism
v4: Just modify the port priority reporting function
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 8 +
drivers/gpu/drm/i915/i915_drv.h | 8 +
driver
be over the required amount of
time (according to HW architects).
v2: Don't forget to save/restore registers used for the wait (Chris)
v3: Name used CS_GPR registers (Chris)
Fix compile issue due to rebase (Lionel)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson
---
driver
h cpu mapping of OA config (Chris)
v3: Properly deal with the perf_metric lock (Chris/Lionel)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 +
drivers/gpu/drm/i915/i915_drv.h | 24 ++-
drivers/gpu/drm/i915/i915_p
The i915 perf stream has its own file descriptor and is tied to
reference of the driver. We haven't taken care of keep the driver
alive.
Signed-off-by: Lionel Landwerlin
Suggested-by: Chris Wilson
Fixes: eec688e1420da5 ("drm/i915: Add i915 perf infrastructure")
Reviewed-b
This was dropped from the original patch series, we weren't sure
whether it was needed at the time. More recent tests show it's
definitely needed to have acurate performance data.
Signed-off-by: Lionel Landwerlin
Fixes: 19f81df2859eb1 ("drm/i915/perf: Add OA unit support for Ge
We have a bunch of offsets in the scratch buffer. As we're about to
add some more, let's group all of the offsets in a common location.
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_gt.h | 6 +++--
drivers/gpu/drm/i915/gt/intel_
Reporting this version will help application figure out what level of
the support the running kernel provides.
v2: Add i915_perf_ioctl_version() (Chris)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.c | 3 +++
drivers/gpu/drm/i915/i915_drv.h
Hi again,
This break one of the commit in 2 so that hold preemption
infrastructure is separate from perf using the feature.
Hopefully it addresses the last bits of locking issues around OA
configurations.
Finally added the Rbs from Chris.
Thanks a lot,
Lionel Landwerlin (13):
drm/i915/perf
On 09/07/2019 13:07, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-07-09 10:32:08)
+static int query_perf_config_data(struct drm_i915_private *i915,
+ struct drm_i915_query_item *query_item,
+ bool use_uuid)
+{
+ struct
On 09/07/2019 14:04, Lionel Landwerlin wrote:
On 09/07/2019 13:02, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-07-09 10:32:07)
+static int emit_oa_config(struct drm_i915_private *i915,
+ struct i915_perf_stream *stream)
{
- u32 i;
+ struct
On 09/07/2019 14:06, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-07-09 11:59:31)
On 09/07/2019 12:58, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-07-09 10:32:05)
+static int eb_oa_config(struct i915_execbuffer *eb)
+{
+ int err;
+
+ if (!eb->oa_con
On 09/07/2019 13:02, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-07-09 10:32:07)
+static int emit_oa_config(struct drm_i915_private *i915,
+ struct i915_perf_stream *stream)
{
- u32 i;
+ struct i915_oa_config *oa_config = stream->oa_con
On 09/07/2019 12:58, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-07-09 10:32:05)
+static int eb_oa_config(struct i915_execbuffer *eb)
+{
+ int err;
+
+ if (!eb->oa_config)
+ return 0;
+
+ err = i915_active_request_set(&eb->engine->l
On 09/07/2019 13:00, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-07-09 10:32:06)
We would like to make use of perf in Vulkan. The Vulkan API is much
lower level than OpenGL, with applications directly exposed to the
concept of command buffers (pretty much equivalent to our batch
buffers
On 09/07/2019 12:53, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-07-09 10:32:02)
+static u32 *save_register(struct drm_i915_private *i915, u32 *cs,
+ i915_reg_t reg, u32 offset, u32 dword_count)
+{
+ uint32_t d;
+
+ for (d = 0; d < dword_count
uAPI.
v2: Fix sparse warnings (Lionel)
Add support to query configuration using uuid (Lionel)
v3: Fix some inconsistency in uapi header (Lionel)
Fix unlocking when not locked issue (Lionel)
Add debug messages (Lionel)
v4: Fix missing unlock (Dan)
Signed-off-by: Lionel Landw
We're planning to use this for a couple of new feature where we need
to provide additional parameters to execbuf.
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 32 ++-
include/uapi/drm/i915_
h cpu mapping of OA config (Chris)
v3: Properly deal with the perf_metric lock (Chris/Lionel)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 +
drivers/gpu/drm/i915/i915_drv.h | 24 ++-
drivers/gpu/drm/i915/i915_p
: Use priorities to avoid preemption rather than the HW mechanism
v4: Just modify the port priority reporting function
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 8 +
drivers/gpu/drm/i915/gt/intel_lrc.c | 7 -
driver
This also allows us to significantly reduce the amount of time we hold
the main lock.
v2: Drop the global lock as much as possible
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h | 7 +
drivers/gpu/drm/i915/i915_perf.c | 261 ++-
2 files changed
Signed-off-by: Lionel Landwerlin
Fixes: 19f81df2859eb1 ("drm/i915/perf: Add OA unit support for Gen 8+")
---
drivers/gpu/drm/i915/i915_perf.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_pe
g the ringbuffer (Chris)
v4: Reuse i915_user_extension_fn
Serialize requests with OA config updates
v5: Check that the chained extension is only present once (Chris)
Unpin oa_vma in main path (Chris)
v6: Use BIT_ULL (Chris)
Signed-off-by: Lionel Landwerlin
---
.../gpu/drm/i91
BIT_ULL (Chris)
v6: Fix issue with already signaled timeline points,
dma_fence_chain_find_seqno() setting fence to NULL (Chris)
Signed-off-by: Lionel Landwerlin
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 297 ++
drivers/gpu/drm/i915/i915_drv.c | 4
We have a bunch of offsets in the scratch buffer. As we're about to
add some more, let's group all of the offsets in a common location.
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_gt.h | 6 +++--
drivers/gpu/drm/i915/gt/intel_
be over the required amount of
time (according to HW architects).
v2: Don't forget to save/restore registers used for the wait (Chris)
v3: Name used CS_GPR registers (Chris)
Fix compile issue due to rebase (Lionel)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i9
Hi all,
Another iteration, I think this time it might just need some more
looking into "drm/i915/perf: execute OA configuration from command
stream".
Cheers,
Lionel Landwerlin (12):
drm/i915/perf: ensure we keep a reference on the driver
drm/i915/perf: add missing delay fo
Reporting this version will help application figure out what level of
the support the running kernel provides.
v2: Add i915_perf_ioctl_version() (Chris)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.c | 3 +++
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915
The i915 perf stream has its own file descriptor and is tied to
reference of the driver. We haven't taken care of keep the driver
alive.
Signed-off-by: Lionel Landwerlin
Suggested-by: Chris Wilson
Fixes: eec688e1420da5 ("drm/i915: Add i915 perf infrastructure")
---
drive
On 01/07/2019 17:37, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-07-01 13:10:53)
On 01/07/2019 15:03, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-07-01 12:34:35)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index
On 01/07/2019 18:09, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-07-01 12:34:29)
struct i915_oa_config {
+ struct drm_i915_private *i915;
+
char uuid[UUID_STRING_LEN + 1];
int id;
@@ -1110,6 +1112,10 @@ struct i915_oa_config {
struct attribute
Looks good, probably best to have someone more familiar with the i915
codebase look at it too.
Thanks a bunch!
Reviewed-by: Lionel Landwerlin
On 05/07/2019 16:16, Chris Wilson wrote:
Avoid a global idle barrier by reconfiguring each context by rewriting
them with MI_STORE_DWORD from the
On 05/07/2019 15:54, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-07-05 13:42:51)
Wow nice. I didn't have the courage to actually write it, knowing how
easy it could be to screw an offset and write at random in GGTT...
I only have one concern below.
Thanks a lot,
-Lionel
On
On 05/07/2019 15:42, Lionel Landwerlin wrote:
+
+static int
+gen8_store_flex(struct i915_request *rq,
+ struct intel_context *ce,
+ const struct flex *flex, unsigned int count)
+{
+ u32 offset;
+ u32 *cs;
+
+ cs = intel_ring_begin(rq, 4 * count);
+ if (IS_ERR(cs
xt by rewriting
them with MI_STORE_DWORD from the kernel context.
Signed-off-by: Chris Wilson
Cc: Lionel Landwerlin
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +
drivers/gpu/drm/i915/gt/intel_lrc.c | 7 +-
drivers/gpu/drm/i915/i915_perf.c
On 03/07/2019 11:56, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-07-01 12:34:33)
+ syncobj = drm_syncobj_find(eb->file, user_fence.handle);
+ if (!syncobj) {
+ DRM_DEBUG("Invalid syncobj handle provided\n");
+
On 02/07/2019 15:30, Mika Kuoppala wrote:
Lionel Landwerlin writes:
The same tests failing on CFL+ platforms are also failing on ICL.
Documentation doesn't list the
WaAllowPMDepthAndInvocationCountAccessFromUMD workaround for ICL but
applying it fixes the same tests as CFL.
Didn't
On 01/07/2019 18:17, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-07-01 12:34:32)
We're planning to use this for a couple of new feature where we need
to provide additional parameters to execbuf.
Signed-off-by: Lionel Landwerlin
Looks ok, are you convinced by I915_EXEC_EXT? It do
On 01/07/2019 16:06, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-07-01 12:34:29)
@@ -2535,9 +2635,21 @@ static int i915_perf_release(struct inode *inode, struct
file *file)
{
struct i915_perf_stream *stream = file->private_data;
struct drm_i915_private *dev_p
On 01/07/2019 16:32, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-07-01 12:34:36)
@@ -1860,23 +1893,55 @@ static int alloc_noa_wait(struct drm_i915_private *i915)
return ret;
}
-static void config_oa_regs(struct drm_i915_private *dev_priv,
- const
On 01/07/2019 16:18, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-07-01 12:34:33)
+ /*
+* For timeline syncobjs we need to preallocate chains for
+* later signaling.
+*/
+ if (point != 0 && user_fen
On 01/07/2019 16:13, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-07-01 12:34:33)
struct i915_execbuffer {
struct drm_i915_private *i915; /** i915 backpointer */
struct drm_file *file; /** per-file lookup tables and limits */
@@ -275,6 +282,7 @@ struct i915_execbuffer
On 01/07/2019 15:43, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-07-01 12:34:31)
NOA configuration take some amount of time to apply. That amount of
time depends on the size of the GT. There is no documented time for
this. For example, past experimentations with powergating
On 01/07/2019 15:05, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-07-01 12:34:34)
+static int eb_oa_config(struct i915_execbuffer *eb)
+{
+ int err;
+
+ if (!eb->oa_config)
+ return 0;
+
+ err = i915_active_request_set(&eb->engine->l
On 01/07/2019 15:03, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-07-01 12:34:35)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index f92bace9caff..012d6d7f54e2 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
Reporting this version will help application figure out what level of
the support the running kernel provides.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.c | 3 +++
include/uapi/drm/i915_drm.h | 21 +
2 files changed, 24 insertions(+)
diff --git
: Lionel Landwerlin
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 288 ++
drivers/gpu/drm/i915/i915_drv.c | 4 +-
include/uapi/drm/i915_drm.h | 38 +++
3 files changed, 273 insertions(+), 57 deletions(-)
diff --git a/drivers/gpu/drm/i915
This also allows us to significantly reduce the amount of time we hold
the main lock.
v2: Drop the global lock as much as possible
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h | 7 +
drivers/gpu/drm/i915/i915_perf.c | 261 ++-
2 files changed
Signed-off-by: Lionel Landwerlin
Fixes: 19f81df2859eb1 ("drm/i915/perf: Add OA unit support for Gen 8+")
---
drivers/gpu/drm/i915/i915_perf.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_pe
* Prevent structure to be listed more than once in execbuffer
extension chain
Many thanks to Chris for his comments.
Cheers,
Lionel Landwerlin (11):
drm/i915/perf: add missing delay for OA muxes configuration
drm/i915/perf: introduce a versioning of the i915-perf uapi
drm/i915/perf
We have a bunch of offsets in the scratch buffer. As we're about to
add some more, let's group all of the offsets in a common location.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/gt/intel_gt.h | 6 +++--
drivers/gpu/drm/i915/gt/intel_gt_type
: Use priorities to avoid preemption rather than the HW mechanism
v4: Just modify the port priority reporting function
Signed-off-by: Lionel Landwerlin
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 8 +++
drivers/gpu/drm/i915/gt/intel_lrc.c | 7 +-
drivers/gpu/drm/i915/i915_
uAPI.
v2: Fix sparse warnings (Lionel)
Add support to query configuration using uuid (Lionel)
v3: Fix some inconsistency in uapi header (Lionel)
Fix unlocking when not locked issue (Lionel)
Add debug messages (Lionel)
v4: Fix missing unlock (Dan)
Signed-off-by: Lionel Landw
g the ringbuffer (Chris)
v4: Reuse i915_user_extension_fn
Serialize requests with OA config updates
v5: Check that the chained extension is only present once (Chris)
Unpin oa_vma in main path (Chris)
Signed-off-by: Lionel Landwerlin
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c
h cpu mapping of OA config (Chris)
v3: Properly deal with the perf_metric lock (Chris/Lionel)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 +
drivers/gpu/drm/i915/i915_drv.h | 24 ++-
drivers/gpu/drm/i915/i915_perf.c
be over the required amount of
time (according to HW architects).
v2: Don't forget to save/restore registers used for the wait (Chris)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 24 ++
drivers/gpu/drm/i915/gt/intel_gt_types.h | 5 +
driver
We're planning to use this for a couple of new feature where we need
to provide additional parameters to execbuf.
Signed-off-by: Lionel Landwerlin
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 32 ++-
include/uapi/drm/i915_drm.h | 25 +
Ship it!
On 29/06/2019 16:13, Chris Wilson wrote:
From: Lionel Landwerlin
When a register is readonly there is not much we can tell about its
value (apart from its default value?). This can be covered by tests
exercising the value of the register from userspace.
For PS_INVOCATION_COUNT we&#x
Okay to land?
-Lionel
On 29/06/2019 06:33, Patchwork wrote:
== Series Details ==
Series: drm/i915: CTS fixes (rev7)
URL : https://patchwork.freedesktop.org/series/62437/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6380_full -> Patchwork_13469_full
===
-GL45.pipeline_statistics_query_tests_ARB.functional_fragment_shader_invocations
Vulkan CTS tests :
dEQP-VK.query_pool.statistics_query.fragment_shader_invocations.*
Signed-off-by: Lionel Landwerlin
Fixes: 86554f48e511 ("drm/i915/selftests: Verify whitelist of context
registers")
---
drivers/
The same tests failing on CFL+ platforms are also failing on ICL.
Documentation doesn't list the
WaAllowPMDepthAndInvocationCountAccessFromUMD workaround for ICL but
applying it fixes the same tests as CFL.
v2: Use only one whitelist entry (Lionel)
Signed-off-by: Lionel Landwerlin
Test
Anuj tested the update to the ICL whitelist. We need a good soul to
either Rb/Ack the rest.
Thanks,
Lionel Landwerlin (3):
drm/i915: fix whitelist selftests with readonly registers
drm/i915: whitelist PS_(DEPTH|INVOCATION)_COUNT
drm/i915/icl: whitelist PS_(DEPTH|INVOCATION)_COUNT
drivers
dEQP-VK.query_pool.statistics_query.fragment_shader_invocations.* (Vulkan)
v2: Only use one whitelist entry (Lionel)
Signed-off-by: Lionel Landwerlin
Cc: sta...@vger.kernel.org
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workaroun
On 27/06/2019 14:53, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-06-27 10:01:15)
CFL:C0+ changed the status of those registers which are now
blacklisted by default.
This is breaking a number of CTS tests on GL & Vulkan :
KHR-
On 27/06/2019 13:02, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-06-27 09:00:44)
We can't run into issues with doing writing the global OA/NOA
registers configuration from CPU so far, but HW engineers actually
recommend doing this from the command streamer.
Since we have a co
deem it necessarily to
disable preemption, for instance.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Mika Kuoppala
Cc: Lionel Landwerlin
Description sounds like what I'm looking for for perf queries with
global counters.
Acked-by: Lionel Landwerlin
---
drivers/gpu/drm/i9
On 27/06/2019 12:53, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-06-27 09:00:43)
We would like to make use of perf in Vulkan. The Vulkan API is much
lower level than OpenGL, with applications directly exposed to the
concept of command buffers (pretty much equivalent to our batch
buffers
On 27/06/2019 15:53, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-06-27 13:32:13)
On 27/06/2019 12:45, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-06-27 09:00:42)
+ /*
+* If the config hasn't changed, skip reconfiguring the HW (this is
+* subject
On 27/06/2019 12:45, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-06-27 09:00:42)
We want the ability to dispatch a set of command buffer to the
hardware, each with a different OA configuration. To achieve this, we
reuse a couple of fields from the execbuf2 struct (I CAN HAZ
execbuf3
So this time it passes...
Do we have flaky reads of the whitelist?
-Lionel
On 27/06/2019 13:38, Patchwork wrote:
== Series Details ==
Series: drm/i915: CTS fixes (rev6)
URL : https://patchwork.freedesktop.org/series/62437/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6373
On 27/06/2019 12:19, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-06-27 09:00:42)
+static int
+get_execbuf_oa_config(struct drm_i915_private *dev_priv,
+ s32 perf_fd, u64 oa_config_id,
+ struct i915_oa_config **out_oa_config
On 27/06/2019 13:59, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-06-27 11:49:56)
Thanks a lot for your comments.
On 27/06/2019 12:15, Chris Wilson wrote:
+ syncobj = drm_syncobj_find(eb->file, user_fence.handle);
+ if (!sync
On 27/06/2019 13:43, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-06-27 11:39:24)
On 27/06/2019 13:21, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-06-27 09:03:37)
Hi,
This revision gets rid of the synchronous wait. We now implement the
synchronous wait as part of the userspace
Thanks a lot for your comments.
On 27/06/2019 12:15, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-06-27 09:00:41)
Introduces a new parameters to execbuf so that we can specify syncobj
handles as well as timeline points.
v2: Reuse i915_user_extension_fn
Signed-off-by: Lionel Landwerlin
On 27/06/2019 13:21, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-06-27 09:03:37)
Hi,
This revision gets rid of the synchronous wait. We now implement the
synchronous wait as part of the userspace driver. A thread is spawned
for each engine and waits for availability of the syncobjs
-GL45.pipeline_statistics_query_tests_ARB.functional_fragment_shader_invocations
Vulkan CTS tests :
dEQP-VK.query_pool.statistics_query.fragment_shader_invocations.*
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/gt/selftest_workarounds.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i9
Hi,
I realized the register are next to one another, so we can use only
one entry to whitelist the 4 of them.
Cheers,
Lionel Landwerlin (3):
drm/i915: fix whitelist selftests with readonly registers
drm/i915: whitelist PS_(DEPTH|INVOCATION)_COUNT
drm/i915/icl: whitelist PS_(DEPTH
dEQP-VK.query_pool.statistics_query.fragment_shader_invocations.* (Vulkan)
v2: Only use one whitelist entry (Lionel)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i91
The same tests failing on CFL+ platforms are also failing on ICL.
Documentation doesn't list the
WaAllowPMDepthAndInvocationCountAccessFromUMD workaround for ICL but
applying it fixes the same tests as CFL.
v2: Use only one whitelist entry (Lionel)
Signed-off-by: Lionel Landwerlin
---
dr
On 27/06/2019 11:27, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-06-27 09:00:39)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 2f1dc9be3bfb..b2f5ba87921c 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
On 27/06/2019 11:07, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-06-27 09:00:36)
Signed-off-by: Lionel Landwerlin
Fixes: 19f81df2859eb1 ("drm/i915/perf: Add OA unit support for Gen 8+")
---
drivers/gpu/drm/i915/i915_perf.c | 23 +++
1 file changed, 23
Introduces a new parameters to execbuf so that we can specify syncobj
handles as well as timeline points.
v2: Reuse i915_user_extension_fn
Signed-off-by: Lionel Landwerlin
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 280 ++
drivers/gpu/drm/i915/i915_drv.c
We're planning to use this for a couple of new feature where we need
to provide additional parameters to execbuf.
Signed-off-by: Lionel Landwerlin
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 30 ++-
include/uapi/drm/i915_drm.h | 25 ++
Hi,
This revision gets rid of the synchronous wait. We now implement the
synchronous wait as part of the userspace driver. A thread is spawned
for each engine and waits for availability of the syncobjs before
calling into execbuffer.
Cheers,
Lionel Landwerlin (2):
drm/i915: introduce a
igned-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 203 +++
1 file changed, 100 insertions(+), 103 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index bf4f5fee6764..7e636463e1f5 100644
--- a/drivers/gp
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