Is there anyone with spare time to review this patch?
It's kind of required for userspace to make sense of timestamps on CNL.
Thanks a lot,
-
Lionel
On 02/11/17 16:29, Lionel Landwerlin wrote:
We use to have this fixed per generation, but starting with CNL userspace
cannot tell just of
On 08/11/17 19:14, Chris Wilson wrote:
+/*
+ * Different engines serve different roles, and there may be more than one
+ * engine serving each role. enum drm_i915_gem_engine_class provides a
+ * classification of the role of the engine, which may be used when requesting
+ * operations to be pe
On 09/11/17 11:13, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2017-11-09 10:04:17)
On 09/11/2017 09:37, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2017-11-09 09:27:33)
On 09/11/2017 09:13, Lionel Landwerlin wrote:
On 08/11/17 19:14, Chris Wilson wrote:
+/*
+ * Different engines serve
With the GPUTop bits wired, here are some mugshots of a set of NUCs I
have running nearby (KBL/SKL/APL) :
https://imgur.com/a/uHzJc
On 08/11/17 16:22, Lionel Landwerlin wrote:
Hi,
This series is based off work that Tvrtko started, initially for
exposing the engines available to userspace
On 09/11/17 11:58, Sagar Arun Kamble wrote:
On 11/2/2017 9:59 PM, Lionel Landwerlin wrote:
We use to have this fixed per generation, but starting with CNL
userspace
cannot tell just off the PCI ID. Let's make this information
available. This
is particularly useful for performance monit
On 09/11/17 14:06, Lionel Landwerlin wrote:
+ } else if (INTEL_GEN(dev_priv) <= 9) {
+ u32 ctc_reg = I915_READ(GEN8_CTC_MODE);
+ u64 freq = 0;
+
+ if ((ctc_reg & GEN8_CTC_SOURCE_PARAMETER_MASK) ==
GEN8_CTC_SOURCE_DIVIDE_LOGIC)
+
On 09/11/17 15:57, Joonas Lahtinen wrote:
On Wed, 2017-11-08 at 16:22 +, Lionel Landwerlin wrote:
From: Tvrtko Ursulin
Query info uAPI allows userspace to probe for a number of properties
of the GPU. This partially removes the need for userspace to maintain
the internal PCI id based
On 09/11/17 14:13, Lionel Landwerlin wrote:
On 09/11/17 14:06, Lionel Landwerlin wrote:
+ } else if (INTEL_GEN(dev_priv) <= 9) {
+ u32 ctc_reg = I915_READ(GEN8_CTC_MODE);
+ u64 freq = 0;
+
+ if ((ctc_reg & GEN8_CTC_SOURCE_PARAMETER_MASK) ==
GEN8_CTC_SOURCE_DIVID
On 09/11/17 21:29, Chris Wilson wrote:
Quoting Lionel Landwerlin (2017-11-09 09:13:03)
On 08/11/17 19:14, Chris Wilson wrote:
+/*
+ * Different engines serve different roles, and there may be more than one
+ * engine serving each role. enum drm_i915_gem_engine_class provides a
Reviewed-by: Lionel Landwerlin
On 10/11/17 13:19, Chris Wilson wrote:
From: Tvrtko Ursulin
We want to be able to report back to userspace details about an engine's
class, and in return for userspace to be able to request actions
regarding certain classes of engines. To isolate the uABI
On 10/11/17 11:11, Matthew Auld wrote:
On 2 November 2017 at 16:29, Lionel Landwerlin
wrote:
This name was added with the whitelisting of registers for building up OA
configs. It is contained in a range gen8 whitelist :
addr >= RPM_CONFIG0.reg && addr <= NOA_CONFIG(8).reg
On 09/11/17 17:34, Tvrtko Ursulin wrote:
On 08/11/2017 16:22, Lionel Landwerlin wrote:
With the introduction of asymetric slices in CNL, we cannot rely on
the previous SUBSLICE_MASK getparam. Here we introduce a more detailed
way of querying the Gen's GPU topology that doesn't
On 10/11/17 16:47, Chris Wilson wrote:
Quoting Lionel Landwerlin (2017-11-10 16:37:33)
On 09/11/17 17:34, Tvrtko Ursulin wrote:
On 08/11/2017 16:22, Lionel Landwerlin wrote:
But in general would it be feasible to define and name the returned
data more precisely? Like:
struct
We can enable GT3 as well as GT2.
Signed-off-by: Lionel Landwerlin
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_oa_cflgt3.c | 109 ++
drivers/gpu/drm/i915
This name was added with the whitelisting of registers for building up OA
configs. It is contained in a range gen8 whitelist :
addr >= RPM_CONFIG0.reg && addr <= NOA_CONFIG(8).reg
Hence why the name isn't used anywhere.
v2: Fix register name again RPC->RCP (Matthew)
in a different series.
Cheers,
Lionel Landwerlin (7):
drm/i915/perf: complete whitelisting for OA programming on HSW
drm/i915/perf: add support for Coffeelake GT3
drm/i915/perf: refactor perf setup
drm/i915: fix register naming
drm/i915/perf: enable perf support on CNL
drm/i915: e
eline
statistics in both GL & Vulkan as well as OA reports).
v2: Use variables for 24MHz/19.2MHz values (Ewelina)
Renamed function & coding style (Sagar)
v3: Fix frequency read on Broadwell (Sagar)
Fix missing divide by 4 on <= gen4 (Sagar)
Signed-off-by: Lionel Landwerlin
T
We were missing some registers and also can name one for which we only had
the offset.
Signed-off-by: Lionel Landwerlin
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_perf.c | 3 ++-
drivers/gpu/drm/i915/i915_reg.h | 14 ++
2 files changed, 16 insertions(+), 1 deletion
Now that we have this stored in the device info, we can drop it from perf
part of the driver.
Note that this requires to init perf after we've computed the frequency,
hence why we move i915_perf_init() from i915_driver_init_early() to after
intel_device_info_runtime_init().
Signed-off-by: L
Gen8/9 aren't very different and we can merge some of this code.
Signed-off-by: Lionel Landwerlin
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_perf.c | 48 +---
1 file changed, 25 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm
This adds new registers to the whitelist to configs emitted from userspace.
Signed-off-by: Lionel Landwerlin
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/i915_oa_cnl.c | 121 +
drivers/gpu/drm/i915
On 10/11/17 21:26, Eric Anholt wrote:
Tested by dropping garbage in my libdrm's headers and rebuilding.
Signed-off-by: Eric Anholt
---
lib/Makefile.am | 5 -
meson.build | 2 +-
tests/Makefile.am | 1 +
3 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/lib/Makefile
goal, patch 1 is :
Reviewed-by: Lionel Landwerlin
-
Lionel
On 10/11/17 21:26, Eric Anholt wrote:
This series imports the UAPI headers from Linux, like we've been doing
in Mesa for vc4 and i965. The advantage is that it lets you build new
kernel UAPI and testcases together, without need
On 13/11/17 09:14, Tvrtko Ursulin wrote:
On 10/11/2017 18:29, Lionel Landwerlin wrote:
On 10/11/17 16:47, Chris Wilson wrote:
Quoting Lionel Landwerlin (2017-11-10 16:37:33)
On 09/11/17 17:34, Tvrtko Ursulin wrote:
On 08/11/2017 16:22, Lionel Landwerlin wrote:
But in general would it be
On 13/11/17 11:40, Chris Wilson wrote:
Quoting Lionel Landwerlin (2017-11-10 19:08:39)
We were missing some registers and also can name one for which we only had
the offset.
Signed-off-by: Lionel Landwerlin
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_perf.c | 3 ++-
drivers
On 10/11/17 21:00, Chris Wilson wrote:
Quoting Lionel Landwerlin (2017-11-10 19:08:45)
@@ -3528,7 +3502,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
spin_lock_init(&dev_priv->perf.oa.oa_buffer.ptr_lock);
oa_sample_rate_har
This replaces accesses to the reg field of the i915_reg_t structure
with the i915_mmio_reg_offset() inline function.
Suggested-by: Chris Wilson
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 39 ---
1 file changed, 24 insertions
This series contains a resend of the last patch that didn't get a
reviewed-by in https://patchwork.freedesktop.org/series/33631/ and
also a suggestion by Chris.
Cheers,
Lionel Landwerlin (2):
drm/i915/perf: reuse timestamp frequency from device info
drm/i915/perf: replace .reg accesses
Now that we have this stored in the device info, we can drop it from perf
part of the driver.
Note that this requires to init perf after we've computed the frequency,
hence why we move i915_perf_init() from i915_driver_init_early() to after
intel_device_info_runtime_init().
Signed-off-by: L
Another round of issues reported mostly by Matthew.
Thanks,
Lionel Landwerlin (4):
drm/i915/perf: reuse timestamp frequency from device info
drm/i915/perf: replace .reg accesses with i915_mmio_reg_offset
drm/i915: fix 64bit divide
drm/i915/cnl: only divide up base frequency with crystal
This replaces accesses to the reg field of the i915_reg_t structure
with the i915_mmio_reg_offset() inline function.
Suggested-by: Chris Wilson
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 39 ---
1 file changed, 24 insertions
We apply this logic to Gen9 as well. We didn't notice this issue as
most part we've encountered so far only use the crystal as source for
their timestamp registers.
Fixes: dab9178333 ("drm/i915: expose command stream timestamp frequency to
userspace")
Signed-off-b
v_u64 (Chris)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.c | 4 ++--
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/i915_perf.c | 32 +++-
3 files changed, 5 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_dr
to
userspace")
Reported-by: Matthew Auld
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/intel_device_info.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index 78b
On 13/11/17 18:44, Matthew Auld wrote:
On 13 November 2017 at 18:19, Lionel Landwerlin
wrote:
ERROR: "__udivdi3" [drivers/gpu/drm/i915/i915.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/i915/i915.ko] undefined!
We can also drop an if() as we divide by (value + 1) on
ab9178333 ("drm/i915: expose command stream timestamp frequency to
userspace")
Reported-by: Matthew Auld
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_debugfs.c | 4 ++--
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h
We apply this logic to Gen9 as well. We didn't notice this issue as
most part we've encountered so far only use the crystal as source for
their timestamp registers.
Fixes: dab9178333 ("drm/i915: expose command stream timestamp frequency to
userspace")
Signed-off-b
v_u64 (Chris)
v3: Drop u64 divs by switching to kHz (Chris/Ville)
Move i915_perf_fini to i915_driver_cleanup_hw (Matthew)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.c | 7 ---
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/i915_perf.c
This replaces accesses to the reg field of the i915_reg_t structure
with the i915_mmio_reg_offset() inline function.
Suggested-by: Chris Wilson
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 39 ---
1 file changed, 24 insertions
Some sensible changes pointed by Chris, Matt & Ville.
Thanks!
Lionel Landwerlin (4):
drm/i915/perf: replace .reg accesses with i915_mmio_reg_offset
drm/i915: fix 64bit divide
drm/i915/perf: reuse timestamp frequency from device info
drm/i915/cnl: only divide up base frequency
Now that we have that information in topology fields, let's just reused it.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_debugfs.c | 26 ++
1 file changed, 10 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/dr
Hi all,
Based on feedback on previous series by Tvrtko & myself, here is a
series that exposes EU topology & engines availability through sysfs.
Cheers,
Lionel Landwerlin (4):
drm/i915: store all subslice masks
drm/i915/debugfs: reuse max slice/subslices already stored in sseu
slices.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_debugfs.c | 24 +++--
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 23 -
drivers/gpu/drm/i915/intel_device_info.c | 169 ++-
drivers/gpu/drm
abled_mask
Each enabled_mask file gives us a mask of the enabled units :
$ cat /sys/devices/pci\:00/\:00\:02.0/drm/card0/topology/enabled_mask
0x7
$ cat
/sys/devices/pci\:00/\:00\:02.0/drm/card0/topology/slice0/subslice2/enabled_mask
0xff
Signed-off-by: Lionel Landwerlin
---
drive
│ ├── class
│ └── instance
└── vecs0
├── class
└── instance
Further capabilities can be added later as attributes of each engine.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_sysfs.c | 92
On 17/11/17 09:37, Tvrtko Ursulin wrote:
On 16/11/2017 16:00, Lionel Landwerlin wrote:
With the introduction of asymetric slices in CNL, we cannot rely on
the previous SUBSLICE_MASK getparam. Here we introduce a more detailed
way of querying the Gen's GPU topology that doesn't
On 17/11/17 09:51, Tvrtko Ursulin wrote:
On 16/11/2017 16:00, Lionel Landwerlin wrote:
This enables userspace to discover the engines available on the GPU.
Here is the layout :
/sys/devices/pci:00/:00:02.0/drm/card0/engines
├── bcs0
│ ├── class
│ └── instance
├── rcs0
On 17/11/17 10:53, Chris Wilson wrote:
Quoting Lionel Landwerlin (2017-11-16 16:00:03)
With the introduction of asymetric slices in CNL, we cannot rely on
the previous SUBSLICE_MASK getparam. Here we introduce a more detailed
way of querying the Gen's GPU topology that doesn't aggrega
On 17/11/17 11:17, Chris Wilson wrote:
Quoting Lionel Landwerlin (2017-11-17 11:08:07)
On 17/11/17 10:53, Chris Wilson wrote:
Is this subslicing only for the render unit; are all platforms going to
have the same fusing across all units? At the least, I thought we would
be able to configure the
Hi,
An update based on Chris & Tvrtko's feedback.
Cheers,
Lionel Landwerlin (4):
drm/i915: store all subslice masks
drm/i915/debugfs: reuse max slice/subslices already stored in sseu
drm/i915: expose engine availability through sysfs
drm/i915: expose EU topology through sysfs
slices.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_debugfs.c | 24 +++--
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 23 -
drivers/gpu/drm/i915/intel_device_info.c | 169 ++-
drivers/gpu/drm
attributes of each engine.
v2: Add capabilities sub directory (Tvrtko)
Move engines directory to drm/card/gt (Chris)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h | 5 +
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/i915_sysfs.c
Now that we have that information in topology fields, let's just reused it.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_debugfs.c | 26 ++
1 file changed, 10 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/dr
\:02.0/drm/card0/gt/rcs/0/slice0/subslice2/enabled_mask
0xff
v2: Move topology below rcs engine (Chris)
Add max_eus_per_subslice (Lionel)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h | 26 ++
drivers/gpu/drm/i915/i915_sysfs.c | 175 +++
On 17/11/17 10:53, Chris Wilson wrote:
Quoting Lionel Landwerlin (2017-11-16 16:00:03)
With the introduction of asymetric slices in CNL, we cannot rely on
the previous SUBSLICE_MASK getparam. Here we introduce a more detailed
way of querying the Gen's GPU topology that doesn't aggrega
slices.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_debugfs.c | 24 +++--
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 23 -
drivers/gpu/drm/i915/intel_device_info.c | 169 ++-
drivers/gpu/drm
attributes of each engine.
v2: Add capabilities sub directory (Tvrtko)
Move engines directory to drm/card/gt (Chris)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h | 5 +
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/i915_sysfs.c
Now that we have that information in topology fields, let's just reused it.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_debugfs.c | 26 ++
1 file changed, 10 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/dr
Hi all,
Last update on this with a couple of sysfs file renamed. I don't have
any other update or unaddressed comment.
Cheers,
Lionel Landwerlin (4):
drm/i915: store all subslice masks
drm/i915/debugfs: reuse max slice/subslices already stored in sseu
drm/i915: expose engine availab
sk (Lionel)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h | 26 ++
drivers/gpu/drm/i915/i915_sysfs.c | 188 ++
2 files changed, 214 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index db
On 20/11/17 16:03, Tvrtko Ursulin wrote:
- I would need engine->instance here as well.
Sure.
I thought that wasn't uabi though.
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On 20/11/17 16:13, Tvrtko Ursulin wrote:
On 20/11/2017 12:23, Lionel Landwerlin wrote:
With the introduction of asymetric slices in CNL, we cannot rely on
the previous SUBSLICE_MASK getparam. Here we introduce a more detailed
way of querying the Gen's GPU topology that doesn't
(Tvrtko)
Move engines directory to drm/card/gt (Chris)
v3: Move engines to drm/card/gt/engines/ (Tvrtko)
Add instance attribute to engines (Tvrtko)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h | 6 ++
drivers/gpu/drm/i915/i915_sysfs.c | 178
Hi,
Another updates with some layout changes in /sys.
Cheers,
Lionel Landwerlin (4):
drm/i915: store all subslice masks
drm/i915/debugfs: reuse max slice/subslices already stored in sseu
drm/i915: expose engine availability through sysfs
drm/i915: expose EU topology through sysfs
abled_mask (Lionel)
v4: Move slices to drm/card/gt/rcs/topology (Tvrtko)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h | 27 +
drivers/gpu/drm/i915/i915_sysfs.c | 208 ++
2 files changed, 235 insertions(+)
diff --git a/drivers/gp
slices.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_debugfs.c | 24 +++--
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 23 -
drivers/gpu/drm/i915/intel_device_info.c | 169 ++-
drivers/gpu/drm
Now that we have that information in topology fields, let's just reused it.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_debugfs.c | 26 ++
1 file changed, 10 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/dr
Hi,
A small fix on a wrongly size array (MAX_ENGINE_CLASS instead of
MAX_ENGINE_CLASS + 1).
Cheers,
Lionel Landwerlin (4):
drm/i915: store all subslice masks
drm/i915/debugfs: reuse max slice/subslices already stored in sseu
drm/i915: expose engine availability through sysfs
drm/i915
slices.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_debugfs.c | 24 +++--
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 23 -
drivers/gpu/drm/i915/intel_device_info.c | 169 ++-
drivers/gpu/drm
Now that we have that information in topology fields, let's just reused it.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_debugfs.c | 26 ++
1 file changed, 10 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/dr
(Tvrtko)
Move engines directory to drm/card/gt (Chris)
v3: Move engines to drm/card/gt/engines/ (Tvrtko)
Add instance attribute to engines (Tvrtko)
v4: Fix dev_priv->gt_topology.engines_classes_kobj size (Lionel)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_dr
abled_mask (Lionel)
v4: Move slices to drm/card/gt/rcs/topology (Tvrtko)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h | 27 +
drivers/gpu/drm/i915/i915_sysfs.c | 208 ++
2 files changed, 235 insertions(+)
diff --git a/drivers/gp
On 01/12/17 20:02, Paulo Zanoni wrote:
Em Sex, 2017-11-10 às 19:08 +, Lionel Landwerlin escreveu:
We use to have this fixed per generation, but starting with CNL
userspace
cannot tell just off the PCI ID. Let's make this information
available. This
is particularly useful for perfor
Hi,
After discussion with Chris, Joonas & Tvrtko, this series adds an
additional commit to link the render node back to the card through a
symlink. Making it obvious from an application using a render node to
know where to get the information it needs.
Cheers,
Lionel Landwerlin (5):
drm:
226\:128/card/
Signed-off-by: Lionel Landwerlin
Cc: dri-de...@lists.freedesktop.org
---
drivers/gpu/drm/drm_drv.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c
index 9acc1e157813..a26c0e86778e 100644
--- a/drivers/gpu/drm/dr
slices.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_debugfs.c | 24 +++--
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 23 -
drivers/gpu/drm/i915/intel_device_info.c | 169 ++-
drivers/gpu/drm
Now that we have that information in topology fields, let's just reused it.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_debugfs.c | 26 ++
1 file changed, 10 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/dr
engines (Tvrtko)
v4: Fix dev_priv->gt_topology.engines_classes_kobj size (Lionel)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h | 6 ++
drivers/gpu/drm/i915/i915_sysfs.c | 178
drivers/gpu/drm/i915/intel_engine_cs.c |
s/topology (Tvrtko)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h | 27 +
drivers/gpu/drm/i915/i915_sysfs.c | 208 ++
2 files changed, 235 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_d
On 15/11/17 12:25, Chris Wilson wrote:
Quoting Sagar Arun Kamble (2017-11-15 12:13:51)
#include
#include
@@ -2149,6 +2150,14 @@ struct i915_perf_stream {
* @oa_config: The OA configuration used by the stream.
*/
struct i915_oa_config *oa_config;
+
+ /**
+
Hey Sagar,
Sorry for the delay looking into this series.
I've done some userspace/UI work in GPUTop to try to correlate perf
samples/tracepoints with i915 perf reports.
I wanted to avoid having to add too much logic into the kernel and tried
to sample both cpu clocks & gpu timestamps from use
values.
v2: Added i915_driver_init_late() function to capture the new late init
phase for perf (Chris)
v3: Removed cross-timestamp changes.
Signed-off-by: Sourab Gupta
Signed-off-by: Sagar Arun Kamble
Cc: Lionel Landwerlin
Cc: Chris Wilson
Cc: Sourab Gupta
Cc: Matthew Auld
---
drivers/gpu/drm
On 05/12/17 14:28, Robert Bragg wrote:
On Tue, Dec 5, 2017 at 2:16 PM, Lionel Landwerlin
mailto:lionel.g.landwer...@intel.com>>
wrote:
Hey Sagar,
Sorry for the delay looking into this series.
I've done some userspace/UI work in GPUTop to try to correlate
p
On 15/11/17 12:13, Sagar Arun Kamble wrote:
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1447,6 +1447,12 @@ enum drm_i915_perf_property_id {
DRM_I915_PERF_PROP_SAMPLE_OA,
/**
+* The value of this property set to 1 requests inclusion of GPU
+
timecounter support.
Signed-off-by: Sourab Gupta
Signed-off-by: Sagar Arun Kamble
Cc: Lionel Landwerlin
Cc: Chris Wilson
Cc: Sourab Gupta
Cc: Matthew Auld
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_perf.c | 26 +-
2 files changed, 27
I've put together some trival IGT tests :
https://github.com/djdeath/intel-gpu-tools/commits/wip/djdeath/cpu-timestamps
With a few changes which I pointed in the review :
https://github.com/djdeath/linux/commit/d0e4cf4d3f464491b4ffe97d112284d1ce73656d
Put together it seems to work relatively we
Some platforms might not have degamma or ctm support.
We can only verify whether those properties behave properly
if they're available.
Fixes: aa55641d4 ("tests/kms_color: New test for pipe level color management")
Signed-off-by: Lionel Landwerlin
---
tests/kms_pi
t;)
Reported-by: Matthew Auld
Signed-off-by: Lionel Landwerlin
Reviewed-by: Matthew Auld
Cc: # v4.12+
---
drivers/gpu/drm/i915/i915_perf.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 96682fd86f8
Hi,
Here is a v8 with some more changes following Andrzej's comment on
whitelisted registers. I've also added some documentation.
Cheers,
Lionel Landwerlin (6):
drm/i915/perf: fix flex eu registers programming
drm/i915/perf: prune OA configs
drm/i915/perf: leave GDT_CH
There will be a need for userspaces configurations to set this
register. We can apply the same model inside the kernel for test
configs.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_oa_bdw.c| 2 ++
drivers/gpu/drm/i915/i915_oa_bxt.c| 1 +
drivers/gpu/drm/i915
We already do it on Haswell and the documentation says it saves power.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index ad84260de949
It makes things easier to read to implement whitelisting in the
following patches.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_reg.h | 212
1 file changed, 106 insertions(+), 106 deletions(-)
diff --git a/drivers/gpu/drm/i915
ate i915 uapi (Chris)
Use wrappers to make assertions more readable (Chris)
v6: Add whitelisting test (Lionel)
Signed-off-by: Lionel Landwerlin
---
tests/perf.c | 336 +++
1 file changed, 336 insertions(+)
diff --git a/tests/perf.c b/te
tthew Auld
Signed-off-by: Lionel Landwerlin
Signed-off-by: Andrzej Datczuk
---
Documentation/gpu/i915.rst | 4 +
drivers/gpu/drm/i915/i915_drv.c | 2 +
drivers/gpu/drm/i915/i915_drv.h | 47
drivers/gpu/drm/i915/i915_perf.c | 468 +--
drivers/gp
Hi Sagar,
I'm curious to what happens if 2 contexts submit requests which a time
period smaller than the sampling OA period on Gen7.5.
My understanding is that with this change you'll only retain the last
submission and then the ctx_id reported in the SAMPLE_CTX_ID field will
be incorrect for
On 31/07/17 08:59, Sagar Arun Kamble wrote:
From: Sourab Gupta
This patch introduces a framework to capture OA counter reports associated
with Render command stream. We can then associate the reports captured
through this mechanism with their corresponding context id's. This can be
further exte
Thanks for the details!
On 31/07/17 12:38, sourab gupta wrote:
On Mon, Jul 31, 2017 at 3:13 PM, Lionel Landwerlin
mailto:lionel.g.landwer...@intel.com>>
wrote:
On 31/07/17 08:59, Sagar Arun Kamble wrote:
From: Sourab Gupta mailto:sourab.gu...@int
On 31/07/17 08:59, Sagar Arun Kamble wrote:
From: Sourab Gupta
This patch introduces a framework to capture OA counter reports associated
with Render command stream. We can then associate the reports captured
through this mechanism with their corresponding context id's. This can be
further exte
On 31/07/17 17:39, Matthew Auld wrote:
On 28 July 2017 at 18:10, Lionel Landwerlin
wrote:
It makes things easier to read to implement whitelisting in the
"easier to read and to" ?
I guess :
"to read when implementing"
following patches.
Signed-off-by: Lionel Land
f-by: Matthew Auld
Signed-off-by: Lionel Landwerlin
Signed-off-by: Andrzej Datczuk
---
Documentation/gpu/i915.rst | 4 +
drivers/gpu/drm/i915/i915_drv.c | 2 +
drivers/gpu/drm/i915/i915_drv.h | 47 drivers/gpu/drm/i915/i915_perf.c
| 468 +--
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