On Mon, Aug 01, 2022 at 02:38:39PM -0700, Harish Chegondi wrote:
> Bspec: 46052
> Reviewed-by: Matt Roper
> Signed-off-by: Harish Chegondi
Applied to drm-intel-gt-next. Thanks for the patch.
Matt
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
> drive
MTP)
> + /*
> + * MTL always uses a 38.4 MHz rawclk. The bspec tells us
Indentation isn't quite right here.
Patch is also missing your s-o-b.
With those fixed,
Reviewed-by: Matt Roper
> + * "RAWCLK_FREQ defaults to the values for 38.4 and does
>
a Tolakanahalli Pradeep (2):
> drm/i915/dmc: Load DMC on MTL
> drm/i915/mtl: Update CHICKEN_TRANS* register addresses
>
> Matt Roper (4):
> drm/i915: Read graphics/media/display arch version from hw
> drm/i915/mtl: MMIO range is now 4MB
> drm/i915/mtl: Don't mask o
_DPA_AUX_CH_DATA1, \
> +_DPB_AUX_CH_DATA1, \
> +0, /* port/aux_ch C is
> non-existent */ \
> +
> _XELPDP_USBC1_AUX_CH_DATA1, \
> +
> _XELPDP_USBC2_AUX_CH_DATA1, \
> +
> _XELPDP_USBC3_AUX_CH_DATA1, \
> +
> _XELPDP_USBC4_AUX_CH_DATA1) + (i) * 4)
> +
> #define DP_AUX_CH_CTL_SEND_BUSY(1 << 31)
> #define DP_AUX_CH_CTL_DONE (1 << 30)
> #define DP_AUX_CH_CTL_INTERRUPT(1 << 29)
> @@ -3631,6 +3659,8 @@
> #define DP_AUX_CH_CTL_RECEIVE_ERROR(1 << 25)
> #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK(0x1f << 20)
> #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
> +#define XELPDP_DP_AUX_CH_CTL_POWER_REQUEST (1 << 19)
> +#define XELPDP_DP_AUX_CH_CTL_POWER_STATUS (1 << 18)
We should probably start using REG_BIT() for the new bits at least.
Matt
> #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
> #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
> #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
On Wed, Jul 27, 2022 at 06:34:06PM -0700, Radhakrishna Sripada wrote:
> The initialization sequence for Meteorlake reuses the sequence for
> icelake for most parts. Some changes viz. reset PICA handshake
> are added.
>
> Bspec: 49189
>
> Cc: Matt Roper
> Signed-off-
the usual places
(e.g., page 20124), but in general we should always assume the next
platform inherits the behavior of the previous platform unless there's
information to suggest different behavior, so
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_bios.c | 14 +++-
pu/drm/i915/display/intel_gmbus.h
> b/drivers/gpu/drm/i915/display/intel_gmbus.h
> index 8edc2e99cf53..20f704bd4e70 100644
> --- a/drivers/gpu/drm/i915/display/intel_gmbus.h
> +++ b/drivers/gpu/drm/i915/display/intel_gmbus.h
> @@ -24,6 +24,7 @@ struct i2c_adapter;
> #define GMBUS_PIN_2
On Thu, Jul 28, 2022 at 11:49:07AM -0700, Harish Chegondi wrote:
> Bspec: 46052
> Cc: Matt Roper
> Signed-off-by: Harish Chegondi
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 8
> 2 files changed, 9 in
On Tue, Jul 26, 2022 at 09:44:38AM -0700, Srivatsa, Anusha wrote:
> Thanks Tvrtko :)
> @Roper, Matthew D Did you have any other feedback on this patch?
Nope, looks fine to me. Thanks.
Reviewed-by: Matt Roper
>
> Anusha
>
> > -Original Message-
> > Fro
gine, struct i915_wa_li
> > > wa_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB);
> > > wa_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB);
> > > }
> > > +
> > > + if (IS_DG2(i915)) {
> > > + /* Performance tuning for Ray-tracing */
> > > + wa_write_clr_set(wal,
> > > + RT_CTRL,
> > > + RT_CTRL_NUMBER_OF_STACKIDS_MASK,
> > > + REG_FIELD_PREP(RT_CTRL_NUMBER_OF_STACKIDS_MASK,
> > > + NUMBER_OF_STACKIDS_512));
> > > + }
> > > }
> > > static void
> >
> >
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
commit message (and drop the "no
> > functional change" statement).
> >
> > The code change itself looks fine to me since it seems like the traditional
> > combo PHYs may be a thing of the past and we don't want to keep assuming
> > future platforms will have a
we don't want to
keep assuming future platforms will have any.
Matt
> to accommodate for cases where combo phy is not available.
>
> v2: retain comment that explains DG2 returning false from
> intel_phy_is_combo() (Arun)
>
> Cc: Arun R Murthy
> Cc: Matt Roper
> Signed-off-
op.org
> > Subject: Re: [Intel-gfx] [PATCH] drm/i915: Pass drm_i915_private struct
> > instead of gt for gen11_gu_misc_irq_handler()
> >
> >
> > On 18/07/2022 19:54, Matt Roper wrote:
> > > On Mon, Jul 18, 2022 at 11:34:24AM -0700, Anusha Srivatsa wrote:
> &
On Mon, Jul 18, 2022 at 11:34:24AM -0700, Anusha Srivatsa wrote:
> gen11_gu_misc_irq_handler() does not do anything tile specific.
>
> Cc: Matt Roper
> Signed-off-by: Anusha Srivatsa
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/i915_irq.c | 8
> 1 file
On Wed, Jul 13, 2022 at 03:50:35AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Correct ss -> steering calculation for pre-Xe_HP platforms
> URL : https://patchwork.freedesktop.org/series/106269/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from
Accidental use of a "SLICE" macro where a "SUBSLICE" macro was intended
causes the group ID for steering to be calculated incorrectly on
pre-Xe_HP platforms.
Fixes: 9a92732f040a ("drm/i915/gt: Add general DSS steering iterator to
intel_gt_mcr")
Signed-off-by: Ma
On Sat, Jul 09, 2022 at 07:41:45AM +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [1/2] drm/i915/dg2: Add Wa_15010599737
> URL : https://patchwork.freedesktop.org/series/106130/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from
We already disable FBC when PSR2 is enabled on display version 12 and
above; this new workaround now requires that we do the same with PSR1 on
display versions 12 and 13.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_fbc.c | 6 ++
1 file changed, 6 insertions(+)
diff
This workaround may need to be extended to other platforms soon, but for
now it's marked as DG2-specific.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++
drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++
2 files changed, 6 insertions(+)
diff --git
On Fri, Jul 08, 2022 at 04:38:48PM +, Patchwork wrote:
> == Series Details ==
>
> Series: i915: Introduce Meteorlake
> URL : https://patchwork.freedesktop.org/series/106075/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_11859_full -> Patchwork_106075v1_full
>
On Sat, Jul 02, 2022 at 06:25:09PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/gt: Add general DSS steering iterator to intel_gt_mcr (rev2)
> URL : https://patchwork.freedesktop.org/series/105883/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from
On Fri, Jul 08, 2022 at 01:44:00PM +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [1/2] i915/perf: Replace DRM_DEBUG with driver
> specific drm_dbg call
> URL : https://patchwork.freedesktop.org/series/106062/
> State : failure
>
> == Summary ==
>
> CI Bug
On Thu, Jul 07, 2022 at 05:03:35PM -0700, Radhakrishna Sripada wrote:
> Add Meteorlake PCI IDs. Split into M, and P subplatforms.
>
> v2: Update PCI id's
> v3: Move id 7d60 under MTL_M(MattR)
>
> Bspec: 55420
>
> Signed-off-by: Radhakrishna Sripada
> Signed-off
Bspec: 45544
> Bspec: 65380
>
> v2: rearrange the fields in pci_info(MattR)
>
> Cc: Matt Roper
> Signed-off-by: Radhakrishna Sripada
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_pci.c | 25
> d
Bspec: 45544
> Bspec: 65380
>
> Cc: Matt Roper
> Signed-off-by: Radhakrishna Sripada
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_pci.c | 25
> drivers/gpu/drm/i915/intel_device_info.c | 1 +
>
On Thu, Jul 07, 2022 at 01:26:10PM -0700, Radhakrishna Sripada wrote:
> Add Meteorlake PCI IDs. Split into M, and P subplatforms.
>
> v2: Update PCI id's
>
> Bspec: 55420
>
> Signed-off-by: Radhakrishna Sripada
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm
whereas DRM_DEBUG_DRIVER is the one that treats them as driver messages
with DRM_UT_DRIVER).
Matt
> + return -ENODEV;
> + }
> +
> if (copy_from_user(_sseu,
> u64_to_user_ptr(value),
> sizeof(user_sseu))) {
> --
> 2.35.3
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
On Fri, Jul 01, 2022 at 04:32:36PM -0400, Tom Rix wrote:
> spelling changes
> resoluition -> resolution
> dont-> don't
> commmit -> commit
> Invalidade -> Invalidate
>
> Signed-off-by: Tom Rix
Reviewed-by: Matt Roper
and applied to drm-intel-ne
++
> Documentation/gpu/rfc/index.rst| 4 +
> include/uapi/drm/i915_drm.h| 205 +
> 4 files changed, 700 insertions(+), 45 deletions(-)
> create mode 100644 Documentation/gpu/rfc/i915_vm_bind.h
> create mode 100644 Documentation/gp
On Fri, Jul 01, 2022 at 09:59:50AM -0700, Lucas De Marchi wrote:
> On Fri, Jul 01, 2022 at 08:22:31AM -0700, Matt Roper wrote:
> > Small BAR support has now landed, which allows us to add the PCI IDs
> > that correspond to add-in card designs of DG2 and ATS-M. There's also
> &
out how to obtain steering IDs for a specific
DSS.
Most of the places where we use this new loop are in the GPU errorstate
code at the moment, but we do have some additional features coming in
the future that will also need to loop over each DSS and steer some
register accesses accordingly.
Signed-off-by
On Fri, Jul 01, 2022 at 12:52:21PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/pvc: Implement w/a 16016694945
> URL : https://patchwork.freedesktop.org/series/105837/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_11835_full ->
list.
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_pci.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.c | 2 --
include/drm/i915_pciids.h| 25 +++-
3 files changed, 4 insertions(+), 25 deletions(-)
diff --git a/drive
Small BAR support has now landed, which allows us to add the PCI IDs
that correspond to add-in card designs of DG2 and ATS-M. There's also
one additional MB-down PCI ID that recently appeared (0x5698) so we add
it too.
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915
0, false);
> + wa_write_clr_set(wal,
> + RT_CTRL,
> + RT_CTRL_NUMBER_OF_STACKIDS_MASK,
> + REG_FIELD_PREP(RT_CTRL_NUMBER_OF_STACKIDS_MASK,
> + NUMBER_OF_STACKIDS_512));
> }
>
> /*
> --
> 2.34.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
fic register and not something that applies to the Xe_HP
architecture as a whole.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 8
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 4 ++--
drivers/gpu/drm/i
it.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 1 +
drivers/gpu/drm/i915/gt/intel_gt_regs.h| 3 +++
drivers/gpu/drm/i915/i915_reg.h| 17 -
3 files changed, 4 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem
On Thu, Jun 23, 2022 at 07:48:32AM -0700, Souza, Jose wrote:
> On Wed, 2022-06-22 at 15:19 -0700, Matt Roper wrote:
> > On Tue, Jun 21, 2022 at 10:03:04AM -0700, Souza, Jose wrote:
> > > On Fri, 2022-06-17 at 12:28 -0700, Matt Roper wrote:
> > > > On Fri, Jun 17,
On Tue, Jun 21, 2022 at 10:03:04AM -0700, Souza, Jose wrote:
> On Fri, 2022-06-17 at 12:28 -0700, Matt Roper wrote:
> > On Fri, Jun 17, 2022 at 12:06:29PM -0700, José Roberto de Souza wrote:
> > > Gem buffers could still be in use by display after i915_gem_suspend()
&g
he kernel coding style).
Matt
> }
>
> if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) {
> --
> 2.32.0
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
ni Nikula
> Signed-off-by: Daniele Ceraolo Spurio
Would the config table still get used somehow even though we return
false for ADL-N in has_table()?
Even if it couldn't be used, this change makes the behavior more clear
and explicit.
Reviewed-by: Matt Roper
> ---
> drivers/gpu/
t; + i915_gem_suspend(i915);
> +
> /*
>* The only requirement is to reboot with display DC states disabled,
>* for now leaving all display power wells in the INIT power domain
> --
> 2.36.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
bind_vma;
> + ggtt->vm.vma_ops.unbind_vma = intel_ggtt_unbind_vma;
> +
> + return ggtt_probe_common(ggtt, size);
> +}
> +
> static int ggtt_probe_hw(struct i915_ggtt *ggtt, struct intel_gt *gt)
> {
> struct drm_i915_private *i915 = gt->i915;
> @@ -576,1
On Fri, Jun 17, 2022 at 06:57:20AM -0700, Harish Chegondi wrote:
> On Tue, Jun 14, 2022 at 05:10:19PM -0700, Matt Roper wrote:
> > Let's replace the assortment of intel_gt_* and intel_uncore_* functions
> > that operate on MCR registers with a cleaner se
On Thu, Jun 16, 2022 at 05:31:00PM +0530, Anshuman Gupta wrote:
> DG2 NB SKU need to distinguish between MBD and AIC to probe
> the VRAM Self Refresh feature support. Adding those sub platform
> accordingly.
>
> Cc: Matt Roper
> Signed-off-by: Anshuman Gupta
> ---
&g
> [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
> [i915#4369]: https://gitlab.freedesktop.org/drm/intel/issues/4369
> [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
> [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
> [i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
> [i915#4893]: https://gitlab.freedesktop.org/drm/intel/issues/4893
> [i915#4939]: https://gitlab.freedesktop.org/drm/intel/issues/4939
> [i915#5099]: https://gitlab.freedesktop.org/drm/intel/issues/5099
> [i915#51]: https://gitlab.freedesktop.org/drm/intel/issues/51
> [i915#5161]: https://gitlab.freedesktop.org/drm/intel/issues/5161
> [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
> [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
> [i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
> [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
> [i915#5287]: https://gitlab.freedesktop.org/drm/intel/issues/5287
> [i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
> [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
> [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
> [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
> [i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
> [i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
> [i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
> [i915#5591]: https://gitlab.freedesktop.org/drm/intel/issues/5591
> [i915#5939]: https://gitlab.freedesktop.org/drm/intel/issues/5939
> [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
> [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
> [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
>
>
> Build changes
> -
>
> * Linux: CI_DRM_11758 -> Patchwork_105134v1
>
> CI-20190529: 20190529
> CI_DRM_11758: a2644b16f1f05a1a6eff99d7076bfa0e770bdeb6 @
> git://anongit.freedesktop.org/gfx-ci/linux
> IGT_6526: 02888400228efbb29437726aa04114575ea939c3 @
> https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
> Patchwork_105134v1: a2644b16f1f05a1a6eff99d7076bfa0e770bdeb6 @
> git://anongit.freedesktop.org/gfx-ci/linux
> piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
> git://anongit.freedesktop.org/piglit
>
> == Logs ==
>
> For more details see:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105134v1/index.html
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
ux: CI_DRM_11758 -> Patchwork_105134v1
>
> CI-20190529: 20190529
> CI_DRM_11758: a2644b16f1f05a1a6eff99d7076bfa0e770bdeb6 @
> git://anongit.freedesktop.org/gfx-ci/linux
> IGT_6526: 02888400228efbb29437726aa04114575ea939c3 @
> https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
> Patchwork_105134v1: a2644b16f1f05a1a6eff99d7076bfa0e770bdeb6 @
> git://anongit.freedesktop.org/gfx-ci/linux
>
>
> ### Linux commits
>
> aa8c692ba084 drm/i915/gt: Cleanup interface for MCR operations
> 6be8d7758465 drm/i915/gt: Move multicast register handling to a dedicated file
>
> == Logs ==
>
> For more details see:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105134v1/index.html
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
On Mon, Jun 13, 2022 at 11:14:39PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> adl-s needs the combo PLL DCO fraction w/a as well.
> Get us slightly more accurate clock out of the PLL.
>
> Cc: sta...@vger.kernel.org
> Signed-off-by: Ville Syrjälä
Re
ntel/issues/4525
> [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
> [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
> [i915#4613]: https://gitlab.freedesktop
to
clarify the difference between "_fw" and non-"_fw" forms.
Matt Roper (2):
drm/i915/gt: Move multicast register handling to a dedicated file
drm/i915/gt: Cleanup interface for MCR operations
Documentation/gpu/i915.rst | 12 +
drivers/gpu/drm/i915/Makefile
ecent
platforms; these days MCR steering applies to more types of replication
than just slice/subslice.
v2:
- Reference the new kerneldoc from i915.rst. (Jani)
- Tweak the wording of the documentation for a couple functions to
clarify the difference between "_fw" and non-"
functions have been moved to the new .c/.h as-is.
Function renames and updates to operate in a more consistent manner will
be done in subsequent patches.
Signed-off-by: Matt Roper
Acked-by: Jani Nikula
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gem
Looks like the logs links finally work (there was probably a big backlog
to upload them after the gitlab downtime). The module_reload log shows
and ext4 filesystem panic (not graphics-related). The syncobj_basic
failure is an unexpected incomplete; no graphics errors in the log that
I can see,
On Tue, Jun 14, 2022 at 07:20:48PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/pvc: Adjust EU per SS according to HAS_ONE_EU_PER_FUSE_BIT()
> URL : https://patchwork.freedesktop.org/series/105010/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from
with real workarounds are flagged.
Bspec: 72161
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 5 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 +
2 files changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/d
ecent
platforms; these days MCR steering applies to more types of replication
than just slice/subslice.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 2 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 33 ++-
drivers/gpu/drm/i915/gt/intel_gt_debugfs.c | 2 +-
-terminated
instance
* intel_gt_mcr_unicast_write -- unicast write to specific instance
* intel_gt_mcr_multicast_write[_fw] -- multicast write to all instances
Matt Roper (2):
drm/i915/gt: Move multicast register handling to a dedicated file
drm/i915/gt: Cleanup interface for MCR operations
functions have been moved to the new .c/.h as-is.
Function renames and updates to operate in a more consistent manner will
be done in subsequent patches.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 1 +
drivers/gpu
If we're treating each bit in the EU fuse register as a single EU
instead of a pair of EUs, then that also cuts the number of potential
EUs per subslice in half.
Fixes: 5ac342ef84d7 ("drm/i915/pvc: Add SSEU changes")
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_sseu.c
On Thu, Jun 09, 2022 at 02:17:54PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/pvc: Add register steering (rev2)
> URL : https://patchwork.freedesktop.org/series/104691/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_11740_full ->
ES() macro to HAS_MSLICE_STEERING().
PVC hardware still has units referred to as mslices, but there's no
register steering based on mslice for this platform.
v2:
- Rebase on other recent changes
- Swap two table rows to keep table sorted & easy to read. (Harish)
Bspec: 67609
Signed-off-by: Matt R
issues/4812
> [i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
> [i915#4842]: https://gitlab.freedesktop.org/drm/intel/issues/4842
> [i915#4852]:
On Wed, Jun 08, 2022 at 08:23:34AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/xehp: Correct steering initialization
> URL : https://patchwork.freedesktop.org/series/104842/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_11732_full ->
: 0.6.4
Commit: drm/i915: More PVC+DG2 workarounds
Okay!
and if I do it manually with "make C=1" I just see the handful of
pre-existing / expected warnings, nothing new from this patch. Any
ideas what could be going on here? Maybe some quirk of the older v0.6.2
version CI
esktop.org/drm/intel/issues/4538
> [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
> [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
> [i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
> [i915#4807]: https://gitlab.freedesktop.org/drm/intel/issues/4807
> [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
> [i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
> [i915#4842]: https://gitlab.freedesktop.org/drm/intel/issues/4842
> [i915#4853]: https://gitlab.freedesktop.org/drm/intel/issues/4853
> [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
> [i915#4893]: https://gitlab.freedesktop.org/drm/intel/issues/4893
> [i915#4911]: https://gitlab.freedesktop.org/drm/intel/issues/4911
> [i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
> [i915#5032]: https://gitlab.freedesktop.org/drm/intel/issues/5032
> [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
> [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
> [i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
> [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
> [i915#5287]: https://gitlab.freedesktop.org/drm/intel/issues/5287
> [i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
> [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
> [i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
> [i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
> [i915#5639]: https://gitlab.freedesktop.org/drm/intel/issues/5639
> [i915#5721]: https://gitlab.freedesktop.org/drm/intel/issues/5721
> [i915#5800]: https://gitlab.freedesktop.org/drm/intel/issues/5800
> [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
> [i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
> [i915#6129]: https://gitlab.freedesktop.org/drm/intel/issues/6129
> [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
> [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
>
>
> Build changes
> -
>
> * Linux: CI_DRM_11731 -> Patchwork_104825v1
>
> CI-20190529: 20190529
> CI_DRM_11731: 9c92db552b999f75af463bd7ccae9de7165cc0f8 @
> git://anongit.freedesktop.org/gfx-ci/linux
> IGT_6510: dacfa80158d586cd0fe322f25f5275f224a946dd @
> https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
> Patchwork_104825v1: 9c92db552b999f75af463bd7ccae9de7165cc0f8 @
> git://anongit.freedesktop.org/gfx-ci/linux
> piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
> git://anongit.freedesktop.org/piglit
>
> == Logs ==
>
> For more details see:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104825v1/index.html
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
Signed-off-by: Badal Nilawar
Signed-off-by: Prathap Kumar Valsan
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 +++--
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 4
drivers/gpu/drm/i915
rm/intel/issues/5176
> [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
> [i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
> [i915#5264]: https://gitlab.freedesktop.org/drm/intel/issues/5264
> [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
> [i915#5287]: https://gitlab.freedesktop.org/drm/intel/issues/5287
> [i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
> [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
> [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
> [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
> [i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
> [i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
> [i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519
> [i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
> [i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
> [i915#5591]: https://gitlab.freedesktop.org/drm/intel/issues/5591
> [i915#5713]: https://gitlab.freedesktop.org/drm/intel/issues/5713
> [i915#5721]: https://gitlab.freedesktop.org/drm/intel/issues/5721
> [i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
> [i915#5776]: https://gitlab.freedesktop.org/drm/intel/issues/5776
> [i915#5903]: https://gitlab.freedesktop.org/drm/intel/issues/5903
> [i915#6076]: https://gitlab.freedesktop.org/drm/intel/issues/6076
> [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
> [i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
> [i915#6140]: https://gitlab.freedesktop.org/drm/intel/issues/6140
> [i915#6141]: https://gitlab.freedesktop.org/drm/intel/issues/6141
> [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
> [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
> [i915#768]: https://gitlab.freedesktop.org/drm/intel/issues/768
> [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
>
>
> Build changes
> -
>
> * Linux: CI_DRM_11730 -> Patchwork_104760v2
>
> CI-20190529: 20190529
> CI_DRM_11730: 5e7f37992081d4600d6329a745ab7edb2ee42bcd @
> git://anongit.freedesktop.org/gfx-ci/linux
> IGT_6510: dacfa80158d586cd0fe322f25f5275f224a946dd @
> https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
> Patchwork_104760v2: 5e7f37992081d4600d6329a745ab7edb2ee42bcd @
> git://anongit.freedesktop.org/gfx-ci/linux
> piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
> git://anongit.freedesktop.org/piglit
>
> == Logs ==
>
> For more details see:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104760v2/index.html
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
uapi")
Cc: Balasubramani Vivekanandan
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index b7
te internal subslice mask
representation from uapi")
Reported-by: Balasubramani Vivekanandan
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers
On Tue, Jun 07, 2022 at 04:15:42PM +0530, Anshuman Gupta wrote:
> i915 must disable Render DOP clock gating globally.
>
> v2:
> - Addressed cosmetic review comments.
>
> Bspec: 52621
> Cc: Matt Roper
> Cc: Badal Nilawar
> Signed-off-by: Anshuman Gupt
On Mon, Jun 06, 2022 at 11:33:24AM +0530, Anshuman Gupta wrote:
> i915 must disable Render DOP clock gating globally.
>
> B.Spec: 52621
> Cc: Matt Roper
> Cc: Badal Nilawar
> Signed-off-by: Anshuman Gupta
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
&g
On Mon, Jun 06, 2022 at 12:55:20PM +0100, Tvrtko Ursulin wrote:
>
> On 27/05/2022 19:42, Matt Roper wrote:
> > On Thu, May 26, 2022 at 11:18:17AM +0100, Tvrtko Ursulin wrote:
> > > On 25/05/2022 19:05, Matt Roper wrote:
> > > > On Wed, May 25, 2022 at 05:03
g/drm/intel/issues/4785
> [i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
> [i915#5122]: https://gitlab.freedesktop.org/drm/intel/issues/5122
> [i915#6011]: https://gitlab.freedesktop.org/drm/intel/issues/6011
>
>
> Build changes
> -
>
> * Linux:
gt; [i915#4842]: https://gitlab.freedesktop.org/drm/intel/issues/4842
> [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
> [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
> [i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
> [i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885
> [i915#4893]: https://gitlab.freedesktop.org/drm/intel/issues/4893
> [i915#4939]: https://gitlab.freedesktop.org/drm/intel/issues/4939
> [i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
> [i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
> [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
> [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
> [i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
> [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
> [i915#5287]: https://gitlab.freedesktop.org/drm/intel/issues/5287
> [i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
> [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
> [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
> [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
> [i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
> [i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
> [i915#5591]: https://gitlab.freedesktop.org/drm/intel/issues/5591
> [i915#5639]: https://gitlab.freedesktop.org/drm/intel/issues/5639
> [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
> [i915#5843]: https://gitlab.freedesktop.org/drm/intel/issues/5843
> [i915#6076]: https://gitlab.freedesktop.org/drm/intel/issues/6076
> [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
> [i915#6139]: https://gitlab.freedesktop.org/drm/intel/issues/6139
> [i915#6140]: https://gitlab.freedesktop.org/drm/intel/issues/6140
> [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
> [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
> [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
>
>
> Build changes
> -
>
> * Linux: CI_DRM_11723 -> Patchwork_104688v1
>
> CI-20190529: 20190529
> CI_DRM_11723: c7b64508e5166dd035e39ea0640f9e1ad840ca0f @
> git://anongit.freedesktop.org/gfx-ci/linux
> IGT_6505: edb1a467fb622b23b927e28ff603fa43851fea97 @
> https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
> Patchwork_104688v1: c7b64508e5166dd035e39ea0640f9e1ad840ca0f @
> git://anongit.freedesktop.org/gfx-ci/linux
> piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
> git://anongit.freedesktop.org/piglit
>
> == Logs ==
>
> For more details see:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104688v1/index.html
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
On Fri, Jun 03, 2022 at 12:53:08AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/display/adlp: More updates to voltage swing table
> URL : https://patchwork.freedesktop.org/series/104661/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_11719_full
ES() macro to HAS_MSLICE_STEERING().
PVC hardware still has units referred to as mslices, but there's no
register steering based on mslice for this platform.
Bspec: 67609
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c | 50 ++---
drivers/gpu/drm/i915/gt/intel_gt_types
On Thu, Jun 02, 2022 at 04:36:02PM -0700, Dixit, Ashutosh wrote:
> On Fri, 27 May 2022 16:41:28 -0700, Matt Roper wrote:
> >
> > On Thu, May 26, 2022 at 12:00:42PM -0700, Ashutosh Dixit wrote:
> > > Create a gt/gtN/.defaults directory (similar to
> > > eng
ected.
Cc: Stuart Summers
Cc: Lucas De Marchi
Signed-off-by: Badal Nilawar
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 4
drivers/gpu/drm/i915/gt/uc/intel_
We missed this setting in the initial device info patch's definition of
XE_HPC_FEATURES.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 047a6e326031
he audio enable
> bit being in the DP or HDMI registers on older platforms.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_audio.c| 1 +
> .../gpu/drm/i915/display/intel_audio_regs.h | 160 ++
> driv
On Thu, Jun 02, 2022 at 01:17:30PM -0700, José Roberto de Souza wrote:
> This workaround brings some regressions to DG2 and if really necessary
> for DG2 an alternative workaround will be implemented.
>
> BSpec: 54077
> Signed-off-by: José Roberto de Souza
Reviewed
g/drm/intel/issues/6135
> [i915#6136]: https://gitlab.freedesktop.org/drm/intel/issues/6136
> [i915#6137]: https://gitlab.freedesktop.org/drm/intel/issues/6137
> [i915#6138]: https://gitlab.freedesktop.org/drm/intel/issues/6138
> [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
>
&g
1
> [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
> [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
> [i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
> [i915#5264]: https://gitlab.freedesktop.org/drm/intel/issues/52
176
> [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
> [i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
> [i915#5264]: https://gitlab.freedesktop.org/drm/intel/issues/5264
> [i915#5266]: https://gitlab.freedesktop.org/drm/intel/issues/5266
> [i915#5286]: h
Most of these registers have existed since earlier platforms (e.g., gen6
or gen7) but were initially introduced only for a subset of the
platforms' engines; gen11 seems to be where they became available on all
engines.
Signed-off-by: Stuart Summers
Signed-off-by: Matt Roper
---
drivers/gpu/drm/
the multi-slice logic from gen11+ platforms.
v2:
- Promote drm_dbg to drm_WARN_ON if the slice fuse register reports
unexpected fusing. (Tvrtko)
Cc: Tvrtko Ursulin
Signed-off-by: Matt Roper
Acked-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 76 +---
1
used on
multi-tile platforms where each tile will have its own masks.
Signed-off-by: Matt Roper
Acked-by: Tvrtko Ursulin
Acked-by: Lionel Landwerlin # mesa
---
drivers/gpu/drm/i915/i915_getparam.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_getparam.c
the local variable in intel_slicemask_from_xehp_dssmask() from
u16 to 'unsigned long' to make it a bit more future-proof.
Cc: Tvrtko Ursulin
Cc: Balasubramani Vivekanandan
Signed-off-by: Matt Roper
Acked-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 5 +-
drivers/gpu/drm/i915/gt/intel_e
has_xehp_dss flag
Signed-off-by: Matt Roper
Acked-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 86
drivers/gpu/drm/i915/gt/intel_sseu.h | 5 ++
2 files changed, 54 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c
b
, but the code is simpler without it.
(Tvrtko)
v3:
- Mask down EUs passed to sseu_set_eus at the callsite rather than
inside the function. (Tvrtko)
- Eliminate sseu->eu_stride and calculate it when needed. (Tvrtko)
Cc: Tvrtko Ursulin
Signed-off-by: Matt Roper
Acked-by: Tvrtko Ursu
cal variable in intel_slicemask_from_xehp_dssmask() from u16 to
'unsigned long' to make it a bit more future-proof.
- Incorporate ack's received from Tvrtko and Lionel.
Cc: Tvrtko Ursulin
Cc: Balasubramani Vivekanandan
Matt Roper (6):
drm/i915/xehp: Use separate sseu init function
drm/i915/x
PVC splits the mask of enabled DSS over two registers. It also changes
the meaning of the EU fuse register such that each bit represents a
single EU rather than a pair of EUs.
Signed-off-by: Matt Roper
Acked-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
drivers/gpu
On Wed, Jun 01, 2022 at 01:48:56PM +0530, Balasubramani Vivekanandan wrote:
> On 23.05.2022 13:45, Matt Roper wrote:
> > As with EU masks, it's easier to store subslice/DSS masks internally in
> > a format that's more natural for the driver to work with, and then only
> > cove
On Sat, May 28, 2022 at 01:36:06PM +, Patchwork wrote:
> == Series Details ==
>
> Series: i915: PVC steppings and initial workarounds
> URL : https://patchwork.freedesktop.org/series/104461/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_11705_full ->
other.
I'm not too familiar with the feature you're working on here. Is there
a way we can detect whether it's supported by querying the pcode? Or
what happens if you send your pcode request on a platform that doesn't
support it? Do you just get a regular error back so that the driver
would know to give up and move on, or would it actually cause some kind
of behavioral problem?
Matt
> Thanks,
> Anshuman Gupta.
> >
> > BR,
> > Jani.
> >
> > > #define IS_ADLS_RPLS(dev_priv) \
> > > IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S,
> > INTEL_SUBPLATFORM_RPL)
> > > #define IS_ADLP_N(dev_priv) \
> >
> > --
> > Jani Nikula, Intel Open Source Graphics Center
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
/i915/gt/uc/intel_guc_slpc.c | 19 --
> 6 files changed, 103 insertions(+), 10 deletions(-)
>
> --
> 2.34.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
On Thu, May 26, 2022 at 11:18:17AM +0100, Tvrtko Ursulin wrote:
>
> On 25/05/2022 19:05, Matt Roper wrote:
> > On Wed, May 25, 2022 at 05:03:13PM +0100, Tvrtko Ursulin wrote:
> > >
> > > On 24/05/2022 18:51, Matt Roper wrote:
> > > > On Tue, May 24, 2022
CI.
>
> Signed-off-by: Lucas De Marchi
Acked-by: Matt Roper
> ---
> .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 21 +--
> 1 file changed, 5 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> b/drivers
On Thu, May 26, 2022 at 03:22:13PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/display/adl_p: Updates to HDMI combo PHY voltage swing table
> URL : https://patchwork.freedesktop.org/series/104393/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from
From: Stuart Summers
Bspec: 64027
Signed-off-by: Stuart Summers
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_engine_regs.h | 5 +-
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 61 ++---
drivers/gpu/drm/i915
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