a Srivatsa
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 19 +++
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++
drivers/gpu/drm/i915/gt/intel_sa_media.c | 7 +++
drivers/gpu/drm/i915/i915_drv.h | 3 +++
4 files changed, 31 insertions(+)
Xe_LPM+ platforms have "standalone media." I.e., the media unit is
designed as an additional GT with its own engine list, GuC, forcewake,
etc. Let's allow platforms to include media GTs in their device info.
Cc: Aravind Iddamsetty
Signed-off-by: Matt Roper
---
drivers/gpu/dr
Moving the locking for MMIO debug (and the final check for unclaimed
accesses when resuming debug after a userspace-initiated forcewake) will
make it simpler to completely skip MMIO debug handling on uncores that
don't support it in future patches.
Signed-off-by: Matt Roper
---
drivers/gp
The common early GT init is needed for initialization of all GT types
(root/primary, remote tile, standalone media). Since standalone media
(coming in the next patch) will be implemented in a separate file,
rename and expose the function for use.
Signed-off-by: Matt Roper
---
drivers/gpu/drm
e simplest solution is to simply leave uncore->debug NULL on all
intel_uncore instances except for the primary one. This will allow us
to avoid the pointless debug spinlock acquisition we've been doing on
MMIO accesses coming in through these intel_uncores.
Signed-off-by: Matt Roper
---
d
e
immediate MTL media enabling, this same framework will also be used
farther down the road when we enable remote tiles on xehpsdv and pvc.
Cc: Aravind Iddamsetty
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt.c
We're slowly transitioning the init-time kzalloc's of the driver over to
DRM-managed allocations; let's make sure the uncore objects allocated
for non-root GTs are thus allocated.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c | 6 ++
1 file changed, 2 i
es, all interrupt handling for
standalone media still happens via the primary GT.
Matt Roper (8):
drm/i915: Move locking and unclaimed check into
mmio_debug_{suspend,resume}
drm/i915: Only hook up uncore->debug for primary uncore
drm/i915: Use managed allocations for extra uncore
:
> - Simplify MTL_MEM_SS_INFO_QGV_POINT macro(MattR)
> - Nit: Rearrange the bit def's from higher to lower(MattR)
> - Restore platform definition for ADL-P(MattR)
> - Move back intel_qgv_point def to intel_bw.c(Jani)
> Bspec: 64636, 64608
>
> Cc: Matt Roper
> Cc:
flag to the ATS-M
device info to enable/disable this setting.
Bspec: 68331
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++
drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 +
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers
in certain circumstances. To ensure userspace's
updates to this chicken bit are handled properly by the hardware, we
need to make sure that FF_SLICE_CS_CHICKEN1[14] is once again set by the
kernel.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
drivers/gpu/drm/
i915#4941]: https://gitlab.freedesktop.org/drm/intel/issues/4941
> [i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
> [i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
> [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
> [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
> [i915#6598]: https://gitlab.freedesktop.org/drm/intel/issues/6598
> [i915#6637]: https://gitlab.freedesktop.org/drm/intel/issues/6637
> [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
>
>
> Build changes
> -
>
> * Linux: CI_DRM_12017 -> Patchwork_107638v1
>
> CI-20190529: 20190529
> CI_DRM_12017: d09b6a64bd55b1c8c7baada7537621015f0cfd71 @
> git://anongit.freedesktop.org/gfx-ci/linux
> IGT_6634: e01fe99f00692864b709253638c809231d1fb333 @
> https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
> Patchwork_107638v1: d09b6a64bd55b1c8c7baada7537621015f0cfd71 @
> git://anongit.freedesktop.org/gfx-ci/linux
> piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
> git://anongit.freedesktop.org/piglit
>
> == Logs ==
>
> For more details see:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107638v1/index.html
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
On Wed, Aug 24, 2022 at 02:26:38PM +0300, Joonas Lahtinen wrote:
> Quoting Matt Roper (2022-08-02 18:09:16)
> > On Mon, Aug 01, 2022 at 02:38:39PM -0700, Harish Chegondi wrote:
> > > Bspec: 46052
> > > Reviewed-by: Matt Roper
> > > Signed-off-by: Harish Chegon
ff-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 8 ++
drivers/gpu/drm/i915/gt/intel_workarounds.c | 27 ++---
2 files changed, 26 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
context ran.
Fixes: 6dc85721df74 ("drm/i915/dg2: Add additional tuning settings")
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/6642
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 21 +
drivers/gpu/drm/i915/gt/intel_workarou
uot;
> + * for DISPLAY_VER() >= 14.
> + *
> + * GV bandwidth will be set by intel_pmdemand_post_plane_update()
> + */
> + if (DISPLAY_VER(i915) >= 14)
> + return;
> +
> /*
>* Just return if we can't control SAGV or don't have it.
>* This is different from situation when we have SAGV but just can't
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
On Thu, Aug 18, 2022 at 04:41:55PM -0700, Radhakrishna Sripada wrote:
> Since Xe LPD+, Memory latency data are in LATENCY_LPX_LPY registers
> instead of GT driver mailbox.
>
> v2: Use the extracted wm latency adjustment function(Matt)
>
> Bspec: 64608
>
> Cc: Matt Roper
On Thu, Aug 18, 2022 at 04:41:54PM -0700, Radhakrishna Sripada wrote:
> Watermark latency is adjusted in cases when latency is 0us for level
> greater than 1, the subsequent levels are disabled. Extract this logic
> into its own function.
>
> Suggested-by: Matt Roper
gmbus.h
> b/drivers/gpu/drm/i915/display/intel_gmbus.h
> index 8edc2e99cf53..20f704bd4e70 100644
> --- a/drivers/gpu/drm/i915/display/intel_gmbus.h
> +++ b/drivers/gpu/drm/i915/display/intel_gmbus.h
> @@ -24,6 +24,7 @@ struct i2c_adapter;
> #define GMBUS_PIN_2_BXT
On Thu, Aug 18, 2022 at 04:41:42PM -0700, Radhakrishna Sripada wrote:
> From: Matt Roper
>
> Going forward, the hardware teams no longer consider new platforms to
> have a "generation" in the way we've defined it for past platforms.
> Instead, each IP block (graph
While we're at it, let's remove the "bdw,skl" from this comment since
it's misleading and doesn't match the code. We do still apply this
workaround on other pre-gen12 platforms than just those two.
Aside from the comment tweak,
Reviewed-by: Matt Roper
> -
ntel/issues/6433
> [i915#6458]: https://gitlab.freedesktop.org/drm/intel/issues/6458
> [i915#6463]: https://gitlab.freedesktop.org/drm/intel/issues/6463
> [i915#6493]: https://gitlab.freedesktop.org/drm/intel/issues/6493
> [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
> [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
>
>
> Build changes
> -
>
> * Linux: CI_DRM_11990 -> Patchwork_107342v1
>
> CI-20190529: 20190529
> CI_DRM_11990: 6590d43d39b99e1cd8693801b2ea8adeb97d9a04 @
> git://anongit.freedesktop.org/gfx-ci/linux
> IGT_6629: d24e986fb3b2ab6d755498d27828bc85931d12ff @
> https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
> Patchwork_107342v1: 6590d43d39b99e1cd8693801b2ea8adeb97d9a04 @
> git://anongit.freedesktop.org/gfx-ci/linux
> piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
> git://anongit.freedesktop.org/piglit
>
> == Logs ==
>
> For more details see:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107342v1/index.html
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
ces
and doesn't conflict with any real workarounds.
Since more of these are starting to show up on recent platforms, it's a
good time to create a dedicated function to hold them so that there's
less ambiguity about how/where to implement new ones.
Cc: Lucas De Marchi
Signed-off-by: Mat
ff-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 8 ++
drivers/gpu/drm/i915/gt/intel_workarounds.c | 27 ++---
2 files changed, 26 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
it a superset of the
workaround.
Bspec: 68331
Cc: Lucas De Marchi
Cc: Lionel Landwerlin
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 8 ++
drivers/gpu/drm/i915/gt/intel_workarounds.c | 27 ++---
2 files changed, 26 insertions(+), 9 dele
ces
and doesn't conflict with any real workarounds.
Since more of these are starting to show up on recent platforms, it's a
good time to create a dedicated function to hold them so that there's
less ambiguity about how/where to implement new ones.
Cc: Lucas De Marchi
Signed-off-by: Ma
>
> * Linux: CI_DRM_11971 -> Patchwork_106927v2
>
> CI-20190529: 20190529
> CI_DRM_11971: 2bdae66c9988dd0f07633629c0a85383cfc05940 @
> git://anongit.freedesktop.org/gfx-ci/linux
> IGT_6614: fbb4a4058b8f4119a079b2fda5c94aaacd850a78 @
> https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
> Patchwork_106927v2: 2bdae66c9988dd0f07633629c0a85383cfc05940 @
> git://anongit.freedesktop.org/gfx-ci/linux
>
>
> ### Linux commits
>
> 4e46a15b7ddf drm/i915: Sanitycheck PCI BARs
> 79faae70c394 drm/i915: Use of BARs names instead of numbers
>
> == Logs ==
>
> For more details see:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106927v2/index.html
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
loads all of the pipe firmwares (including pipe C and pipe D)
assuming it found them in the firmware file.
> DMC debug register for MTL.
>
> BSpec: 49788
> Cc: Matt Roper
> Signed-off-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/display/intel_dmc.c | 8
>
dmc->fw_path = DG2_DMC_PATH;
> dmc->required_version = DG2_DMC_VERSION_REQUIRED;
> dmc->max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE;
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
On Wed, Jul 27, 2022 at 06:34:16PM -0700, Radhakrishna Sripada wrote:
> From: José Roberto de Souza
>
> Display version 14 also supports MBUS joining just like ADL-P
> and also it don't need MBUS initialization, so extending ADL-P
s/don't/doesn't/
Otherwise,
Revie
ferent
handling/programming of DBUF (via the new PM demand mechanism). The
only thing that's actually the same is the computation of which dbufs
will be enabled (which is all this patch deals with).
>
> Bspec: 49255
>
> Cc: Matt Roper
> Original Author: Caz Yokoyama
> Signed
On Wed, Jul 27, 2022 at 06:34:14PM -0700, Radhakrishna Sripada wrote:
> Display version 14 platforms has different credits values compared to ADL-P.
s/has/have/
> Update the credits based on pipe usage.
>
> Bspec: 49213
>
> Cc: Jose Roberto de Souza
> Cc: Matt Roper
&
On Wed, Jul 27, 2022 at 06:34:13PM -0700, Radhakrishna Sripada wrote:
> Like ADL_P, Meteorlake has different memory characteristics from
> past platforms. Update the values used by our memory bandwidth
> calculations accordingly.
>
> Bspec: 64631
>
> Cc: Matt Roper
> Cc
be a typo here. I'm not sure what it's trying to say.
>
> Bspec: 49324, 64636
49324 doesn't look correct. Did you mean 64608?
>
> Cc: Matt Roper
> Original Author: Caz Yokoyama
> Signed-off-by: José Roberto de Souza
> Signed-off-by: Radhakrishna S
On Wed, Jul 27, 2022 at 06:34:10PM -0700, Radhakrishna Sripada wrote:
> Since Xe LPD+, Memory latency data are in LATENCY_LPX_LPY registers
> instead of GT driver mailbox.
>
> Bspec: 64608
>
> Cc: Matt Roper
> Original Author: Caz Yokoyama
> Signed-off-by: Radhakrishna S
t;aux_ch;
>
> - if (DISPLAY_VER(dev_priv) >= 12) {
> + if (DISPLAY_VER(dev_priv) >= 14) {
> + intel_dp->aux_ch_ctl_reg = xelpdp_aux_ctl_reg;
> + intel_dp->aux_ch_data_reg = xelpdp_aux_data_reg;
> + } else if (DISPLAY_VER(dev_priv) &g
On Mon, Aug 01, 2022 at 06:23:39PM -0700, Matt Roper wrote:
> On Wed, Jul 27, 2022 at 06:34:07PM -0700, Radhakrishna Sripada wrote:
> > From: Imre Deak
> >
> > Add support for display power wells on MTL. The differences from D13:
Also, this should be "...from Xe_LPD
On Mon, Aug 01, 2022 at 02:38:39PM -0700, Harish Chegondi wrote:
> Bspec: 46052
> Reviewed-by: Matt Roper
> Signed-off-by: Harish Chegondi
Applied to drm-intel-gt-next. Thanks for the patch.
Matt
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
> drive
gt; + /*
> + * MTL always uses a 38.4 MHz rawclk. The bspec tells us
Indentation isn't quite right here.
Patch is also missing your s-o-b.
With those fixed,
Reviewed-by: Matt Roper
> + * "RAWCLK_FREQ defaults to the values for 38.4 and does
Madhumitha Tolakanahalli Pradeep (2):
> drm/i915/dmc: Load DMC on MTL
> drm/i915/mtl: Update CHICKEN_TRANS* register addresses
>
> Matt Roper (4):
> drm/i915: Read graphics/media/display arch version from hw
> drm/i915/mtl: MMIO range is now 4MB
> drm/i915/mtl: Do
, \
> +_DPB_AUX_CH_DATA1, \
> +0, /* port/aux_ch C is
> non-existent */ \
> +
> _XELPDP_USBC1_AUX_CH_DATA1, \
> +
> _XELPDP_USBC2_AUX_CH_DATA1, \
> +
> _XELPDP_USBC3_AUX_CH_DATA1, \
> +
> _XELPDP_USBC4_AUX_CH_DATA1) + (i) * 4)
> +
> #define DP_AUX_CH_CTL_SEND_BUSY(1 << 31)
> #define DP_AUX_CH_CTL_DONE (1 << 30)
> #define DP_AUX_CH_CTL_INTERRUPT(1 << 29)
> @@ -3631,6 +3659,8 @@
> #define DP_AUX_CH_CTL_RECEIVE_ERROR(1 << 25)
> #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK(0x1f << 20)
> #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
> +#define XELPDP_DP_AUX_CH_CTL_POWER_REQUEST (1 << 19)
> +#define XELPDP_DP_AUX_CH_CTL_POWER_STATUS (1 << 18)
We should probably start using REG_BIT() for the new bits at least.
Matt
> #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
> #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
> #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
On Wed, Jul 27, 2022 at 06:34:06PM -0700, Radhakrishna Sripada wrote:
> The initialization sequence for Meteorlake reuses the sequence for
> icelake for most parts. Some changes viz. reset PICA handshake
> are added.
>
> Bspec: 49189
>
> Cc: Matt Roper
> Signed-off-
c in the usual places
(e.g., page 20124), but in general we should always assume the next
platform inherits the behavior of the previous platform unless there's
information to suggest different behavior, so
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_bios.c | 1
ers/gpu/drm/i915/display/intel_gmbus.h
> b/drivers/gpu/drm/i915/display/intel_gmbus.h
> index 8edc2e99cf53..20f704bd4e70 100644
> --- a/drivers/gpu/drm/i915/display/intel_gmbus.h
> +++ b/drivers/gpu/drm/i915/display/intel_gmbus.h
> @@ -24,6 +24,7 @@ struct i2c_adapter;
> #define GMBUS_
On Thu, Jul 28, 2022 at 11:49:07AM -0700, Harish Chegondi wrote:
> Bspec: 46052
> Cc: Matt Roper
> Signed-off-by: Harish Chegondi
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 8
> 2 files changed, 9 in
On Tue, Jul 26, 2022 at 09:44:38AM -0700, Srivatsa, Anusha wrote:
> Thanks Tvrtko :)
> @Roper, Matthew D Did you have any other feedback on this patch?
Nope, looks fine to me. Thanks.
Reviewed-by: Matt Roper
>
> Anusha
>
> > -Original Message-
> > Fro
> intel_engine_cs *engine, struct i915_wa_li
> > > wa_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB);
> > > wa_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB);
> > > }
> > > +
> > > + if (IS_DG2(i915)) {
> > > + /* Performance tuning for Ray-tracing */
> > > + wa_write_clr_set(wal,
> > > + RT_CTRL,
> > > + RT_CTRL_NUMBER_OF_STACKIDS_MASK,
> > > + REG_FIELD_PREP(RT_CTRL_NUMBER_OF_STACKIDS_MASK,
> > > + NUMBER_OF_STACKIDS_512));
> > > + }
> > > }
> > > static void
> >
> >
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
hat in the commit message (and drop the "no
> > functional change" statement).
> >
> > The code change itself looks fine to me since it seems like the traditional
> > combo PHYs may be a thing of the past and we don't want to keep assuming
> > future platfo
st and we don't want to
keep assuming future platforms will have any.
Matt
> to accommodate for cases where combo phy is not available.
>
> v2: retain comment that explains DG2 returning false from
> intel_phy_is_combo() (Arun)
>
> Cc: Arun R Murthy
> Cc: Matt Roper
&
op.org
> > Subject: Re: [Intel-gfx] [PATCH] drm/i915: Pass drm_i915_private struct
> > instead of gt for gen11_gu_misc_irq_handler()
> >
> >
> > On 18/07/2022 19:54, Matt Roper wrote:
> > > On Mon, Jul 18, 2022 at 11:34:24AM -0700, Anusha Srivatsa wrote:
> &
On Mon, Jul 18, 2022 at 11:34:24AM -0700, Anusha Srivatsa wrote:
> gen11_gu_misc_irq_handler() does not do anything tile specific.
>
> Cc: Matt Roper
> Signed-off-by: Anusha Srivatsa
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/i915_irq.c | 8
> 1 file
On Wed, Jul 13, 2022 at 03:50:35AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Correct ss -> steering calculation for pre-Xe_HP platforms
> URL : https://patchwork.freedesktop.org/series/106269/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_1
Accidental use of a "SLICE" macro where a "SUBSLICE" macro was intended
causes the group ID for steering to be calculated incorrectly on
pre-Xe_HP platforms.
Fixes: 9a92732f040a ("drm/i915/gt: Add general DSS steering iterator to
intel_gt_mcr")
Signed-off-by: Ma
On Sat, Jul 09, 2022 at 07:41:45AM +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [1/2] drm/i915/dg2: Add Wa_15010599737
> URL : https://patchwork.freedesktop.org/series/106130/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_11862_full
We already disable FBC when PSR2 is enabled on display version 12 and
above; this new workaround now requires that we do the same with PSR1 on
display versions 12 and 13.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_fbc.c | 6 ++
1 file changed, 6 insertions(+)
diff
This workaround may need to be extended to other platforms soon, but for
now it's marked as DG2-specific.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++
drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++
2 files changed, 6 insertions(+)
diff --
On Fri, Jul 08, 2022 at 04:38:48PM +, Patchwork wrote:
> == Series Details ==
>
> Series: i915: Introduce Meteorlake
> URL : https://patchwork.freedesktop.org/series/106075/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_11859_full -> Patchwork_106075v1_full
> ===
On Sat, Jul 02, 2022 at 06:25:09PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/gt: Add general DSS steering iterator to intel_gt_mcr (rev2)
> URL : https://patchwork.freedesktop.org/series/105883/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_
On Fri, Jul 08, 2022 at 01:44:00PM +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [1/2] i915/perf: Replace DRM_DEBUG with driver
> specific drm_dbg call
> URL : https://patchwork.freedesktop.org/series/106062/
> State : failure
>
> == Summary ==
>
> CI Bug Log
On Thu, Jul 07, 2022 at 05:03:35PM -0700, Radhakrishna Sripada wrote:
> Add Meteorlake PCI IDs. Split into M, and P subplatforms.
>
> v2: Update PCI id's
> v3: Move id 7d60 under MTL_M(MattR)
>
> Bspec: 55420
>
> Signed-off-by: Radhakrishna Sripada
> Signe
Bspec: 45544
> Bspec: 65380
>
> v2: rearrange the fields in pci_info(MattR)
>
> Cc: Matt Roper
> Signed-off-by: Radhakrishna Sripada
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_pci.c | 25
> d
Bspec: 45544
> Bspec: 65380
>
> Cc: Matt Roper
> Signed-off-by: Radhakrishna Sripada
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_pci.c | 25
> drivers/gpu/drm/i915/intel_device_info.c | 1 +
>
On Thu, Jul 07, 2022 at 01:26:10PM -0700, Radhakrishna Sripada wrote:
> Add Meteorlake PCI IDs. Split into M, and P subplatforms.
>
> v2: Update PCI id's
>
> Bspec: 55420
>
> Signed-off-by: Radhakrishna Sripada
> Signed-off-by: Matt Roper
> ---
> drivers/gp
s DRM_UT_CORE,
whereas DRM_DEBUG_DRIVER is the one that treats them as driver messages
with DRM_UT_DRIVER).
Matt
> + return -ENODEV;
> + }
> +
> if (copy_from_user(&user_sseu,
> u64_to_user_ptr(value),
> sizeof(user_sseu))) {
> --
> 2.35.3
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
On Fri, Jul 01, 2022 at 04:32:36PM -0400, Tom Rix wrote:
> spelling changes
> resoluition -> resolution
> dont-> don't
> commmit -> commit
> Invalidade -> Invalidate
>
> Signed-off-by: Tom Rix
Reviewed-by: Matt Roper
and applied to drm-int
++
> Documentation/gpu/rfc/index.rst| 4 +
> include/uapi/drm/i915_drm.h| 205 +
> 4 files changed, 700 insertions(+), 45 deletions(-)
> create mode 100644 Documentation/gpu/rfc/i915_vm_bind.h
> create mode 100644 Documentation/gp
On Fri, Jul 01, 2022 at 09:59:50AM -0700, Lucas De Marchi wrote:
> On Fri, Jul 01, 2022 at 08:22:31AM -0700, Matt Roper wrote:
> > Small BAR support has now landed, which allows us to add the PCI IDs
> > that correspond to add-in card designs of DG2 and ATS-M. There's also
&
igure out the details about how to obtain steering IDs for a specific
DSS.
Most of the places where we use this new loop are in the GPU errorstate
code at the moment, but we do have some additional features coming in
the future that will also need to loop over each DSS and steer some
register access
On Fri, Jul 01, 2022 at 12:52:21PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/pvc: Implement w/a 16016694945
> URL : https://patchwork.freedesktop.org/series/105837/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_11835_full -> Patchwork_105837
iling list.
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_pci.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.c | 2 --
include/drm/i915_pciids.h| 25 +++-
3 files changed, 4 insertions(+), 25 deletions(-)
diff --git a/
Small BAR support has now landed, which allows us to add the PCI IDs
that correspond to add-in card designs of DG2 and ATS-M. There's also
one additional MB-down PCI ID that recently appeared (0x5698) so we add
it too.
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
---
drivers/gpu/drm
S_TIMER_MASK,
> FF_MODE2_TDS_TIMER_128,
> 0, false);
> + wa_write_clr_set(wal,
> + RT_CTRL,
> + RT_CTRL_NUMBER_OF_STACKIDS_MASK,
> + REG_FIELD_PREP(RT_CTRL_NUMBER_OF_STACKIDS_MASK,
> + NUMBER_OF_STACKIDS_512));
> }
>
> /*
> --
> 2.34.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
form-specific register and not something that applies to the Xe_HP
architecture as a whole.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 8
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 4 ++--
dr
.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 1 +
drivers/gpu/drm/i915/gt/intel_gt_regs.h| 3 +++
drivers/gpu/drm/i915/i915_reg.h| 17 -
3 files changed, 4 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem
On Thu, Jun 23, 2022 at 07:48:32AM -0700, Souza, Jose wrote:
> On Wed, 2022-06-22 at 15:19 -0700, Matt Roper wrote:
> > On Tue, Jun 21, 2022 at 10:03:04AM -0700, Souza, Jose wrote:
> > > On Fri, 2022-06-17 at 12:28 -0700, Matt Roper wrote:
> > > > On Fri, Jun 17,
On Tue, Jun 21, 2022 at 10:03:04AM -0700, Souza, Jose wrote:
> On Fri, 2022-06-17 at 12:28 -0700, Matt Roper wrote:
> > On Fri, Jun 17, 2022 at 12:06:29PM -0700, José Roberto de Souza wrote:
> > > Gem buffers could still be in use by display after i915_gem_suspend()
> > &
where we should have tabs according to the kernel coding style).
Matt
> }
>
> if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) {
> --
> 2.32.0
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
ni Nikula
> Signed-off-by: Daniele Ceraolo Spurio
Would the config table still get used somehow even though we return
false for ADL-N in has_table()?
Even if it couldn't be used, this change makes the behavior more clear
and explicit.
Reviewed-by: Matt Roper
> ---
> drivers
suspend(i915);
>
> + i915_gem_suspend(i915);
> +
> /*
>* The only requirement is to reboot with display DC states disabled,
>* for now leaving all display power wells in the INIT power domain
> --
> 2.36.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
ggtt->vm.pte_encode = ivb_pte_encode;
> + else
> + ggtt->vm.pte_encode = snb_pte_encode;
> +
> + ggtt->vm.vma_ops.bind_vma= intel_ggtt_bind_vma;
> + ggtt->vm.vma_ops.unbind_vma = intel_ggtt_unbind_vma;
> +
> + return ggtt_probe_common
On Fri, Jun 17, 2022 at 06:57:20AM -0700, Harish Chegondi wrote:
> On Tue, Jun 14, 2022 at 05:10:19PM -0700, Matt Roper wrote:
> > Let's replace the assortment of intel_gt_* and intel_uncore_* functions
> > that operate on MCR registers with a clean
On Thu, Jun 16, 2022 at 05:31:00PM +0530, Anshuman Gupta wrote:
> DG2 NB SKU need to distinguish between MBD and AIC to probe
> the VRAM Self Refresh feature support. Adding those sub platform
> accordingly.
>
> Cc: Matt Roper
> Signed-off-by: Anshuman Gupta
> ---
&g
ssues/4281
> [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
> [i915#4369]: https://gitlab.freedesktop.org/drm/intel/issues/4369
> [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
> [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
> [i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
> [i915#4893]: https://gitlab.freedesktop.org/drm/intel/issues/4893
> [i915#4939]: https://gitlab.freedesktop.org/drm/intel/issues/4939
> [i915#5099]: https://gitlab.freedesktop.org/drm/intel/issues/5099
> [i915#51]: https://gitlab.freedesktop.org/drm/intel/issues/51
> [i915#5161]: https://gitlab.freedesktop.org/drm/intel/issues/5161
> [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
> [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
> [i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
> [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
> [i915#5287]: https://gitlab.freedesktop.org/drm/intel/issues/5287
> [i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
> [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
> [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
> [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
> [i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
> [i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
> [i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
> [i915#5591]: https://gitlab.freedesktop.org/drm/intel/issues/5591
> [i915#5939]: https://gitlab.freedesktop.org/drm/intel/issues/5939
> [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
> [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
> [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
>
>
> Build changes
> -
>
> * Linux: CI_DRM_11758 -> Patchwork_105134v1
>
> CI-20190529: 20190529
> CI_DRM_11758: a2644b16f1f05a1a6eff99d7076bfa0e770bdeb6 @
> git://anongit.freedesktop.org/gfx-ci/linux
> IGT_6526: 02888400228efbb29437726aa04114575ea939c3 @
> https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
> Patchwork_105134v1: a2644b16f1f05a1a6eff99d7076bfa0e770bdeb6 @
> git://anongit.freedesktop.org/gfx-ci/linux
> piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
> git://anongit.freedesktop.org/piglit
>
> == Logs ==
>
> For more details see:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105134v1/index.html
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
> * Linux: CI_DRM_11758 -> Patchwork_105134v1
>
> CI-20190529: 20190529
> CI_DRM_11758: a2644b16f1f05a1a6eff99d7076bfa0e770bdeb6 @
> git://anongit.freedesktop.org/gfx-ci/linux
> IGT_6526: 02888400228efbb29437726aa04114575ea939c3 @
> https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
> Patchwork_105134v1: a2644b16f1f05a1a6eff99d7076bfa0e770bdeb6 @
> git://anongit.freedesktop.org/gfx-ci/linux
>
>
> ### Linux commits
>
> aa8c692ba084 drm/i915/gt: Cleanup interface for MCR operations
> 6be8d7758465 drm/i915/gt: Move multicast register handling to a dedicated file
>
> == Logs ==
>
> For more details see:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105134v1/index.html
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
On Mon, Jun 13, 2022 at 11:14:39PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> adl-s needs the combo PLL DCO fraction w/a as well.
> Get us slightly more accurate clock out of the PLL.
>
> Cc: sta...@vger.kernel.org
> Signed-off-by: Ville Syrjälä
Re
ntel/issues/4525
> [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
> [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
> [i915#4613]: https://gitlab.freedesktop
ns to
clarify the difference between "_fw" and non-"_fw" forms.
Matt Roper (2):
drm/i915/gt: Move multicast register handling to a dedicated file
drm/i915/gt: Cleanup interface for MCR operations
Documentation/gpu/i915.rst | 12 +
drivers/gpu/drm/i915/Mak
for more recent
platforms; these days MCR steering applies to more types of replication
than just slice/subslice.
v2:
- Reference the new kerneldoc from i915.rst. (Jani)
- Tweak the wording of the documentation for a couple functions to
clarify the difference between "_fw" and
functions have been moved to the new .c/.h as-is.
Function renames and updates to operate in a more consistent manner will
be done in subsequent patches.
Signed-off-by: Matt Roper
Acked-by: Jani Nikula
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gem
Looks like the logs links finally work (there was probably a big backlog
to upload them after the gitlab downtime). The module_reload log shows
and ext4 filesystem panic (not graphics-related). The syncobj_basic
failure is an unexpected incomplete; no graphics errors in the log that
I can see, al
On Tue, Jun 14, 2022 at 07:20:48PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/pvc: Adjust EU per SS according to HAS_ONE_EU_PER_FUSE_BIT()
> URL : https://patchwork.freedesktop.org/series/105010/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_
conflicts with real workarounds are flagged.
Bspec: 72161
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 5 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 +
2 files changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/dri
for more recent
platforms; these days MCR steering applies to more types of replication
than just slice/subslice.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 2 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 33 ++-
drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
y non-terminated
instance
* intel_gt_mcr_unicast_write -- unicast write to specific instance
* intel_gt_mcr_multicast_write[_fw] -- multicast write to all instances
Matt Roper (2):
drm/i915/gt: Move multicast register handling to a dedicated file
drm/i915/gt: Cleanup interface for MCR opera
functions have been moved to the new .c/.h as-is.
Function renames and updates to operate in a more consistent manner will
be done in subsequent patches.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 1 +
drivers/gpu
If we're treating each bit in the EU fuse register as a single EU
instead of a pair of EUs, then that also cuts the number of potential
EUs per subslice in half.
Fixes: 5ac342ef84d7 ("drm/i915/pvc: Add SSEU changes")
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_s
On Thu, Jun 09, 2022 at 02:17:54PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/pvc: Add register steering (rev2)
> URL : https://patchwork.freedesktop.org/series/104691/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_11740_full -> Patchwork_104
we'll rename the HAS_MSLICES() macro to HAS_MSLICE_STEERING().
PVC hardware still has units referred to as mslices, but there's no
register steering based on mslice for this platform.
v2:
- Rebase on other recent changes
- Swap two table rows to keep table sorted & easy to read. (Har
issues/4812
> [i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
> [i915#4842]: https://gitlab.freedesktop.org/drm/intel/issues/4842
> [i915#4852]:
On Wed, Jun 08, 2022 at 08:23:34AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/xehp: Correct steering initialization
> URL : https://patchwork.freedesktop.org/series/104842/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_11732_full -> Patchwork
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