Re: [Intel-gfx] [PATCH v2 3/4] drm/i915/dmabuf: dmabuf cleanup

On Fri, 28 Oct 2022 at 16:51, Matthew Auld wrote: > > From: "Michael J. Ruhl" > > Some minor cleanup of some variables for consistency. > > Normalize struct sg_table to sgt. > Normalize struct dma_buf_attachment to attach. > checkpatch issues sizeof(), !NU

Re: [Intel-gfx] [PATCH v2 4/4] drm/i915/dmabuf: Use scatterlist for_each_sg API

On Fri, 28 Oct 2022 at 16:51, Matthew Auld wrote: > > From: "Michael J. Ruhl" > > Update open coded for loop to use the standard scatterlist > for_each_sg API. > > Cc: Tvrtko Ursulin > Signed-off-by: Michael J. Ruhl Reviewed-by: Matthew Auld > Signed-o

[Intel-gfx] [PATCH v2 4/4] drm/i915/dmabuf: Use scatterlist for_each_sg API

From: "Michael J. Ruhl" Update open coded for loop to use the standard scatterlist for_each_sg API. Cc: Tvrtko Ursulin Signed-off-by: Michael J. Ruhl Signed-off-by: Matthew Auld --- drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletion

[Intel-gfx] [PATCH v2 3/4] drm/i915/dmabuf: dmabuf cleanup

From: "Michael J. Ruhl" Some minor cleanup of some variables for consistency. Normalize struct sg_table to sgt. Normalize struct dma_buf_attachment to attach. checkpatch issues sizeof(), !NULL updates. Cc: Tvrtko Ursulin Signed-off-by: Michael J. Ruhl Signed-off-by: Ma

[Intel-gfx] [PATCH v2 2/4] drm/i915/selftests: exercise GPU access from the importer

the CPU side. v2: Switch over to igt_gpu_fill_dw(), which looks to be more widely supported than the migrate stuff (at least OOTB). References: https://gitlab.freedesktop.org/drm/intel/-/issues/7306 Signed-off-by: Matthew Auld Cc: Lionel Landwerlin Cc: Tvrtko Ursulin Cc: Ville Syrjälä Cc: Michael J

[Intel-gfx] [PATCH v2 1/4] drm/i915/dmabuf: fix sg_table handling in map_dma_buf

mapping the first struct page (and any physically contiguous pages following it), even if there is potentially lots more data to follow. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/7306 Signed-off-by: Matthew Auld Cc: Lionel Landwerlin Cc: Tvrtko Ursulin Cc: Ville Syrjälä Cc: Michael J

Re: [Intel-gfx] [PATCH 1/2] drm/i915/dmabuf: fix sg_table handling in map_dma_buf

On 28/10/2022 14:55, Ruhl, Michael J wrote: -Original Message- From: Intel-gfx On Behalf Of Matthew Auld Sent: Thursday, October 27, 2022 11:27 AM To: intel-gfx@lists.freedesktop.org Subject: [Intel-gfx] [PATCH 1/2] drm/i915/dmabuf: fix sg_table handling in map_dma_buf We need

[Intel-gfx] [PATCH v2] drm/i915/userptr: restore probe_range behaviour

://gitlab.freedesktop.org/drm/intel/-/issues/7247 Testcase: igt@gem_userptr_blits@probe Fixes: f683b9d61319 ("i915: use the VMA iterator") Reported-by: kernel test robot Signed-off-by: Matthew Auld Cc: Tvrtko Ursulin Cc: Matthew Wilcox (Oracle) Cc: Liam R. Howlett Cc: Vlastimil Babka C

[Intel-gfx] [PATCH 2/2] drm/i915/selftests: exercise GPU access from the importer

the CPU side. References: https://gitlab.freedesktop.org/drm/intel/-/issues/7306 Signed-off-by: Matthew Auld Cc: Lionel Landwerlin Cc: Tvrtko Ursulin Cc: Ville Syrjälä --- .../drm/i915/gem/selftests/i915_gem_dmabuf.c | 37 ++- 1 file changed, 35 insertions(+), 2 deletions(-) diff

[Intel-gfx] [PATCH 1/2] drm/i915/dmabuf: fix sg_table handling in map_dma_buf

mapping the first struct page (and any physically contiguous pages following it), even if there is potentially lots more data to follow. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/7306 Signed-off-by: Matthew Auld Cc: Lionel Landwerlin Cc: Tvrtko Ursulin Cc: Ville Syrjälä --- drivers

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Revert "drm/i915/uapi: expose GTT alignment"

On 26/10/2022 18:53, Vudum, Lakshminarayana wrote: @Auld, Matthew Can you check if this is related to your patch? Looks new to me. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/shard-skl9/igt@i915_selftest@m...@requests.html#dmesg-warnings16 For sure unrelated to this series.

Re: [Intel-gfx] [PATCH v5 19/19] drm/i915/vm_bind: Render VM_BIND documentation

On 25/10/2022 07:59, Niranjana Vishwanathapura wrote: Update i915 documentation to include VM_BIND changes and render all VM_BIND related documentation. Signed-off-by: Niranjana Vishwanathapura Thanks for adding this, Reviewed-by: Matthew Auld

Re: [Intel-gfx] [PATCH v5 09/19] drm/i915/vm_bind: Add out fence support

va->fence.flags & I915_TIMELINE_FENCE_WAIT) + ret = -EINVAL; I guess also: if (flags & __I915_TIMELINE_FENCE_UNKNOWN_FLAGS) Reviewed-by: Matthew Auld + obj = i915_gem_object_lookup(file, va->handle); if (!obj) return -ENOENT; @@ -237

Re: [Intel-gfx] [PATCH v5 16/19] drm/i915/vm_bind: userptr dma-resv changes

ana Vishwanathapura Signed-off-by: Andi Shyti Reviewed-by: Matthew Auld

Re: [Intel-gfx] [PATCH v5 17/19] drm/i915/vm_bind: Limit vm_bind mode to non-recoverable contexts

On 25/10/2022 07:59, Niranjana Vishwanathapura wrote: Only support vm_bind mode with non-recoverable contexts. With new vm_bind mode with eb3 submission path, we need not support older recoverable contexts. Signed-off-by: Niranjana Vishwanathapura Reviewed-by: Matthew Auld

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Revert "drm/i915/uapi: expose GTT alignment"

On 26/10/2022 08:47, Patchwork wrote: *Patch Details* *Series:* Revert "drm/i915/uapi: expose GTT alignment" *URL:* https://patchwork.freedesktop.org/series/110041/ *State:*failure *Details:*

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for Revert "drm/i915/uapi: expose GTT alignment"

On 25/10/2022 17:37, Patchwork wrote: *Patch Details* *Series:* Revert "drm/i915/uapi: expose GTT alignment" *URL:* https://patchwork.freedesktop.org/series/110041/ *State:*failure *Details:*

Re: [Intel-gfx] [PATCH v2] drm/ttm: rework on ttm_resource to use size_t type

On Tue, 25 Oct 2022 at 16:51, Somalapuram Amaranath wrote: > > Change ttm_resource structure from num_pages to size_t size in bytes. > v1 -> v2: change PFN_UP(dst_mem->size) to ttm->num_pages > v1 -> v2: change bo->resource->size to bo->base.size at some places > v1 -> v2: remove the local

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for Revert "drm/i915/uapi: expose GTT alignment"

On 24/10/2022 12:55, Patchwork wrote: *Patch Details* *Series:* Revert "drm/i915/uapi: expose GTT alignment" *URL:* https://patchwork.freedesktop.org/series/110041/ *State:*failure *Details:*

[Intel-gfx] [PATCH] drm/i915/userptr: restore probe_range behaviour

Fixes: f683b9d61319 ("i915: use the VMA iterator") Reported-by: kernel test robot Signed-off-by: Matthew Auld Cc: Tvrtko Ursulin Cc: Matthew Wilcox (Oracle) Cc: Vlastimil Babka Cc: Yu Zhao --- drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 3 ++- 1 file changed, 2 insertions(+),

Re: [Intel-gfx] [PATCH] drm/i915: Remove unwanted ghost obj check

On 24/10/2022 15:45, Nirmoy Das wrote: vm_fault_ttm() should not expect ttm ghost obj so remove that check. Suggested-by: Matthew Auld Signed-off-by: Nirmoy Das Reviewed-by: Matthew Auld

Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/dgfx: Grab wakeref at i915_ttm_unmap_virtual

). v2: - Removed lmem_userfault_{list,lock} from intel_gt. [Matt Auld] Fixes: ad74457a6b5a ("drm/i915/dgfx: Release mmap on rpm suspend") Suggested-by: Matthew Auld Signed-off-by: Anshuman Gupta Reviewed-by: Matthew Auld

Re: [Intel-gfx] [PATCH v2 1/2] drm/i915: Encapsulate lmem rpm stuff in intel_runtime_pm

index d9160e3ff4af..d0c04af2a6f3 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.h +++ b/drivers/gpu/drm/i915/intel_runtime_pm.h @@ -53,6 +53,28 @@ struct intel_runtime_pm { bool irqs_enabled; bool no_wakeref_tracking; + /** Nit: that's not properly formatted kernel-doc. Reviewed-by

[Intel-gfx] [PATCH] Revert "drm/i915/uapi: expose GTT alignment"

The process for merging uAPI is to have UMD side ready and reviewed and merged before merging. Revert for now until that is ready. This reverts commit d54576a074a29d4901d0a693cd84e1a89057f694. Reported-by: Joonas Lahtinen Signed-off-by: Matthew Auld Cc: Lionel Landwerlin Cc: Michal Mrozek Cc

Re: [Intel-gfx] [PATCH v4 13/17] drm/i915/vm_bind: Update i915_vma_verify_bind_complete()

On 20/10/2022 17:51, Niranjana Vishwanathapura wrote: On Thu, Oct 20, 2022 at 10:16:06AM +0100, Matthew Auld wrote: On 19/10/2022 19:28, Niranjana Vishwanathapura wrote: On Wed, Oct 19, 2022 at 05:07:31PM +0100, Matthew Auld wrote: On 18/10/2022 08:16, Niranjana Vishwanathapura wrote: Ensure

Re: [Intel-gfx] [PATCH v4 15/17] drm/i915/vm_bind: Handle persistent vmas in execbuf3

On 18/10/2022 08:16, Niranjana Vishwanathapura wrote: Handle persistent (VM_BIND) mappings during the request submission in the execbuf3 path. v2: Ensure requests wait for bindings to complete. v3: Remove short term pinning with PIN_VALIDATE flag. Individualize fences before adding to

Re: [Intel-gfx] [PATCH v4 15/17] drm/i915/vm_bind: Handle persistent vmas in execbuf3

to dma_resv obj. Signed-off-by: Niranjana Vishwanathapura Signed-off-by: Andi Shyti Reviewed-by: Matthew Auld

Re: [Intel-gfx] [PATCH v4 16/17] drm/i915/vm_bind: userptr dma-resv changes

On 18/10/2022 08:16, Niranjana Vishwanathapura wrote: For persistent (vm_bind) vmas of userptr BOs, handle the user page pinning by using the i915_gem_object_userptr_submit_init() /done() functions v2: Do not double add vma to vm->userptr_invalidated_list Signed-off-by: Niranjana

[Intel-gfx] [PATCH] drm/i915: use i915_sg_dma_sizes() for internal backend

do for other backends, switch over to calling i915_sg_dma_sizes() after mapping the pages. Signed-off-by: Matthew Auld Cc: Andrzej Hajda --- drivers/gpu/drm/i915/gem/i915_gem_internal.c | 5 + 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/gem

Re: [Intel-gfx] [PATCH v4 13/17] drm/i915/vm_bind: Update i915_vma_verify_bind_complete()

On 19/10/2022 19:28, Niranjana Vishwanathapura wrote: On Wed, Oct 19, 2022 at 05:07:31PM +0100, Matthew Auld wrote: On 18/10/2022 08:16, Niranjana Vishwanathapura wrote: Ensure i915_vma_verify_bind_complete() handles case where bind is not initiated. Also make it non static, add documentation

Re: [Intel-gfx] [PATCH v4 13/17] drm/i915/vm_bind: Update i915_vma_verify_bind_complete()

ete() - Check for the bind completion of the vma + * @vma: vma to check for bind completion Maybe mention the locking since this is now more than just DEBUG_GEM stuff. I assume we need the object lock or otherwise some guarantee that the vma is pinned? Reviewed-by: Matthew Auld + * + * Retu

Re: [Intel-gfx] [PATCH v4 14/17] drm/i915/vm_bind: Expose i915_request_await_bind()

; /* do not reserve memory to prevent deadlocks */ #define __EXEC_OBJECT_NO_RESERVE BIT(31) +static inline int +i915_request_await_bind(struct i915_request *rq, struct i915_vma *vma) Some kernel doc might be good? Reviewed-by: Matthew Auld +{ + return __i915_request_await_exclusive(rq

Re: [Intel-gfx] [PATCH v4 12/17] drm/i915/vm_bind: Implement I915_GEM_EXECBUFFER3 ioctl

On 18/10/2022 08:16, Niranjana Vishwanathapura wrote: Implement new execbuf3 ioctl (I915_GEM_EXECBUFFER3) which only works in vm_bind mode. The vm_bind mode only works with this new execbuf3 ioctl. The new execbuf3 ioctl will not have any list of objects to validate bind as all required objects

Re: [Intel-gfx] [PATCH v4 09/17] drm/i915/vm_bind: Add out fence support

On 19/10/2022 03:43, Niranjana Vishwanathapura wrote: On Tue, Oct 18, 2022 at 04:28:07PM +0100, Matthew Auld wrote: On 18/10/2022 08:16, Niranjana Vishwanathapura wrote: Add support for handling out fence for vm_bind call. v2: Reset vma->vm_bind_fence.syncobj to NULL at the end     of vm_b

Re: [Intel-gfx] [PATCH] drm/i915/selftests: add prefetch padding to store_dw batchbuffer

On 19/10/2022 10:12, Matthew Auld wrote: On 19/10/2022 08:12, Andrzej Hajda wrote: Instruction prefetch mechanism requires that 512 bytes after the last command should be readable by EU. Otherwise DMAR errors and engine hangs can happen. Closes: https://gitlab.freedesktop.org/drm/intel

Re: [Intel-gfx] [PATCH] drm/i915/selftests: add prefetch padding to store_dw batchbuffer

On 19/10/2022 08:12, Andrzej Hajda wrote: Instruction prefetch mechanism requires that 512 bytes after the last command should be readable by EU. Otherwise DMAR errors and engine hangs can happen. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5278 Signed-off-by: Andrzej Hajda Is

Re: [Intel-gfx] [PATCH v4 15/17] drm/i915/vm_bind: Handle persistent vmas in execbuf3

On 18/10/2022 08:16, Niranjana Vishwanathapura wrote: Handle persistent (VM_BIND) mappings during the request submission in the execbuf3 path. v2: Ensure requests wait for bindings to complete. v3: Remove short term pinning with PIN_VALIDATE flag. Individualize fences before adding to

Re: [Intel-gfx] [PATCH v4 12/17] drm/i915/vm_bind: Implement I915_GEM_EXECBUFFER3 ioctl

xt specified by @ctx_id. +*/ + __u32 engine_idx; + + /** +* @batch_address: Batch gpu virtual address/es. +* +* For normal submission, it is the gpu virtual address of the batch +* buffer. For parallel submission, it is a pointer to an array of +* batch b

Re: [Intel-gfx] [PATCH v4 17/17] drm/i915/vm_bind: Add uapi for user to enable vm_bind_mode

check with i915_gem_vm_is_vm_bind_mode() Reviewed-by: Matthew Auld Signed-off-by: Niranjana Vishwanathapura Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gem/i915_gem_context.c | 25 +++-- drivers/gpu/drm/i915/gem/i915_gem_context.h | 3 +-- drivers/gpu/drm/i915/gt/intel

Re: [Intel-gfx] [PATCH v4 09/17] drm/i915/vm_bind: Add out fence support

On 18/10/2022 08:16, Niranjana Vishwanathapura wrote: Add support for handling out fence for vm_bind call. v2: Reset vma->vm_bind_fence.syncobj to NULL at the end of vm_bind call. v3: Remove vm_unbind out fence uapi which is not supported yet. Signed-off-by: Niranjana Vishwanathapura

Re: [Intel-gfx] [PATCH v3 09/17] drm/i915/vm_bind: Add out fence support

On 14/10/2022 07:48, Niranjana Vishwanathapura wrote: On Sun, Oct 09, 2022 at 11:58:18PM -0700, Niranjana Vishwanathapura wrote: Add support for handling out fence for vm_bind call. v2: Reset vma->vm_bind_fence.syncobj to NULL at the end    of vm_bind call. Signed-off-by: Niranjana

Re: [Intel-gfx] [PATCH v3 2/2] drm/i915/uapi: expose GTT alignment

On 14/10/2022 17:51, Jordan Justen wrote: On 2022-10-14 03:58:12, Matthew Auld wrote: On 14/10/2022 08:20, Jordan Justen wrote: Acked-by: Jordan Justen Thanks. Can I take that as ack for merging the series from Mesa POV? I think Lionel was going to test this, but I think keeps getting

Re: [Intel-gfx] [PATCH] drm/i915: Refactor ttm ghost obj detection

l_wakeref_t wakeref = 0; vm_fault_t ret; int idx; - obj = i915_ttm_to_gem(bo); - if (!obj) + if (i915_ttm_is_ghost_object(bo)) return VM_FAULT_SIGBUS; I think this one can be dropped, maybe in a separate patch? Otherwise looks good to me, Reviewe

Re: [Intel-gfx] [PATCH v3 2/2] drm/i915/uapi: expose GTT alignment

04:49:15, Matthew Auld wrote: On some platforms we potentially have different alignment restrictions depending on the memory type. We also now have different alignment restrictions for the same region across different kernel versions. Extend the region query to return the minimum required GTT

Re: [Intel-gfx] [PATCH] drm/i915/ttm: Fix access_memory null pointer exception

On 14/10/2022 11:38, Das, Nirmoy wrote: Hi Matt, On 10/14/2022 12:13 PM, Matthew Auld wrote: On 14/10/2022 10:27, Das, Nirmoy wrote: Hi Matt On 10/14/2022 10:39 AM, Matthew Auld wrote: On 13/10/2022 18:56, Jonathan Cavitt wrote: i915_ttm_to_gem can return a NULL pointer, which

Re: [Intel-gfx] [PATCH] drm/i915/ttm: Fix access_memory null pointer exception

On 14/10/2022 10:27, Das, Nirmoy wrote: Hi Matt On 10/14/2022 10:39 AM, Matthew Auld wrote: On 13/10/2022 18:56, Jonathan Cavitt wrote: i915_ttm_to_gem can return a NULL pointer, which is dereferenced in i915_ttm_access_memory without first checking if it is NULL.  Inspecting

Re: [Intel-gfx] [PATCH] drm/i915/ttm: Fix access_memory null pointer exception

On 14/10/2022 09:56, Andi Shyti wrote: On Fri, Oct 14, 2022 at 09:39:52AM +0100, Matthew Auld wrote: On 13/10/2022 18:56, Jonathan Cavitt wrote: i915_ttm_to_gem can return a NULL pointer, which is dereferenced in i915_ttm_access_memory without first checking if it is NULL. Inspecting

Re: [Intel-gfx] [PATCH] drm/i915/ttm: Fix access_memory null pointer exception

t access_memory") Signed-off-by: Jonathan Cavitt Suggested-by: John C Harrison CC: Matthew Auld CC: Andrzej Hajda CC: Nirmoy Das CC: Andi Shyti --- drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/g

Re: [Intel-gfx] [PATCH] drm/i915/dgfx: Temporary hammer to keep autosuspend control 'on'

On 12/10/2022 15:57, Rodrigo Vivi wrote: On Wed, Oct 12, 2022 at 10:48:30AM +0100, Matthew Auld wrote: On 12/10/2022 09:34, Anshuman Gupta wrote: DGFX platforms has lmem and cpu can access the lmem objects via mmap and i915 internal i915_gem_object_pin_map() for i915 own usages. Both

Re: [Intel-gfx] [PATCH] drm/i915: add wait and lock to i915_vma_move_to_active

On 12/10/2022 13:43, Andrzej Hajda wrote: Since almost all calls to i915_vma_move_to_active are prepended with i915_request_await_object and many of them are surrounded with i915_vma_lock, let's put both into i915_vma_move_to_active and add i915_vma_move_to_active_unlocked helper to handle

Re: [Intel-gfx] [PATCH v3 12/17] drm/i915/vm_bind: Implement I915_GEM_EXECBUFFER3 ioctl

On 10/10/2022 07:58, Niranjana Vishwanathapura wrote: Implement new execbuf3 ioctl (I915_GEM_EXECBUFFER3) which only works in vm_bind mode. The vm_bind mode only works with this new execbuf3 ioctl. The new execbuf3 ioctl will not have any list of objects to validate bind as all required objects

Re: [Intel-gfx] [PATCH] drm/i915/dgfx: Temporary hammer to keep autosuspend control 'on'

On 12/10/2022 09:34, Anshuman Gupta wrote: DGFX platforms has lmem and cpu can access the lmem objects via mmap and i915 internal i915_gem_object_pin_map() for i915 own usages. Both of these methods has pre-requisite requirement to keep GFX PCI endpoint in D0 for a supported iomem transaction

Re: [Intel-gfx] [PATCH v3 06/17] drm/i915/vm_bind: Support for VM private BOs

On 11/10/2022 17:27, Matthew Auld wrote: On 10/10/2022 07:58, Niranjana Vishwanathapura wrote: Each VM creates a root_obj and shares it with all of its private objects to use it as dma_resv object. This has a performance advantage as it requires a single dma_resv object update for all private

Re: [Intel-gfx] [PATCH v3 05/17] drm/i915/vm_bind: Implement bind and unbind of object

ing with PIN_VALIDATE flag. Signed-off-by: Niranjana Vishwanathapura Signed-off-by: Prathap Kumar Valsan Signed-off-by: Andi Shyti Reviewed-by: Matthew Auld

Re: [Intel-gfx] [PATCH v3 06/17] drm/i915/vm_bind: Support for VM private BOs

On 10/10/2022 07:58, Niranjana Vishwanathapura wrote: Each VM creates a root_obj and shares it with all of its private objects to use it as dma_resv object. This has a performance advantage as it requires a single dma_resv object update for all private BOs vs list of dma_resv objects update for

Re: [Intel-gfx] [PATCH v3 07/17] drm/i915/vm_bind: Add support to handle object evictions

On 11/10/2022 01:55, Niranjana Vishwanathapura wrote: On Mon, Oct 10, 2022 at 05:43:47PM -0700, Niranjana Vishwanathapura wrote: On Mon, Oct 10, 2022 at 06:15:02PM +0100, Matthew Auld wrote: On 10/10/2022 17:11, Niranjana Vishwanathapura wrote: On Mon, Oct 10, 2022 at 02:30:49PM +0100

Re: [Intel-gfx] [PATCH v5 4/5] drm/i915/display: consider DG2_RC_CCS_CC when migrating buffers

On 11/10/2022 16:03, Tvrtko Ursulin wrote: On 11/10/2022 15:39, Matthew Auld wrote: Hi, On 11/10/2022 14:54, Tvrtko Ursulin wrote: Hi Matt, On 04/10/2022 14:19, Matthew Auld wrote: For these types of display buffers, we need to able to CPU access some part of the backing memory

Re: [Intel-gfx] [PATCH v5 4/5] drm/i915/display: consider DG2_RC_CCS_CC when migrating buffers

Hi, On 11/10/2022 14:54, Tvrtko Ursulin wrote: Hi Matt, On 04/10/2022 14:19, Matthew Auld wrote: For these types of display buffers, we need to able to CPU access some part of the backing memory in prepare_plane_clear_colors(). As a result we need to ensure we always place in the mappable

Re: [Intel-gfx] [PATCH v3 07/17] drm/i915/vm_bind: Add support to handle object evictions

On 10/10/2022 17:11, Niranjana Vishwanathapura wrote: On Mon, Oct 10, 2022 at 02:30:49PM +0100, Matthew Auld wrote: On 10/10/2022 07:58, Niranjana Vishwanathapura wrote: Support eviction by maintaining a list of evicted persistent vmas for rebinding during next submission. Ensure the list do

Re: [Intel-gfx] [PATCH v3 07/17] drm/i915/vm_bind: Add support to handle object evictions

__i915_vma_unbind_async() case. Acked-by: Matthew Auld Signed-off-by: Niranjana Vishwanathapura Signed-off-by: Andi Shyti --- .../drm/i915/gem/i915_gem_vm_bind_object.c| 6 drivers/gpu/drm/i915/gt/intel_gtt.c | 2 ++ drivers/gpu/drm/i915/gt/intel_gtt.h | 4

[Intel-gfx] [PATCH i-g-t] tests/i915/module_load: fix resize-bar on DG1

DG1, as expected only has a fixed sized bar, so attempting to force the BAR size should fail. Update the test to account for such devices, and perform a skip, instead of failing. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/6458 Signed-off-by: Matthew Auld Cc: Nirmoy Das --- tests

Re: [Intel-gfx] [PATCH v2 2/3] drm/i915: Name our BARs based on the spec

; > v2: Fix gvt build > > Signed-off-by: Ville Syrjälä Acked-by: Matthew Auld

Re: [Intel-gfx] [PATCH 3/3] drm/i915: s/HAS_BAR2_SMEM_STOLEN/HAS_LMEMBAR_SMEM_STOLEN/

On Wed, 5 Oct 2022 at 16:42, Ville Syrjala wrote: > > From: Ville Syrjälä > > The fact that LMEMBAR is BAR2 should be of no real interest > to anyone. So use the name of the BAR rather than its index. > > Signed-off-by: Ville Syrjälä Acked-by: Matthew Auld

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Name our BARs based on the spec

On Wed, 5 Oct 2022 at 16:42, Ville Syrjala wrote: > > From: Ville Syrjälä > > We use all kinds of weird names for our base address registers. > Take the names from the spec and stick to them to avoid confusing > everyone. > > The only exceptions are IOBAR and LMEMBAR since naming them >

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Extract intel_mmio_bar()

On Wed, 5 Oct 2022 at 16:42, Ville Syrjala wrote: > > From: Ville Syrjälä > > We have the same code to determine the MMIO BAR in > two places. Collect it to a single place. > > Signed-off-by: Ville Syrjälä Reviewed-by: Matthew Auld

[Intel-gfx] [PATCH 2/2] drm/i915: restore stolen memory behaviour for DG2

m_size against the BAR size. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/7007 Fixes: dbb2ffbfd708 ("drm/i915/mtl: enable local stolen memory") Signed-off-by: Matthew Auld Cc: Aravind Iddamsetty Cc: Lucas De Marchi Cc: Matt Roper --- drivers/gpu/drm/i915/gem/i915_gem_stolen

[Intel-gfx] [PATCH 1/2] drm/i915: add back GEN12_BDSM_MASK

2ffbfd708 ("drm/i915/mtl: enable local stolen memory") Signed-off-by: Matthew Auld Cc: Aravind Iddamsetty Cc: Lucas De Marchi Cc: Matt Roper --- drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gem/i915_g

Re: [Intel-gfx] [PATCH RESEND] drm/i915: Fix display problems after resume

ktop.org/patch/msgid/20220912121957.31310-1-thomas.hellst...@linux.intel.com Cc: Matthew Auld Cc: intel-gfx@lists.freedesktop.org Cc: # v5.18+ Reported-and-tested-by: Kevin Boulain Tested-by: David de Sousa Reviewed-by: Matthew Auld

[Intel-gfx] [PATCH i-g-t v2 4/5] tests/i915/query: sanity check reported GTT alignment

Signed-off-by: Matthew Auld Cc: Andrzej Hajda Cc: Nirmoy Das Reviewed-by: Nirmoy Das --- tests/i915/i915_query.c | 12 1 file changed, 12 insertions(+) diff --git a/tests/i915/i915_query.c b/tests/i915/i915_query.c index 4e43c7cd..366427b4 100644 --- a/tests/i915/i915_query.c +++ b/

[Intel-gfx] [PATCH i-g-t v2 5/5] tests/i915/gem_create: add some basic testing for GTT alignment

Make sure we can always place an object at some GTT address, so long as we adhere to the min GTT alignment for the given region. Signed-off-by: Matthew Auld Cc: Andrzej Hajda Cc: Nirmoy Das Reviewed-by: Nirmoy Das --- tests/i915/gem_create.c | 117 1

[Intel-gfx] [PATCH i-g-t v2 3/5] tests/i915/query: stop checking rsvd0 in region info

No longer reserved, in the near future this will be the GTT alignment. Signed-off-by: Matthew Auld Cc: Andrzej Hajda Cc: Nirmoy Das Reviewed-by: Nirmoy Das --- tests/i915/i915_query.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/tests/i915/i915_query.c b/tests/i915/i915_query.c index

[Intel-gfx] [PATCH i-g-t v2 2/5] tests/i915/query: fix igt_assert_eq_u32

rsvd1 is u64 here. Signed-off-by: Matthew Auld Cc: Andrzej Hajda Cc: Nirmoy Das Reviewed-by: Nirmoy Das --- tests/i915/i915_query.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/i915/i915_query.c b/tests/i915/i915_query.c index 2744421c..b92d7593 100644

[Intel-gfx] [PATCH i-g-t v2 1/5] i915_drm.h sync

Get the small-bar related stuff at: 525e93f6317a ("drm/i915/uapi: add NEEDS_CPU_ACCESS hint"), and drop the local related bits. Signed-off-by: Matthew Auld Cc: Andrzej Hajda Cc: Nirmoy Das Reviewed-by: Nirmoy Das --- include/drm-uapi/i915_drm.h| 182 +---

[Intel-gfx] [PATCH v5 4/5] drm/i915/display: consider DG2_RC_CCS_CC when migrating buffers

eems. Fixes: eb1c535f0d69 ("drm/i915: turn on small BAR support") Reported-by: Jianshui Yu Signed-off-by: Matthew Auld Cc: Ville Syrjälä Cc: Nirmoy Das --- drivers/gpu/drm/i915/display/intel_fb_pin.c | 13 - 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/d

[Intel-gfx] [PATCH v5 2/5] drm/i915/display: handle migration for dpt

xelpd: First stab at DPT support") Signed-off-by: Matthew Auld Cc: Jianshui Yu Cc: Ville Syrjälä Cc: Nirmoy Das --- drivers/gpu/drm/i915/display/intel_fb_pin.c | 51 + 1 file changed, 33 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_f

[Intel-gfx] [PATCH v5 3/5] drm/i915: allow control over the flags when migrating

In the next patch we want to move the object (if the current resource is not compatible), to the mappable part of lmem for some display buffers. Currently that requires being able to unset the I915_BO_ALLOC_GPU_ONLY hint. Signed-off-by: Matthew Auld Cc: Jianshui Yu Cc: Ville Syrjälä Cc: Nirmoy

[Intel-gfx] [PATCH v5 5/5] drm/i915: check memory is mappable in read_from_page

On small-bar systems we could be given something non-mappable here, which leads to nasty oops. Make this nicer by checking if the resource is mappable or not, and return an error otherwise. v2: drop GEM_BUG_ON(flags & I915_BO_ALLOC_GPU_ONLY) Signed-off-by: Matthew Auld Cc: Jianshui Yu

[Intel-gfx] [PATCH v5 1/5] drm/i915: remove the TODO in pin_and_fence_fb_obj

The copy is async (if there even is one), but when later updating the GGTT we always sync against the binding, which will in turn sync against any moves. Signed-off-by: Matthew Auld Cc: Jianshui Yu Cc: Ville Syrjälä Cc: Nirmoy Das Reviewed-by: Nirmoy Das --- drivers/gpu/drm/i915/display

Re: [Intel-gfx] [PATCH v4 2/5] drm/i915/display: handle migration for dpt

On 04/10/2022 12:22, Ville Syrjälä wrote: On Tue, Oct 04, 2022 at 11:33:08AM +0100, Matthew Auld wrote: On platforms like DG2, it looks like the dpt path here is missing the migrate-to-lmem step on discrete platforms. Fixes: 33e7a975103c ("drm/i915/xelpd: First stab at DPT support")

Re: [Intel-gfx] [PATCH v4 4/5] drm/i915/display: consider DG2_RC_CCS_CC when migrating buffers

On 04/10/2022 12:28, Ville Syrjälä wrote: On Tue, Oct 04, 2022 at 11:33:10AM +0100, Matthew Auld wrote: For these types of display buffers, we need to able to CPU access some part of the backing memory in prepare_plane_clear_colors(). As a result we need to ensure we always place

[Intel-gfx] [PATCH v3 2/2] drm/i915/uapi: expose GTT alignment

@gem_create@create-ext-placement-alignment Testcase: igt@i915_query@query-regions-sanity-check Suggested-by: Lionel Landwerlin Signed-off-by: Matthew Auld Cc: Michal Mrozek Cc: Thomas Hellström Cc: Stuart Summers Cc: Jordan Justen Cc: Yang A Shi Cc: Nirmoy Das Cc: Niranjana Vishwanathapura

[Intel-gfx] [PATCH v3 1/2] drm/i915: enable PS64 support for DG2

restrictions, as documented in: commit caa574ffc4aaf4f29b890223878c63e2e7772f62 Author: Matthew Auld Date: Sat Feb 19 00:17:49 2022 +0530 drm/i915/uapi: document behaviour for DG2 64K support On discrete platforms like DG2, we need to support a minimum page size of 64K when dealing

[Intel-gfx] [PATCH v5 4/5] drm/i915/display: consider DG2_RC_CCS_CC when migrating buffers

tary for why we need to CPU access the buffer. - Split out the other changes, so we just consider the display change here. v3: - Handle this in the dpt path. Fixes: eb1c535f0d69 ("drm/i915: turn on small BAR support") Reported-by: Jianshui Yu Signed-off-by: Matthew Auld Cc: Vil

[Intel-gfx] [PATCH v5 5/5] drm/i915: check memory is mappable in read_from_page

On small-bar systems we could be given something non-mappable here, which leads to nasty oops. Make this nicer by checking if the resource is mappable or not, and return an error otherwise. v2: drop GEM_BUG_ON(flags & I915_BO_ALLOC_GPU_ONLY) Signed-off-by: Matthew Auld Cc: Jianshui Yu

[Intel-gfx] [PATCH v5 2/5] drm/i915/display: handle migration for dpt

xelpd: First stab at DPT support") Signed-off-by: Matthew Auld Cc: Jianshui Yu Cc: Ville Syrjälä Cc: Nirmoy Das --- drivers/gpu/drm/i915/display/intel_fb_pin.c | 51 + 1 file changed, 33 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_f

[Intel-gfx] [PATCH v5 3/5] drm/i915: allow control over the flags when migrating

In the next patch we want to move the object (if the current resource is not compatible), to the mappable part of lmem for some display buffers. Currently that requires being able to unset the I915_BO_ALLOC_GPU_ONLY hint. Signed-off-by: Matthew Auld Cc: Jianshui Yu Cc: Ville Syrjälä Cc: Nirmoy

[Intel-gfx] [PATCH v5 1/5] drm/i915: remove the TODO in pin_and_fence_fb_obj

The copy is async (if there even is one), but when later updating the GGTT we always sync against the binding, which will in turn sync against any moves. Signed-off-by: Matthew Auld Cc: Jianshui Yu Cc: Ville Syrjälä Cc: Nirmoy Das Reviewed-by: Nirmoy Das --- drivers/gpu/drm/i915/display

[Intel-gfx] [PATCH v4 4/5] drm/i915/display: consider DG2_RC_CCS_CC when migrating buffers

tary for why we need to CPU access the buffer. - Split out the other changes, so we just consider the display change here. v3: - Handle this in the dpt path. Fixes: eb1c535f0d69 ("drm/i915: turn on small BAR support") Reported-by: Jianshui Yu Signed-off-by: Matthew Auld Cc: Vil

[Intel-gfx] [PATCH v4 5/5] drm/i915: check memory is mappable in read_from_page

On small-bar systems we could be given something non-mappable here, which leads to nasty oops. Make this nicer by checking if the resource is mappable or not, and return an error otherwise. v2: drop GEM_BUG_ON(flags & I915_BO_ALLOC_GPU_ONLY) Signed-off-by: Matthew Auld Cc: Jianshui Yu

[Intel-gfx] [PATCH v4 3/5] drm/i915: allow control over the flags when migrating

In the next patch we want to move the object (if the current resource is not compatible), to the mappable part of lmem for some display buffers. Currently that requires being able to unset the I915_BO_ALLOC_GPU_ONLY hint. Signed-off-by: Matthew Auld Cc: Jianshui Yu Cc: Ville Syrjälä Cc: Nirmoy

[Intel-gfx] [PATCH v4 2/5] drm/i915/display: handle migration for dpt

On platforms like DG2, it looks like the dpt path here is missing the migrate-to-lmem step on discrete platforms. Fixes: 33e7a975103c ("drm/i915/xelpd: First stab at DPT support") Signed-off-by: Matthew Auld Cc: Jianshui Yu Cc: Ville Syrjälä Cc: Nirmoy Das --- drivers/gpu/drm/i9

[Intel-gfx] [PATCH v4 1/5] drm/i915: remove the TODO in pin_and_fence_fb_obj

The copy is async (if there even is one), but when later updating the GGTT we always sync against the binding, which will in turn sync against any moves. Signed-off-by: Matthew Auld Cc: Jianshui Yu Cc: Ville Syrjälä Cc: Nirmoy Das Reviewed-by: Nirmoy Das --- drivers/gpu/drm/i915/display

[Intel-gfx] [PATCH v3] drm/i915/ttm: implement access_memory

/bytes/ when passing in the size of the mapping. References: https://gitlab.freedesktop.org/drm/intel/-/issues/6989 Signed-off-by: Matthew Auld Cc: Andrzej Hajda Cc: Nirmoy Das Cc: Andi Shyti --- drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 45 + 1 file changed, 45 insertions

[Intel-gfx] [PATCH i-g-t 3/4] tests/i915/query: sanity check reported GTT alignment

Ensure the kernel is reporting "normal" values here, based on our current expectations. Signed-off-by: Matthew Auld Cc: Andrzej Hajda Cc: Nirmoy Das --- tests/i915/i915_query.c | 12 ++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/tests/i915/i915_query

[Intel-gfx] [PATCH i-g-t 2/4] tests/i915/query: fix igt_assert_eq_u32

rsvd1 is u64 here. Signed-off-by: Matthew Auld Cc: Andrzej Hajda Cc: Nirmoy Das --- tests/i915/i915_query.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/i915/i915_query.c b/tests/i915/i915_query.c index 2744421c..b92d7593 100644 --- a/tests/i915/i915_query.c +++ b

[Intel-gfx] [PATCH i-g-t 4/4] tests/i915/gem_create: add some basic testing for GTT alignment

Make sure we can always place an object at some GTT address, so long as we adhere to the min GTT alignment for the given region. Signed-off-by: Matthew Auld Cc: Andrzej Hajda Cc: Nirmoy Das --- tests/i915/gem_create.c | 117 1 file changed, 117

[Intel-gfx] [PATCH i-g-t 1/4] i915_drm.h sync

Get the small-bar related stuff at: 525e93f6317a ("drm/i915/uapi: add NEEDS_CPU_ACCESS hint"), and drop the local related bits. Signed-off-by: Matthew Auld Cc: Andrzej Hajda Cc: Nirmoy Das --- include/drm-uapi/i915_drm.h| 182 + lib/i915/i915_d

[Intel-gfx] [PATCH v2] drm/i915/ttm: implement access_memory

://gitlab.freedesktop.org/drm/intel/-/issues/6989 Signed-off-by: Matthew Auld Cc: Andrzej Hajda Cc: Nirmoy Das --- drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 45 + 1 file changed, 45 insertions(+) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c b/drivers/gpu/drm/i915/gem

Re: [Intel-gfx] [PATCH v2 15/17] drm/i915/vm_bind: Handle persistent vmas in execbuf3

On 03/10/2022 07:12, Niranjana Vishwanathapura wrote: Handle persistent (VM_BIND) mappings during the request submission in the execbuf3 path. v2: Ensure requests wait for bindings to complete. Signed-off-by: Niranjana Vishwanathapura Signed-off-by: Andi Shyti ---

Re: [Intel-gfx] [PATCH 14/16] drm/i915/vm_bind: Handle persistent vmas in execbuf3

On 02/10/2022 07:28, Niranjana Vishwanathapura wrote: On Fri, Sep 30, 2022 at 10:47:48AM +0100, Matthew Auld wrote: On 28/09/2022 07:19, Niranjana Vishwanathapura wrote: Handle persistent (VM_BIND) mappings during the request submission in the execbuf3 path. Signed-off-by: Niranjana

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