On Sat, 25 May 2019 12:39:13 +0200, Patchwork
wrote:
== Series Details ==
Series: GuC 32.0.3 (rev5)
URL : https://patchwork.freedesktop.org/series/58760/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6137_full -> Patchwork_13086_full
On Fri, 24 May 2019 15:10:58 +0200, Joonas Lahtinen
wrote:
Quoting Ye, Tony (2019-05-22 14:32:41)
From UMD perspective, when HuC is not working as expected, usually we
look into the kernel log and i915_huc_load_status debugfs to find out
why it's not working. It will be helpful to know the
Define HuC firmware version for Icelake.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: Anusha Srivatsa
Cc: Tony Ye
v2: 8.4.3238 is now available
---
drivers/gpu/drm/i915/intel_huc_fw.c | 12
1 file changed, 12 insertions(+)
diff --git
GuC stores some data in there, which might be stale after a reset.
Reinitialize whole ADS in case any part of it was corrupted during
previous GuC run.
v2: s/reinit/init, update functions descriptions (Tomek/Michal)
v3: reset ADS right before fw upload
Signed-off-by: Michal Wajdeczko
Cc
Define HuC firmware version for Geminilake.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: Anusha Srivatsa
Cc: Tony Ye
---
drivers/gpu/drm/i915/intel_huc_fw.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915
submission bit.
v2: force switch to non-GuC submission mode
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Rodrigo Vivi
Cc: Daniele Ceraolo Spurio
Cc: John Spotswood
Cc: Vinay Belgaumkar
Cc: Tony Ye
Cc: Anusha Srivatsa
Cc: Jeff Mcgee
Cc: Antonio Argen
From: Oscar Mateo
The GuC interrupts now get their own interrupt vector (instead of
sharing a register with the PM interrupts) so handle appropriately.
v2: (Chris)
v3: rebased (Michal)
Bspec: 19820
Signed-off-by: Oscar Mateo
Signed-off-by: Michal Wajdeczko
Cc: Tvrtko Ursulin
Cc: Daniele
Current GuC firmwares identify response message in a different way.
v2: update comments for other H2G bits (Daniele)
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Kelvin Gardiner
Cc: John Spotswood
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_guc_ct.c
With newer GuC firmware it is always ok to ask GuC to update power
domain states. Make it an unconditional initialization step.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: John Spotswood
Reviewed-by: Daniele Ceraolo Spurio
Reviewed-by: John Spotswood
---
drivers/gpu/drm
New GuC firmwares use updated sleep status definitions.
The polling on scratch register 14 is also now required only on suspend
and there is no need to provide the shared page.
v2: include changes for polling and shared page
Signed-off-by: Michal Wajdeczko
Signed-off-by: Daniele Ceraolo Spurio
-by: Michal Wajdeczko
Cc: Rodrigo Vivi
Cc: Tvrtko Ursulin
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/i915_irq.c | 6 +++---
drivers/gpu/drm/i915/intel_guc.c | 8 ++--
drivers/gpu/drm/i915/intel_guc.h | 8 +++-
drivers
Define GuC firmware version for Icelake.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Cc: Anusha Srivatsa
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_guc_fw.c | 11 +++
1 file changed, 11 insertions(+)
diff --git
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
drivers/gpu/drm/i915/intel_huc.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index 3f14e9881a0d..e28ae23de516
New GuC firmwares use updated definitions for the Additional Data
Structures (ADS).
v2: add note about Gen9 definition mismatch (Daniele)
rename __intel_engine_context_size (Daniele)
Signed-off-by: Michal Wajdeczko
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Fernando Pacheco
Cc
Gen11 defines new register for checking HuC authentication status.
Look into the right register and bit.
v2: use reg/mask/value instead of dedicated functions (Daniele)
BSpec: 19686
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Cc: Tony Ye
Cc: Vinay Belgaumkar
Cc
Gen11 GuC firmware expects H2G command messages to be sent over CTB
(command transport buffers).
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: John Spotswood
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
1 file changed, 1
New GuC firmwares require updated boot parameters.
v2: rebased
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Tvrtko Ursulin
Cc: Daniele Ceraolo Spurio
Cc: John Spotswood
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_guc.c | 38
Gen11 defines new more flexible Host-to-GuC interrupt register.
Now the host can write any 32-bit payload to trigger an interrupt
and GuC can additionally read this payload from the register.
Current GuC firmware ignores the payload so we just write 0.
Bspec: 21043
Signed-off-by: Michal
Gen11 adds new set of scratch registers that can be used for MMIO
based Host-to-Guc communication. Due to limited number of these
registers it is expected that host will use them only for command
transport buffers (CTB) communication setup if one is available.
Bspec: 21044
Signed-off-by: Michal
New GuC firmwares use different action code value for this command.
Signed-off-by: Michal Wajdeczko
Cc: John Spotswood
Cc: Daniele Ceraolo Spurio
Reviewed-by: Daniele Ceraolo Spurio
Reviewed-by: John Spotswood
---
drivers/gpu/drm/i915/intel_guc_fwif.h | 2 +-
1 file changed, 1 insertion
Define GuC firmware version for Geminilake.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_guc_fw.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c
b/drivers/gpu/drm/i915
There are few minor changes in the CSS header related to the version
numbering in new GuC firmwares. Update our definition and start using
common tools for extracting bitfields.
v2: drop deprecated prod_preprod_fw field, replace unions with bit defs
Signed-off-by: Michal Wajdeczko
Cc: Daniele
)
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Daniele Ceraolo Spurio
Cc: Rodrigo Vivi
Cc: Anusha Srivatsa
Cc: Jeff Mcgee
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_guc_fw.c | 75 -
1 file changed, 41 insertions(+), 34 deletions
mode
v4: rebased + newer HuC + GLK
Cc: Joonas Lahtinen
Cc: Martin Peres
Cc: Chris Wilson
Cc: Rodrigo Vivi
Cc: Tony Ye
Michal Wajdeczko (20):
drm/i915/guc: Change platform default GuC mode
drm/i915/guc: Don't allow GuC submission
drm/i915/guc: Update GuC firmware versions and names
Today our most desired GuC configuration is to only enable HuC
if it is available and we really don't care about GuC submission.
Change platform default GuC mode to match our desire.
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Rodrigo Vivi
Cc: Daniele Ceraolo
and upcoming firmware still expect graceful
cleanup.
v2: update commit msg
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_guc_ct.h | 5 +
drivers/gpu/drm/i915/intel_uc.c | 13 -
2 files changed, 17 insertions(+), 1
On Wed, 22 May 2019 22:06:53 +0200, Chris Wilson
wrote:
Quoting Michal Wajdeczko (2019-05-22 20:32:02)
Knowing that GuC will be reset soon, we may stop all communication
immediately without doing graceful cleanup as it is not needed.
The difference between stop and disable
On Wed, 22 May 2019 22:53:11 +0200, Patchwork
wrote:
== Series Details ==
Series: GuC fixes (rev2)
URL : https://patchwork.freedesktop.org/series/60795/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6123 -> Patchwork_13075
On Wed, 22 May 2019 22:19:47 +0200, Chris Wilson
wrote:
Quoting Michal Wajdeczko (2019-05-22 20:00:57)
Without breaking existing usage, slightly update HuC status codes
to provide more info to the clients:
1 if HuC firmware is loaded and verified,
0 if HuC firmware is not enabled
We were testing full GPU reset in atomic context without correctly
wrapping it by prepare/finish steps. This could confuse our GuC
reset handling code.
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_reset.c | 2 ++
1 file changed, 2 insertions(+)
diff
Split igt_atomic_reset selftests into separate full & engines parts,
so we can move former to the dedicated reset selftests file.
While here change engines test to loop first over atomic phases and
then loop over available engines.
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
---
dri
Explicitly sanitize GuC/HuC on load failure and when we finish
using them to make sure our fw state tracking is always correct.
While around, use new helper in uc_reset_prepare.
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_uc.c
We may skip reset preparation steps if GuC is already sanitized.
v2: replace USES_GUC with guc_is_loaded
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_uc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers
We already have helper function for checking GuC firmware
load status. Replace existing open-coded checks.
v2: drop redundant USES_GUC check
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
---
drivers/gpu/drm/i915/intel_uc.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions
This function just check our software flag, while 'is_alive'
may suggest that we are checking runtime firmware status.
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_guc.h| 10 +-
drivers/gpu/drm/i915
igt_global_reset and igt_wedged_reset testcases are first candidates.
Suggested-by: Chris Wilson
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_reset.c | 4 +
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 50
drivers/gpu/drm/i915/gt
Knowing that GuC will be reset soon, we may stop all communication
immediately without doing graceful cleanup as it is not needed.
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_guc_ct.h | 5 +
drivers/gpu/drm/i915/intel_uc.c
We should not attempt to unwind GuC hardware/firmware setup
if we already have sanitized GuC.
v2: replace USES_GUC with guc_is_loaded
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_uc.c | 2 +-
1 file changed, 1 insertion(+), 1
Misc GuC fixes for upcoming 32.0.3
v2: modified reset selftests
Michal Wajdeczko (9):
drm/i915/selftests: Move some reset testcases to separate file
drm/i915/selftests: Split igt_atomic_reset testcase
drm/i915/selftests: Use prepare/finish during atomic reset test
drm/i915/guc: Rename
Test-with: <20190519201634.24816-1-michal.wajdec...@intel.com>
Michal Wajdeczko (3):
drm/i915/uc: Make uc_sanitize part of gt_sanitize
drm/i915/huc: Check HuC firmware status only once
drm/i915/huc: Update HuC status codes
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 2 ++
drivers/g
Without breaking existing usage, slightly update HuC status codes
to provide more info to the clients:
1 if HuC firmware is loaded and verified,
0 if HuC firmware is not enabled,
-ENOPKG if HuC firmware is not loaded,
-ENODEV if HuC is not present on this platform.
Signed-off-by: Michal
During driver load we checked that HuC firmware was verified, and once
verified it stays verified, so there is no need to check that again.
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
Cc: Tony Ye
---
drivers/gpu/drm/i915/intel_huc.c | 17 ++---
drivers/gpu/drm/i915
In gt_sanitize we reset whole GPU (and indirectly uC).
Make sure we don't miss to run our dedicated uC sanitize code.
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 2 ++
drivers/gpu/drm/i915/i915_gem_pm.c| 1 -
2 files changed, 2 insertions
On 5/20/2019 8:16 PM, Michal Wajdeczko wrote:
On Mon, 20 May 2019 12:44:43 +0200, Chris Wilson
wrote:
Quoting Michal Wajdeczko (2019-05-20 11:24:37)
On Mon, 20 May 2019 11:35:26 +0200, Chris Wilson
wrote:
> Quoting Michal Wajdeczko (2019-05-19 22:50:43)
>> If we never at
On Mon, 20 May 2019 12:44:43 +0200, Chris Wilson
wrote:
Quoting Michal Wajdeczko (2019-05-20 11:24:37)
On Mon, 20 May 2019 11:35:26 +0200, Chris Wilson
wrote:
> Quoting Michal Wajdeczko (2019-05-19 22:50:43)
>> If we never attempted to load HuC firmware, or we already wedged
&g
On Mon, 20 May 2019 11:35:26 +0200, Chris Wilson
wrote:
Quoting Michal Wajdeczko (2019-05-19 22:50:43)
If we never attempted to load HuC firmware, or we already wedged
or reset GuC/HuC, then there is no reason to wake up the device
to check one bit in the register that will be for sure
Wilson
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
Cc: Tony Ye
---
drivers/gpu/drm/i915/intel_huc.c | 20
drivers/gpu/drm/i915/intel_huc.h | 5 +
2 files changed, 17 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915
On Fri, 17 May 2019 23:52:37 +0200, Chris Wilson
wrote:
Quoting Michal Wajdeczko (2019-05-17 22:40:28)
If we never attempted to load HuC firmware, or we already wedged
or reset GuC/HuC, then there is no reason to wake up the device
to check one bit in the register that will be for sure
If we never attempted to load HuC firmware, or we already wedged
or reset GuC/HuC, then there is no reason to wake up the device
to check one bit in the register that will be for sure cleared.
Suggested-by: Chris Wilson
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
Cc: Tony Ye
---
drivers
On Fri, 17 May 2019 22:08:56 +0200, Chris Wilson
wrote:
Quoting Michal Wajdeczko (2019-05-17 19:01:06)
On Fri, 17 May 2019 19:14:01 +0200, Chris Wilson
wrote:
> Quoting Michal Wajdeczko (2019-05-17 18:11:07)
>> On Fri, 17 May 2019 18:31:31 +0200, Chris Wilson
>> wrote:
On Fri, 17 May 2019 19:14:01 +0200, Chris Wilson
wrote:
Quoting Michal Wajdeczko (2019-05-17 18:11:07)
On Fri, 17 May 2019 18:31:31 +0200, Chris Wilson
wrote:
> Quoting Michal Wajdeczko (2019-05-17 17:22:25)
>> We may skip reset preparation steps if GuC is already sanitized.
>
On Fri, 17 May 2019 18:31:31 +0200, Chris Wilson
wrote:
Quoting Michal Wajdeczko (2019-05-17 17:22:25)
We may skip reset preparation steps if GuC is already sanitized.
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_uc.c | 3
On Fri, 17 May 2019 18:30:40 +0200, Chris Wilson
wrote:
Quoting Michal Wajdeczko (2019-05-17 17:22:24)
Knowing that GuC will be reset soon, we may stop all communication
immediately without doing graceful cleanup as it is not needed.
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
Cc
On Fri, 17 May 2019 18:27:44 +0200, Chris Wilson
wrote:
Quoting Michal Wajdeczko (2019-05-17 17:22:27)
When we reset engines using ALL_ENGINES mask, we will do
full GPU reset and GuC will be also affected. Let GuC be
prepared for upcoming reset.
Signed-off-by: Michal Wajdeczko
Cc: Chris
We should not attempt to unwind GuC hardware/firmware setup
if we already have sanitized GuC.
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_uc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_uc.c
Misc GuC fixes for upcoming 32.0.3
Michal Wajdeczko (7):
drm/i915/uc: Use GuC firmware status helper
drm/i915/uc: Explicitly sanitize GuC/HuC on failure and finish
drm/i915/uc: Skip GuC HW unwinding if GuC is already dead
drm/i915/uc: Stop talking with GuC when resetting
drm/i915/uc
We already have helper function for checking GuC firmware
load status. Replace existing open-coded checks.
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
---
drivers/gpu/drm/i915/intel_uc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915
Knowing that GuC will be reset soon, we may stop all communication
immediately without doing graceful cleanup as it is not needed.
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_guc_ct.h | 5 +
drivers/gpu/drm/i915/intel_uc.c
Explicitly sanitize GuC/HuC on load failure and when we finish
using them to make sure our fw state tracking is always correct.
While around, use new helper in uc_reset_prepare.
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_uc.c
Knowing that GuC will be reset soon, perform only minimal
cleanup actions (ie. doorbells) without talking with GuC.
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_guc_submission.c | 25 +
drivers/gpu/drm/i915
We may skip reset preparation steps if GuC is already sanitized.
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_uc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915
When we reset engines using ALL_ENGINES mask, we will do
full GPU reset and GuC will be also affected. Let GuC be
prepared for upcoming reset.
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/intel_reset.c | 4
1 file changed, 4
New GuC firmwares use updated sleep status definitions.
The polling on scratch register 14 is also now required only on suspend
and there is no need to provide the shared page.
v2: include changes for polling and shared page
Signed-off-by: Michal Wajdeczko
Signed-off-by: Daniele Ceraolo Spurio
submission bit.
v2: force switch to non-GuC submission mode
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Rodrigo Vivi
Cc: Daniele Ceraolo Spurio
Cc: John Spotswood
Cc: Vinay Belgaumkar
Cc: Tony Ye
Cc: Anusha Srivatsa
Cc: Jeff Mcgee
Cc: Antonio Argen
From: Oscar Mateo
Controlling and handling of the GuC interrupts is Gen specific.
Create virtual functions to avoid redundant runtime Gen checks.
Gen-specific versions of these functions will follow.
v2: move vfuncs to struct guc (Daniele)
Signed-off-by: Oscar Mateo
Signed-off-by: Michal
This patch adds the support to load HuC on ICL.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: Anusha Srivatsa
Cc: Tony Ye
---
drivers/gpu/drm/i915/intel_huc_fw.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915
New GuC firmwares require updated boot parameters.
v2: rebased
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Tvrtko Ursulin
Cc: Daniele Ceraolo Spurio
Cc: John Spotswood
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_guc.c | 38
There are few minor changes in the CSS header related to the version
numbering in new GuC firmwares. Update our definition and start using
common tools for extracting bitfields.
v2: drop deprecated prod_preprod_fw field, replace unions with bit defs
Signed-off-by: Michal Wajdeczko
Cc: Daniele
Current GuC firmwares identify response message in a different way.
v2: update comments for other H2G bits (Daniele)
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Kelvin Gardiner
Cc: John Spotswood
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_guc_ct.c
Define GuC firmware version for Icelake.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Cc: Anusha Srivatsa
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_guc_fw.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion
From: Oscar Mateo
The GuC interrupts now get their own interrupt vector (instead of
sharing a register with the PM interrupts) so handle appropriately.
v2: (Chris)
v3: rebased (Michal)
Bspec: 19820
Signed-off-by: Oscar Mateo
Signed-off-by: Michal Wajdeczko
Cc: Tvrtko Ursulin
Cc: Daniele
Gen11 adds new set of scratch registers that can be used for MMIO
based Host-to-Guc communication. Due to limited number of these
registers it is expected that host will use them only for command
transport buffers (CTB) communication setup if one is available.
Bspec: 21044
Signed-off-by: Michal
With newer GuC firmware it is always ok to ask GuC to update power
domain states. Make it an unconditional initialization step.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: John Spotswood
Reviewed-by: Daniele Ceraolo Spurio
Reviewed-by: John Spotswood
---
drivers/gpu/drm
New GuC firmwares use different action code value for this command.
Signed-off-by: Michal Wajdeczko
Cc: John Spotswood
Cc: Daniele Ceraolo Spurio
Reviewed-by: Daniele Ceraolo Spurio
Reviewed-by: John Spotswood
---
drivers/gpu/drm/i915/intel_guc_fwif.h | 2 +-
1 file changed, 1 insertion
Today our most desired GuC configuration is to only enable HuC
if it is available and we really don't care about GuC submission.
Change platform default GuC mode to match our desire.
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Rodrigo Vivi
Cc: Daniele Ceraolo
Gen11 defines new more flexible Host-to-GuC interrupt register.
Now the host can write any 32-bit payload to trigger an interrupt
and GuC can additionally read this payload from the register.
Current GuC firmware ignores the payload so we just write 0.
Bspec: 21043
Signed-off-by: Michal
Gen11 defines new register for checking HuC authentication status.
Look into the right register and bit.
v2: use reg/mask/value instead of dedicated functions (Daniele)
BSpec: 19686
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Cc: Tony Ye
Cc: Vinay Belgaumkar
Cc
Gen11 GuC firmware expects H2G command messages to be sent over CTB
(command transport buffers).
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: John Spotswood
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
1 file changed, 1
GuC stores some data in there, which might be stale after a reset.
Reinitialize whole ADS in case any part of it was corrupted during
previous GuC run.
v2: s/reinit/init, update functions descriptions (Tomek/Michal)
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: MichaĹ
New GuC firmwares use updated definitions for the Additional Data
Structures (ADS).
v2: add note about Gen9 definition mismatch (Daniele)
rename __intel_engine_context_size (Daniele)
Signed-off-by: Michal Wajdeczko
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Fernando Pacheco
Cc
)
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Daniele Ceraolo Spurio
Cc: Rodrigo Vivi
Cc: Anusha Srivatsa
Cc: Jeff Mcgee
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_guc_fw.c | 75 -
1 file changed, 41 insertions(+), 34 deletions
Cc: Joonas Lahtinen
Cc: Martin Peres
Cc: Chris Wilson
Cc: Rodrigo Vivi
Michal Wajdeczko (17):
drm/i915/guc: Change platform default GuC mode
drm/i915/guc: Don't allow GuC submission
drm/i915/guc: Update GuC firmware versions and names
drm/i915/guc: Update GuC firmware CSS header
On Mon, 15 Apr 2019 23:19:40 +0200, Daniele Ceraolo Spurio
wrote:
On 4/11/19 1:44 AM, Michal Wajdeczko wrote:
Gen11 defines new register for checking HuC authentication status.
Look into the right register and bit.
BSpec: 19686
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc
On Fri, 12 Apr 2019 13:30:47 +0200, Martin Peres
wrote:
On 11/04/2019 11:44, Michal Wajdeczko wrote:
Some CI systems might be configured to run with no longer supported
configuration "enable_guc=3" or "enable_guc=1". Hack that ;)
This is not a hack, this is what we n
Due to the upcoming changes to the GuC ABI interface, we must
disable GuC submission mode until final ABI will be available
on all GuC firmwares.
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Cc: Daniele Ceraolo Spurio
Cc: John Spotswood
Cc: Vinay Belgaumkar
Cc: Tony
Today our most desired GuC configuration is to only enable HuC
if it is available and we really don't care about GuC submission.
Change platform default GuC mode to match our desire.
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Cc: Daniele Ceraolo Spurio
Cc: John
GuC firmware changed its release version numbering schema and now it
also includes patch version. Update our GuC firmware path definitions
to match new pattern:
_guc_...bin
While here, reorder platform checks and start from the latest.
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
New GuC firmwares require updated boot parameters.
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Tvrtko Ursulin
Cc: Daniele Ceraolo Spurio
Cc: John Spotswood
---
drivers/gpu/drm/i915/intel_guc.c | 36 +
drivers/gpu/drm/i915/intel_guc_fwif.h | 39
There are few minor changes in the CSS header related to the version
numbering in new GuC firmwares. Update our definition and start using
common tools for extracting bitfields.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: John Spotswood
Cc: Jeff Mcgee
Gen11 defines new register for checking HuC authentication status.
Look into the right register and bit.
BSpec: 19686
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Cc: Tony Ye
Cc: Vinay Belgaumkar
Cc: John Spotswood
Cc: Anusha Srivatsa
---
drivers/gpu/drm/i915
From: Oscar Mateo
Controlling and handling of the GuC interrupts is Gen specific.
Create virtual functions to avoid redundant runtime Gen checks.
Gen-specific versions of these functions will follow.
Signed-off-by: Oscar Mateo
Signed-off-by: Michal Wajdeczko
Cc: Rodrigo Vivi
Cc: Tvrtko
Definition of the parameters block passed to GuC is about to change.
Slightly refactor code now to make upcoming patch smaller.
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: John Spotswood
Reviewed-by: John Spotswood
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915
This patch adds the support to load HuC on ICL.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: Anusha Srivatsa
Cc: Tony Ye
---
drivers/gpu/drm/i915/intel_huc_fw.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915
New GuC firmwares use updated definitions for the Additional Data
Structures (ADS).
Signed-off-by: Michal Wajdeczko
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Fernando Pacheco
Cc: Joonas Lahtinen
Cc: John Spotswood
Cc: Tomasz Lis
---
drivers/gpu/drm/i915/intel_engine_cs.c | 5
New GuC firmwares use updated sleep status definitions.
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Daniele Ceraolo Spurio
Cc: John Spotswood
---
drivers/gpu/drm/i915/intel_guc_fwif.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915
Define GuC firmware version for Icelake.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Cc: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_guc_fw.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915
From: Oscar Mateo
The GuC interrupts now get their own interrupt vector (instead of
sharing a register with the PM interrupts) so handle appropriately.
v2: (Chris)
v3: rebased (Michal)
Bspec: 19820
Signed-off-by: Oscar Mateo
Signed-off-by: Michal Wajdeczko
Cc: Tvrtko Ursulin
Cc: Daniele
There is no fallback to execlists, but instead of aborting whole
driver load, just mark it as wedged.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Tvrtko Ursulin
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 3 ++-
drivers/gpu/drm/i915/intel_uc.c | 6 ++
2
Gen11 adds new set of scratch registers that can be used for MMIO
based Host-to-Guc communication. Due to limited number of these
registers it is expected that host will use them only for command
transport buffers (CTB) communication setup if one is available.
Bspec: 21044
Signed-off-by: Michal
GuC stores some data in there, which might be stale after a reset.
Reinitialize whole ADS in case any part of it was corrupted during
previous GuC run.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: MichaĹ Winiarski
Cc: Tomasz Lis
---
drivers/gpu/drm/i915/intel_guc.h | 2
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