and use the GuC definitions for the firmware interface.
We also keep the same class id in the ctx descriptor to be able to have
the same values in the driver and firmware logs.
Signed-off-by: Michel Thierry
Signed-off-by: Rodrigo Vivi
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
re we haven't misprogrammed
any WQ or stage descriptor data. This will also help validating
upcoming changes in the db programming flow.
Cc: Michel Thierry
Cc: Michal Wajdeczko
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_guc_fwif.h | 1 +
drivers/gp
On 7/13/2018 1:41 PM, Chris Wilson wrote:
Quoting Chris Wilson (2018-07-13 21:35:28)
Inside intel_engine_is_idle(), we flush the tasklet to ensure that is
being run in a timely fashion (ksoftirqd has taught us to expect the
worst). However, if we are in the middle of reset, the HW may not yet be
if (__tasklet_is_enabled(t))
I would add a comment that this catches any reset in progress as it
isn't as clear as using reset_in_progress (although you explain why in
the commit message).
Up-to you.
Reviewed-by: Michel Thierr
On 7/13/2018 1:18 PM, Chris Wilson wrote:
Knowing the boundary of each subtest can be instrumental in digesting
the voluminous trace output and finding the critical piece of
information.
Signed-off-by: Chris Wilson
Reviewed-by: Michel Thierry
---
drivers/gpu/drm/i915/selftests
On 7/13/2018 1:18 PM, Chris Wilson wrote:
Check that reset_in_progress() is true when we process the reset.
Signed-off-by: Chris Wilson
Reviewed-by: Michel Thierry
---
drivers/gpu/drm/i915/intel_lrc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c
.411064] secondary_startup_64+0xa5/0xb0
The easiest remedy is to remove the defunct code.
Fixes: ff047a87cfac ("drm/i915/icl: Correctly clear lost ctx-switch interrupts
across reset for Gen11")
References: fd8526e50902 ("drm/i915/execlists: Trust the CSB")
If I read &qu
c/huc struct.
v2: don't forget to move wopcm_init - Michele
v3: fetch in init_misc phase - Michal
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Michel Thierry
Reviewed-by: Michel Thierry #2
R-b stands for v3
---
drivers/gpu/drm/i915/i915_gem.c | 7 ---
drivers/gp
On 6/28/2018 7:15 AM, Michal Wajdeczko wrote:
We will add more init steps to misc phase and there is no need
to expose them separately for use in uc_init_misc function.
Signed-off-by: Michal Wajdeczko
Cc: Michel Thierry
---
drivers/gpu/drm/i915/intel_guc.c | 28
al Wajdeczko
Cc: Michał Winiarski
Cc: Michel Thierry
---
drivers/gpu/drm/i915/intel_engine_cs.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 32bf3a408d46..d3264bd6e9dc 100644
--- a/drivers/gpu/drm/i915
don't forget to move wopcm_init - Michele
I'm not Italian ;)
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem.c | 8
drivers/gpu/drm/i915/intel_guc.c | 7 ++-
Cc: Daniele Ceraolo Spurio
Cc: Michel Thierry
---
drivers/gpu/drm/i915/intel_guc.c | 7 ++-
drivers/gpu/drm/i915/intel_huc.c | 8
drivers/gpu/drm/i915/intel_huc.h | 6 ++
drivers/gpu/drm/i915/intel_uc.c | 37 -
4 files changed, 40 inserti
On 06/15/2018 07:10 AM, Michal Wajdeczko wrote:
While debugging we may want to examine params passed to GuC.
Print them all if config I915_DEBUG_GUC is enabled.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Michel Thierry
---
drivers/gpu/drm/i915/intel_guc.c | 5 +
1
fic_ctx_id had this
problem.
v2: Just use the upper 32 bits of lrc_desc (Chris)
v3: If we use the lrc_desc, we must apply the ctx_id_mask too (Lionel)
Fixes: 61d5676b5561 ("drm/i915/perf: fix ctx_id read with GuC & ICL")
Signed-off-by: Michel Thierry
Cc: Lionel Landwerlin
Cc: Chris
The upper 32 bits of the lrc_desc (bits 52-32 to be precise) are the
context hw id in GEN8-10, so use them and have one less thing to
maintain in the unlikely case we change the descriptor sw fields.
v2: If we use the lrc_desc, we must apply the ctx_id_mask too (Lionel)
Signed-off-by: Michel
On 6/4/2018 4:11 PM, Lionel Landwerlin wrote:
On 04/06/18 22:40, Michel Thierry wrote:
The upper 32 bits of the lrc_desc (bits 52-32 to be precise) are the
context hw id in GEN8-10, so use them and have one less thing to
maintain in the unlikely case we change the descriptor sw fields.
Signed
fic_ctx_id had this
problem.
v2: Just use the upper 32 bits of lrc_desc (Chris)
Fixes: 61d5676b5561 ("drm/i915/perf: fix ctx_id read with GuC & ICL")
Signed-off-by: Michel Thierry
Cc: Lionel Landwerlin
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_perf.c | 7 +--
1 fil
The upper 32 bits of the lrc_desc (bits 52-32 to be precise) are the
context hw id in GEN8-10, so use them and have one less thing to
maintain in the unlikely case we change the descriptor sw fields.
Signed-off-by: Michel Thierry
Cc: Lionel Landwerlin
Cc: Chris Wilson
---
drivers/gpu/drm/i915
On 6/4/2018 2:03 PM, Chris Wilson wrote:
Quoting Michel Thierry (2018-06-04 19:17:24)
Use the correct engine class shift value while storing the ctx hw id.
Fixes the copy+paste error from commit 61d5676b5561 ("drm/i915/perf: fix
ctx_id read with GuC & ICL").
Apologies for not sp
On 06/04/2018 11:58 AM, Patchwork wrote:
== Series Details ==
Series: drm/i915/perf: fix gen11 engine class shift
URL : https://patchwork.freedesktop.org/series/44216/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4277 -> Patchwork_9187 =
== Summary - FAILURE ==
Serio
fic_ctx_id had this
problem.
Signed-off-by: Michel Thierry
Cc: Lionel Landwerlin
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_perf.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index a6c8d61add0c..c15c7
d-single-ctx-counters
Acked-by: Chris Wilson
Please ping Michel for an r-b confirmation on using the lrca for the guc
ctx_id.
-Chris
Got the information from Michel initially ;)
Will wait for his Rb on the last version.
Both patches,
Reviewed-by: Michel Thierry
_
'm already writing this...
Reviewed-by: Michel Thierry
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On 6/1/2018 10:08 AM, Lionel Landwerlin wrote:
On 01/06/18 16:18, Chris Wilson wrote:
Quoting Lionel Landwerlin (2018-06-01 10:52:15)
+ /*
+* The LRCA is aligned to a page. As a result the
+* lower 12bits are always at 0 and
stop trying to do any further preemption on this engine.
References:
https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_2235/shard-apl4/igt@gem_exec_sched...@preempt-bsd.html
Signed-off-by: Chris Wilson
Cc: Michal Wajdeczko
Cc: Michel Thierry
Cc: Michałt Winiarski
Reviewed-by: Michel T
r Gen11), but not me.
Reviewed-by: Michel Thierry
Signed-off-by: Lionel Landwerlin
Fixes: 1de401c08fa805 ("drm/i915/perf: enable perf support on ICL")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104252
BSpec: 1237
Testcase: igt/perf/gen8-unprivileged-single-ctx-counters
---
5))
+ return MAX_GUC_CONTEXT_HW_ID;
+
+ return MAX_CONTEXT_HW_ID;
+}
+
What was the reason of moving this out of i915_gem_context.c? I don't
see any other user.
Everything else looks good to me so
Reviewed-by: Michel Thierry
int i915_gem_contexts_set_dynamic_sse
Hi,
On 5/29/2018 12:16 PM, Lionel Landwerlin wrote:
We want to be able to modify other context images from the kernel
context in a following commit. To be able to do this we need to map
the context image into the kernel context's ppgtt.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i9
On 5/16/2018 4:39 PM, Paulo Zanoni wrote:
Em Qui, 2018-05-10 às 14:59 -0700, Oscar Mateo escreveu:
Stop reading some now deprecated interrupt registers in both
debugfs and error state. Instead, read the new equivalents in the
Gen11 interrupt repartitioning scheme.
Note that the equivalent to th
On 5/15/2018 11:17 AM, Jani Nikula wrote:
On Tue, 15 May 2018, Michel Thierry wrote:
On 5/15/2018 10:13 AM, Jani Nikula wrote:
On Mon, 14 May 2018, Michel Thierry wrote:
Factor in clear values wherever required while updating destination
min/max.
Hi Michel, please elaborate what the
On 5/15/2018 10:13 AM, Jani Nikula wrote:
On Mon, 14 May 2018, Michel Thierry wrote:
Factor in clear values wherever required while updating destination
min/max.
Hi Michel, please elaborate what the intention here is.
Hi Jani, isn't the intention of all the workarounds to preven
Factor in clear values wherever required while updating destination
min/max.
References: HSDES#160184
Signed-off-by: Michel Thierry
Cc: mesa-...@lists.freedesktop.org
Cc: Mika Kuoppala
Cc: Oscar Mateo
Reviewed-by: Mika Kuoppala
Signed-off-by: Chris Wilson
Link:
https
On 5/11/2018 5:43 AM, Mika Kuoppala wrote:
Chris Wilson writes:
Quoting Mika Kuoppala (2018-05-11 10:56:49)
Michel Thierry writes:
Factor in clear values wherever required while updating destination
min/max.
References: HSDES#160184
Signed-off-by: Michel Thierry
Cc: mesa
Factor in clear values wherever required while updating destination
min/max.
References: HSDES#160184
Signed-off-by: Michel Thierry
Cc: mesa-...@lists.freedesktop.org
Cc: Mika Kuoppala
Cc: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915
lines") but the issue was
masked in CI by the earlier lockdep spam.
Fixes: a89d1f921c15 ("drm/i915: Split i915_gem_timeline into individual
timelines")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Joonas Lahtinen
Cc: Michel Thierry
Double checked that mock_ring
first
module on boot. This is due to the removal of the distinct global
timeline, and its separate lock class. So instead mark up the expected
nesting. An alternative would be to define a separate lock class for the
engine, but since we only expect to have a single point of nesting, we
can avoid havi
c: Mika Kuoppala
Cc: Joonas Lahtinen
Cc: Tvrtko Ursulin
Cc: Michał Winiarski
Cc: Rafael Antognolli
Cc: Michel Thierry
Cc: Timo Aaltonen
Tested-by: Timo Aaltonen
Acked-by: Michel Thierry
---
drivers/gpu/drm/i915/intel_engine_cs.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/
915/cnl: Use mmio access to context status
buffer")
Suggested-by: Mika Kuoppala
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Joonas Lahtinen
Cc: Tvrtko Ursulin
Cc: Michał Winiarski
Cc: Rafael Antognolli
Cc: Michel Thierry
Cc: Timo Aaltonen
Tested-by: Timo Aaltonen
Acked-by: Michel
breadcrumb; switching
contexts at this point is futile so don't.
Signed-off-by: Chris Wilson
Cc: Michał Winiarski
Cc: Michel Thierry
Cc: Joonas Lahtinen
Reviewed-by: Tvrtko Ursulin
---
Michał and Michel,
please take a look and see if you can think of any objections.
No objections,
On 05/02/2018 02:11 AM, Chris Wilson wrote:
Quoting Michel Thierry (2018-05-01 15:21:53)
On 5/1/2018 12:52 AM, Chris Wilson wrote:
As our early doorbell is split between early allocation and a late setup
after we have a channel to the GuC, it may happen due to a lapse of
programmer judgement
still be there when CONFIG_DRM_I915_DEBUG_GEM=n, right?
(btw, until late last year, there where more users of that function).
Reported-by: Matthias Kaehlcke
Signed-off-by: Chris Wilson
Cc: Daniele Ceraolo Spurio
Cc: Michał Winiarski
Cc: Michal Wajdeczko
Cc: Michel Thierry
---
drivers/gpu/drm
This is identical to v2.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Michał Winiarski
Cc: Michel Thierry
Cc: Tvrtko Ursulin
Reviewed-by: Michel Thierry #v2
---
drivers/gpu/drm/i915/intel_lrc.c | 24 +---
1 file changed, 17 insertions(+), 7 deletions(-)
diff
On 4/27/2018 1:35 PM, Chris Wilson wrote:
Quoting Michel Thierry (2018-04-27 21:27:46)
On 4/27/2018 1:24 PM, Chris Wilson wrote:
Previously, we just reset the ring register in the context image such
that we could skip over the broken batch and emit the closing
breadcrumb. However, on resume
-by-one from including the ppHSWP in with the register
state.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Michał Winiarski
Cc: Michel Thierry
Cc: Tvrtko Ursulin
Reviewed-by: Michel Thierry
Does it need a 'Fixes:' tag or has a bugzilla reference?
---
drivers/gp
: Chris Wilson
Cc: Mika Kuoppala
Cc: Michał Winiarski
Cc: Michel Thierry
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_lrc.c | 24 +---
1 file changed, 17 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
t.
v3: Fix double definition of PCI IDs, update IDs according to bspec
and keep them in the same order and rebase (Lucas)
Cc: Michel Thierry
Signed-off-by: Paulo Zanoni
Signed-off-by: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
---
intel/intel_bufmgr_gem.c | 2 ++
intel/intel_chipset
the style currently in upstream
Suggested-by: Michel Thierry
Signed-off-by: Rodrigo Vivi
Signed-off-by: Michel Thierry
Signed-off-by: Oscar Mateo
Cc: Tvrtko Ursulin
Cc: Daniele Ceraolo Spurio
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_irq.c | 6 ++--
drivers/gpu/drm/i915/intel_drv.h
rious snooping by reset, be it whole-device or per-engine. \o/
The only real issue now is that this makes it crystal clear that we
don't actually do any testing of hangcheck per se in
drv_selftest/live_hangcheck, merely of resets!
Don't tell anyone
Signed-off-by: Chris Wilson
Cc: Michel Th
On 4/6/2018 2:30 PM, Chris Wilson wrote:
Quoting Michel Thierry (2018-04-06 22:23:21)
And I thought we believed in presumption of innocence...
On 4/6/2018 2:00 PM, Chris Wilson wrote:
If we are resetting just one engine, we know it has stalled. So we can
pass the stalled parameter directly to
{
Are the ones in igt_handle_error() still needed?
hangcheck.stalled = true;
hangcheck.seqno = intel_engine_get_seqno(engine);
Because igt_handle_error is sending a real request.
(I think the only ones remaining in the selftest should be in
fake_hangcheck).
Reviewed-by: Miche
If it's true that it's the same as Gen10,
Reviewed-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_debugfs.c | 10 +-
drivers/gpu/drm/i915/intel_pm.c | 10 --
2 files changed, 9 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
I would think of (intel_ringbuffer.h, were other
instances exist) would be also odd since this is not really an engine.
Maybe someone else can think of a better place,
Reviewed-by: Michel Thierry
#define MAX_ENGINE_INSTANCE3
/* PCI config space */
diff --git a/drivers/gp
; GEN11_GT_DW_IRQ(bank))
+ gen11_gt_bank_handler(i915, bank);
+ }
+
+ spin_unlock(&i915->irq_lock);
}
static irqreturn_t gen11_irq_handler(int irq, void *arg)
But it does what is supposed to do s
use correct class / instance limits (Michel)
v4: split engine/other handling
Suggested-by: Daniele Ceraolo Spurio
Cc: Daniele Ceraolo Spurio
Cc: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Michel Thierry
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_irq.c | 102
in
Reported-by: Michel Thierry
Cc: Michel Thierry
Thanks,
Reviewed-by: Michel Thierry
---
lib/igt_gt.h | 12 +++-
tests/perf_pmu.c | 30 ++
2 files changed, 17 insertions(+), 25 deletions(-)
diff --git a/lib/igt_gt.h b/lib/igt_gt.h
ind
On 28/03/18 14:52, Chris Wilson wrote:
Quoting Michel Thierry (2018-03-28 22:47:55)
On 28/03/18 14:18, Chris Wilson wrote:
@@ -2094,7 +2095,7 @@ int intel_gpu_reset(struct drm_i915_private *dev_priv,
unsigned engine_mask)
int retry;
int ret;
- might_sleep
gen (pre-gen8) have been left as they
are only used in full device reset mode.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Michał Winiarski
CC: Michel Thierry
Cc: Jeff McGee
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_uncore.c | 31 ---
1 file
It's not like it will magically appear or disappear ;)
Signed-off-by: Michel Thierry
Cc: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_ddi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index a6672a9
Probably lost while rebasing commit eacd8391f977 ("drm/i915/guc: Keep GuC
interrupts enabled when using GuC").
Not really needed since i915_gem_init_hw is called before uc_resume, but
it brings symmetry to uc_suspend.
Signed-off-by: Michel Thierry
Cc: Michał Winiarski
Reviewed-
From: Michal Wajdeczko
Stolen from...
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index c96360398072..53037b5eff22 100644
---
communication, so some
code reuse is still possible.
v2: filter disabled messages (Daniele)
Signed-off-by: Michal Wajdeczko
Cc: Oscar Mateo
Reviewed-by: Michel Thierry #1
^ still applies for v2, but I would wait for Daniele's blessing
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm
On 3/26/2018 12:48 PM, Michal Wajdeczko wrote:
With this series we will be able to receive more data from the Guc.
New Guc firmwares will be required to actually use that feature.
v4: respin series after 1/2 year break
v5: updated after review comments
Michal Wajdeczko (12):
drm/i915/guc: Ad
er (Michal)
v3: rebased
v4: don't name it 'dispatch' (Michel) and fix checkpatch
add some documentation (Michal)
Signed-off-by: Michal Wajdeczko
Cc: Oscar Mateo
Cc: Michel Thierry
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm
of the scratch register used in MMIO based communication, so some
code reuse is still possible.
Signed-off-by: Michal Wajdeczko
Cc: Oscar Mateo
Reviewed-by: Michel Thierry
---
drivers/gpu/drm/i915/intel_guc.c | 5 +
drivers/gpu/drm/i915/intel_guc.h | 1 +
drivers/gpu/drm/i915
On 3/16/2018 1:28 PM, Daniele Ceraolo Spurio wrote:
On 16/03/18 05:14, Mika Kuoppala wrote:
From: Michel Thierry
The bits used to reset the different engines/domains have changed in
GEN11, this patch maps the reset engine mask bits with the new bits
in the reset control register.
v2: Use
communication, so some
code reuse is still possible.
Spoiler alert, some g2h messages (reset-engine and preemption afaik)
will send us more data, so just passing request->data[1] won't be enough
¯\_(ツ)_/¯
Signed-off-by: Michal Wajdeczko
Cc: Oscar Mateo
---
Reviewed-by: Michel Thierry
er (Michal)
v3: rebased
Signed-off-by: Michal Wajdeczko
Cc: Oscar Mateo
Cc: Michel Thierry
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_guc_ct.c | 72 -
drivers/gpu/drm/i915/intel_guc_ct.h | 4 +++
2 files changed, 75 insertions(+), 1 deletio
: Michel Thierry
Acked-by: Oscar Mateo
---
drivers/gpu/drm/i915/intel_uc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 8dc6a9c..9c20b1b 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm
will WARN if response from GuC does not
match caller expectation.
v2: fix timeout and checkpatch warnings (Michal)
Signed-off-by: Michal Wajdeczko
Cc: Oscar Mateo
Cc: Michel Thierry
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_guc_ct.c | 137
make placeholders
for actual response/request handlers.
v2: misc improvements (Michal)
v3: change response detection (Michal)
invalid status is protocol error (Michal)
v4: rebase
Signed-off-by: Michal Wajdeczko
Cc: Oscar Mateo
Cc: Michel Thierry
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm
or without that,
Reviewed-by: Michel Thierry
+ u32 fence,
+ u32 *status)
{
int err;
@@ -395,7 +402,7 @@ static int ctch_send(struct intel_guc *guc,
intel_guc_notify(guc);
- err = wait_for_response(desc, fence, statu
;handler' makes sense too.
Reviewed-by: Michel Thierry
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 9ce01e5..118db81 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -69,6 +69,7 @@ void intel_guc_in
ted commit message
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Oscar Mateo
Reviewed-by: Michel Thierry #2
---
drivers/gpu/drm/i915/intel_guc.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gp
Wajdeczko
Cc: Oscar Mateo
Cc: Michel Thierry
Cc: Daniele Ceraolo Spurio
Reviewed-by: Michel Thierry #1
r-b still applies to v3.
---
drivers/gpu/drm/i915/intel_guc.c| 6 --
drivers/gpu/drm/i915/intel_guc.h| 18 ++
drivers/gpu/drm/i915/intel_guc_ct.c | 7
bited space after '~' (Michel)
update commit message (Daniele)
v3: rebase
Signed-off-by: Michal Wajdeczko
Cc: Oscar Mateo
Cc: Michel Thierry
Cc: Daniele Ceraolo Spurio
Reviewed-by: Michel Thierry #2
The r-b stands for v3.
---
drivers/gpu/drm/i915/intel_guc.c| 3 +++
7; or 'action'
instead of 'code' but that's personal preference (the archaic fw docs
use 'action code' for this field, is it why you decided to use code?).
Plus it isn't like we want to keep the same names, looking at
intel_guc_fwif.h vs the 'or
nprocessed, hanging the GPU.
Fixes: 767a983ab255 ("drm/i915/execlists: Read the context-status HEAD from the
HWSP")
Signed-off-by: Chris Wilson
Cc: Michel Thierry
Cc: Tvrtko Ursulin
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_lrc.c | 21 -
1 file changed,
eff McGee
Cc: Mika Kuoppala
Cc: Michel Thierry
Reviewed-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_debugfs.c | 4 +-
drivers/gpu/drm/i915/i915_drv.c | 17
drivers/gpu/drm/i915/i915_drv.h | 10 ++---
drivers/gpu/drm/i
t;.
Fixes: 14b730fcb8d9 ("drm/i915/tdr: Prepare error handler to accept mask of hung
engines")
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Michel Thierry
Reviewed-by: Michel Thierry
---
drivers/gpu/drm/i915/intel_hangcheck.c | 4 ++--
1 file changed, 2 insertions(+), 2 dele
Probably lost while rebasing commit eacd8391f977 ("drm/i915/guc: Keep GuC
interrupts enabled when using GuC").
Not really needed since i915_gem_init_hw is called before uc_resume, but
it brings symmetry to uc_suspend.
Signed-off-by: Michel Thierry
Cc: Michał Winiarski
---
drivers/gp
On 3/19/2018 5:44 PM, Chris Wilson wrote:
Quoting Michel Thierry (2018-03-20 00:39:35)
On 3/19/2018 5:18 PM, Chris Wilson wrote:
Not all callers want the GPU error to handled in the same way, so expose
a control parameter. In the first instance, some callers do not want the
heavyweight error
i915_reset/i915_reset_engine so that we include the
reason for the reset in the dev_notice(), superseding the earlier option
to not print that notice.
Signed-off-by: Chris Wilson
Cc: Jeff McGee
Cc: Mika Kuoppala
Cc: Michel Thierry
---
drivers/gpu/drm/i915/i915_debugfs.c | 4
On 16/03/18 14:50, Chris Wilson wrote:
Not all callers want the GPU error to handled in the same way, so expose
a control parameter. In the first instance, some callers do not want the
heavyweight error capture so add a bit to request the state to be
captured and saved.
Signed-off-by: Chris Wils
reset when userspace writes -1 into debugfs/i915_wedged.
I thought that was the desired behaviour...
Reported-by: Michał Winiarski
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Michał Winiarski
Please? It papers over the issue in gem_exec_capture...
-Chris
Reviewed-by: Michel Thierry
)
Suggested-by: Daniele Ceraolo Spurio
Cc: Daniele Ceraolo Spurio
Cc: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Michel Thierry
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_irq.c | 80 +++--
drivers/gpu/drm/i915/i915_reg.h | 4 ++-
2 files changed
On 14/03/18 15:23, Michal Wajdeczko wrote:
On Wed, 14 Mar 2018 21:17:29 +0100, Michel Thierry
wrote:
On 14/03/18 13:04, Michal Wajdeczko wrote:
We try to keep all HuC related code in dedicated file.
There is no need to peek HuC register directly during
handling getparam ioctl.
Signed-off
On 14/03/18 13:04, Michal Wajdeczko wrote:
We try to keep all HuC related code in dedicated file.
There is no need to peek HuC register directly during
handling getparam ioctl.
Signed-off-by: Michal Wajdeczko
Cc: Michel Thierry
Cc: Rodrigo Vivi
Cc: Anusha Srivatsa
---
drivers/gpu/drm/i915
Hi,
On 3/12/2018 7:41 AM, Mika Kuoppala wrote:
Interrupt identity register we already read from hardware
contains engine class and instance fields. Leverage
these fields to find correct engine to handle the interrupt.
add/remove: 0/0 grow/shrink: 0/1 up/down: 0/-160 (-160)
Function
15 in functions that don't
perform register reads.
v2: take i915 from error->i915 (Michal), s/dev_priv/i915,
update commit message
Cc: Michal Wajdeczko
Cc: Chris Wilson
Signed-off-by: Daniele Ceraolo Spurio
Reviewed-by: Michel Thierry
---
drivers/
description
- Remove also GUC_CORE_FAMILY_* definitions (Michel)
Signed-off-by: Piotr Piórkowski
Cc: Sagar Arun Kamble
Cc: Michał Winiarski
Cc: John A Spotswood
Cc: Michal Wajdeczko
Cc: Chris Wilson
Cc: Michel Thierry
---
drivers/gpu/drm/i915/intel_guc.c | 24
On 3/1/2018 10:07 AM, Michel Thierry wrote:
So change timeout_ts and use time_after64 in gen11_gt_engine_intr.
I just read Chris' original comment about this, so ignore the patch,
"The squash should be made, but time_after64 is no more correct since
the native 32b/64b wrapped ari
So change timeout_ts and use time_after64 in gen11_gt_engine_intr.
Fixes: 51951ae7ed00 ("drm/i915/icl: Interrupt handling").
Suggested-by: Tvrtko Ursulin (long time ago)
Signed-off-by: Michel Thierry
Cc: Daniele Ceraolo Spurio
Cc: Chris Wilson
Cc: Oscar Mateo
Cc: Mika Kuoppala
--
On 28/02/18 12:26, Michel Thierry wrote:
On 28/02/18 10:42, Piotr Piórkowski wrote:
In the i915 driver, there is a function, intel_guc_init_params(),
which initializes the GuC parameter block which is passed into
the GuC. There is parameter GUC_CTL_DEVICE_INFO with values
GfxGtType and
On 28/02/18 10:42, Piotr Piórkowski wrote:
In the i915 driver, there is a function, intel_guc_init_params(),
which initializes the GuC parameter block which is passed into
the GuC. There is parameter GUC_CTL_DEVICE_INFO with values
GfxGtType and GfxCoreFamily unused by GuC.
This patch remove GUC
On 28/02/18 09:18, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
In decimal its just a weird big number, while in hex can actually log
which engines were requested to be wedged.
And IGT is not reading the hang reason in this case, so
Reviewed-by: Michel Thierry
Signed-off-by: Tvrtko
On 22/02/18 13:21, Michal Wajdeczko wrote:
On Thu, 22 Feb 2018 21:52:39 +0100, Michel Thierry
wrote:
On 22/02/18 10:45, Michal Wajdeczko wrote:
Right after GPU reset there will be a small window of time during which
some of GuC/HuC fields will still show state before reset. Let's sta
On 22/02/18 10:45, Michal Wajdeczko wrote:
Right after GPU reset there will be a small window of time during which
some of GuC/HuC fields will still show state before reset. Let's start
to fix that by sanitizing firmware status as we will use it shortly.
Suggested-by: Daniele Ceraolo Spurio
Sig
Mostly doc/print messages that were not updated after commit e61e0f51ba79
("drm/i915: Rename drm_i915_gem_request to i915_request").
Signed-off-by: Michel Thierry
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_context.h | 2 +-
drivers/gpu/drm/i915/i915_request.c
Head!=Tail when attempting lite
restore.
Note that after some digging by Michal Winiarski, we found that
RING_HEAD is no longer being updated (due to inhibiting context save
restore) so this patch is already in effect!
Signed-off-by: Chris Wilson
Cc: Michal Winiarski
Cc: Michel Thierr
(index);
+ case VCS3:
+ return GEN11_MFX2_MOCS(index);
default:
MISSING_CASE(engine_id);
return INVALID_MMIO_REG;
--
2.14.1
Reviewed-by: Michel Thierry
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