Describe newly added parameter target_rr_divider in struct
drm_dp_as_sdp.
-v2:
Remove extra line from commit message.(Lucas)
-v3:
Rebase.
Fixes: a20c6d954d75 ("drm/dp: Add refresh rate divider to struct representing
AS SDP")
Cc: Mitul Golani
Cc: Arun R Murthy
Cc: Suraj Kandpal
Describe newly added parameter target_rr_divider in struct
drm_dp_as_sdp.
-v2:
Remove extra line from commit message.(Lucas)
-v3:
Rebase.
Fixes: a20c6d954d75 ("drm/dp: Add refresh rate divider to struct representing
AS SDP")
Cc: Mitul Golani
Cc: Arun R Murthy
Cc: Suraj Kandpal
:
- Rebase.
--v3:
- Correct HSD number in commit message.
--v4:
- Reformat commit message.
- Use intel_de_rmw instead of intel_de_write
--v5:
- Build Fixes.
Signed-off-by: Mitul Golani
Reviewed-by: Nemesa Garg
---
drivers/gpu/drm/i915/display/intel_display_power.c | 8
1 file changed, 8
:
- Rebase.
--v3:
- Correct HSD number in commit message.
--v4:
- Reformat commit message.
- Use intel_de_rmw instead of intel_de_write
Signed-off-by: Mitul Golani
Reviewed-by: Nemesa Garg
---
drivers/gpu/drm/i915/display/intel_display_power.c | 8
1 file changed, 8 insertions(+)
diff --git
Add new member to struct intel_dp to cache support of Adaptive Sync
SDP capabilities and use it whenever required to avoid HW access
to read capability during each atomic commit.
-v2:
- Squash both the patches
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_alpm.c | 2
Cache connector caps during connector detection instead of reading
capabilities each time during atomic commit.
-v2:
- Squash both the patches(Jani).
Mitul Golani (1):
drm/i915/display: Cache adpative sync caps to use it later
drivers/gpu/drm/i915/display/intel_alpm.c | 2 +-
.../drm
Cache as sdp caps during connector detection itself and
remove intel_dp_as_sdp_supported usage as it is being taken
care by already caching caps.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_dp.c | 19 +++
drivers/gpu/drm/i915/display/intel_dp.h | 1 -
2
Cache connector caps during connector detection instead of reading
capabilities each time during atomic commit.
Mitul Golani (2):
drm/i915/display: Avoid reading as sdp caps during each atomic commit
drm/i915/display: Cache Adaptive Sync SDP caps
drivers/gpu/drm/i915/display/intel_alpm.c
Add new member to struct intel_dp to cache support of Adaptive Sync
SDP capabilities and use it whenever required to avoid HW access
to read capability during each atomic commit.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_alpm.c | 2 +-
drivers/gpu/drm/i915
Consider adjusted_pixel_rate to be a u64 to match the return
type of mul_u32_u32() and avoid any compiler dependency for
do_div.
Fixes: 1676ecd303ac ("drm/i915: Compute CMRR and calculate vtotal")
Cc: Mitul Golani
Cc: Ankit Nautiyal
Cc: Suraj Kandpal
Cc: Jani Nikula
Cc: Rodrig
-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_display_power.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index e288a1b21d7e..aef54c1a2ba9 100644
--- a/drivers/gpu/drm
:
- Update workaround number in commit message.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_display_power.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index
The dispcnlunit1_cp_xosc_clk should be de-asserted in display off
and only asserted in display on. But during observation it found
clk remains active in display OFF. As workaround, Display driver
shall execute set-reset sequence at the end of the Initialize
Sequence.
Wa_14020225554
Mitul Golani
Update calculation to avoid overflow.
-v2:
Remove extra line between cc and signed-off.
Fixes: 1676ecd303ac ("drm/i915: Compute CMRR and calculate vtotal")
Cc: Mitul Golani
Cc: Ankit Nautiyal
Cc: Suraj Kandpal
Cc: Jani Nikula
Cc: Stephen Rothwell
Signed-off-by: Mitul Golani
Address following issues regarding CMRR
1. Describe target_rr_divider in struct drm_dp_as_sdp.
2. Use required macro to avoid overflow.
-v2:
- Remove extra line from commit message.
Mitul Golani (2):
drm/dp: Describe target_rr_divider in struct drm_dp_as_sdp
drm/i915/display: Update
Describe newly added parameter target_rr_divider in struct
drm_dp_as_sdp.
-v2:
Remove extra line from commit message.(Lucas)
Fixes: a20c6d954d75 ("drm/dp: Add refresh rate divider to struct representing
AS SDP")
Cc: Mitul Golani
Cc: Arun R Murthy
Cc: Suraj Kandpal
Cc: Ankit Na
Update calculation to avoid overflow.
-v2:
Remove extra line from commit message.(Lucas)
Fixes: 1676ecd303ac ("drm/i915: Compute CMRR and calculate vtotal")
Cc: Mitul Golani
Cc: Ankit Nautiyal
Cc: Suraj Kandpal
Cc: Jani Nikula
Cc: Stephen Rothwell
Signed-off-by: Mitul Golani
Update calculation to avoid overflow.
Fixes: 1676ecd303ac ("drm/i915: Compute CMRR and calculate vtotal")
Cc: Mitul Golani
Cc: Ankit Nautiyal
Cc: Suraj Kandpal
Cc: Jani Nikula
Cc: Stephen Rothwell
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i9
Update calculation to avoid overflow.
Fixes: 1676ecd303ac ("drm/i915: Compute CMRR and calculate vtotal")
Cc: Mitul Golani
Cc: Ankit Nautiyal
Cc: Suraj Kandpal
Cc: Jani Nikula
Cc: Stephen Rothwell
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i9
Address following issues regarding CMRR
1. Describe target_rr_divider in struct drm_dp_as_sdp.
3. Use required macro to avoid overflow.
Mitul Golani (2):
drm/dp: Describe target_rr_divider in struct drm_dp_as_sdp
drm/i915/display: Update calculation to avoid overflow
drivers/gpu/drm/i915
Describe newly added parameter target_rr_divider in struct
drm_dp_as_sdp.
Fixes: a20c6d954d75 ("drm/dp: Add refresh rate divider to struct representing
AS SDP")
Cc: Mitul Golani
Cc: Arun R Murthy
Cc: Suraj Kandpal
Cc: Ankit Nautiyal
Cc: Jani Nikula
Cc: Stephen Rothwell
Compute trans vrr vsync params only when either VRR or CMRR
is enabled.
Fixes: 5922f45329cd ("drm/i915/display: Compute vrr vsync params")
Cc: Mitul Golani
Cc: Ankit Nautiyal
Cc: Suraj Kandpal
Cc: Jani Nikula
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gp
Update calculation to avoid overflow.
Fixes: 1676ecd303ac ("drm/i915: Compute CMRR and calculate vtotal")
Cc: Mitul Golani
Cc: Ankit Nautiyal
Cc: Suraj Kandpal
Cc: Jani Nikula
Cc: Stephen Rothwell
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_vrr.c | 9 ++
Address following issues regarding CMRR
1. Describe target_rr_divider in struct drm_dp_as_sdp.
2. Compute vrr_vsync params when vrr.enable is set.
3. Use required macro to avoid overflow.
Mitul Golani (3):
drm/dp: Describe target_rr_divider in struct drm_dp_as_sdp
drm/i915/display: Send vrr
Describe newly added parameter target_rr_divider in struct
drm_dp_as_sdp.
Fixes: a20c6d954d75 ("drm/dp: Add refresh rate divider to struct representing
AS SDP")
Cc: Mitul Golani
Cc: Arun R Murthy
Cc: Suraj Kandpal
Cc: Ankit Nautiyal
Cc: Jani Nikula
Cc: Stephen Rothwell
Fix vtotal division calculation which works for 32b systems.
Fixes: 1676ecd303ac ("drm/i915: Compute CMRR and calculate vtotal")
Cc: Mitul Golani
Cc: Ankit Nautiyal
Cc: Suraj Kandpal
Cc: Jani Nikula
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_vrr.c | 3 +
Fix few divisions which may not work on 32b builds.
Use DIV_ROUND_UP, with that expecting deviate params
from +/- 1 accuracy in value.
Fixes: 1676ecd303ac ("drm/i915: Compute CMRR and calculate vtotal")
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_vrr.c | 10 +++
Compute trans vrr vsync params only when either VRR or CMRR
is enabled.
Fixes: 5922f45329cd ("drm/i915/display: Compute vrr vsync params")
Cc: Mitul Golani
Cc: Ankit Nautiyal
Cc: Suraj Kandpal
Cc: Jani Nikula
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel
Compute trans vrr vsync params only when either VRR or CMRR
is enabled.
Fixes: 5922f45329cd ("drm/i915/display: Compute vrr vsync params")
Cc: Mitul Golani
Cc: Ankit Nautiyal
Cc: Suraj Kandpal
Cc: Jani Nikula
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel
Add support of pack and unpack for target_rr_divider.
--v2:
- Set Target Refresh Rate Divider bit when related
AS SDP bit is set (Ankit).
--v3:
- target_rr_divider is bools so set accordingly (Ankit).
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display
cmrr.enable.(Ankit)
- Add TODO: for to address target refresh rate precision as future
enhancement.
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_display.c | 1 +
.../drm/i915/display/intel_display_device.h | 1 +
drivers/gpu/drm/i915/display
intel_dp_compute_as_sdp.
--v4:
- Use drm_mode_vrefresh instead of manual calculation (Ankit).
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915
)
- Replace vrr.enable flag to cmrr.enable, mistakenly added. (Ankit)
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_vrr.c | 17 +
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
Add target_rr_divider to structure representing AS SDP.
It is valid only in FAVT mode, sink device ignores the bit in AVT
mode.
--v2:
- Update commit header and send patch to dri-devel.
Signed-off-by: Mitul Golani
Reviewed-by: Arun R Murthy
Acked-by: Maxime Ripard
---
include/drm/display
Move VRR related register definitions to a separate file called
intel_vrr_regs.h.
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_vrr.c | 1 +
drivers/gpu/drm/i915/display/intel_vrr_regs.h | 111 ++
drivers/gpu/drm/i915
.
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/i915_reg.h | 174
1 file changed, 87 insertions(+), 87 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7daf902772e4..3fbf639e6aa0
-v4:
- Removing RFC tag.
--v5:
- CMRR handling in co-existatnce of LRR and DRRS.
--v7:
- Rebase on top of AS SDP merge.
--v8:
- Remove cmrr_enabling/disabling and update commit message. (Ankit)
--v9:
- Revert removed line(Ankit).
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/
name to intel_vrr_regs.h instead of reg.h (Jani)
--v7:
- Remove adding CMRR flag to vrr_ctl register during set_transcoder_timing,
as it is already being done during intel_vrr_enable. (Ankit)
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display
.
-v12:
- Add patch to fix check patch issues for VRR related registers
in i915_reg.h then move them to intel_vrr_regs.h with separate
patch.
-v13:
- Reverted unrelated patches while rebase.
-v14:
- Fix all indentations for VRR related registes in Patch#1
-v15:
- Rebase.
Mitul Golani (9):
drm/i915
intel_dp_compute_as_sdp.
--v4:
- Use drm_mode_vrefresh instead of manual calculation (Ankit).
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915
Add support of pack and unpack for target_rr_divider.
--v2:
- Set Target Refresh Rate Divider bit when related
AS SDP bit is set (Ankit).
--v3:
- target_rr_divider is bools so set accordingly (Ankit).
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display
name to intel_vrr_regs.h instead of reg.h (Jani)
--v7:
- Remove adding CMRR flag to vrr_ctl register during set_transcoder_timing,
as it is already being done during intel_vrr_enable. (Ankit)
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display
cmrr.enable.(Ankit)
- Add TODO: for to address target refresh rate precision as future
enhancement.
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_display.c | 1 +
.../drm/i915/display/intel_display_device.h | 1 +
drivers/gpu/drm/i915/display
)
- Replace vrr.enable flag to cmrr.enable, mistakenly added. (Ankit)
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_vrr.c | 17 +
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
Add target_rr_divider to structure representing AS SDP.
It is valid only in FAVT mode, sink device ignores the bit in AVT
mode.
--v2:
- Update commit header and send patch to dri-devel.
Signed-off-by: Mitul Golani
Reviewed-by: Arun R Murthy
Acked-by: Maxime Ripard
---
include/drm/display
-v4:
- Removing RFC tag.
--v5:
- CMRR handling in co-existatnce of LRR and DRRS.
--v7:
- Rebase on top of AS SDP merge.
--v8:
- Remove cmrr_enabling/disabling and update commit message. (Ankit)
--v9:
- Revert removed line(Ankit).
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/
Move VRR related register definitions to a separate file called
intel_vrr_regs.h.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_vrr.c | 1 +
drivers/gpu/drm/i915/display/intel_vrr_regs.h | 111 ++
drivers/gpu/drm/i915/i915_reg.h | 100
.
-v12:
- Add patch to fix check patch issues for VRR related registers
in i915_reg.h then move them to intel_vrr_regs.h with separate
patch.
-v13:
- Reverted unrelated patches while rebase.
-v14:
- Fix all indentations for VRR related registes in Patch#1
-v15:
- Rebase.
Mitul Golani (9):
gpu/drm
.
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/i915_reg.h | 174
1 file changed, 87 insertions(+), 87 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7daf902772e4..a10591424338
Move VRR related register definitions to a separate file called
intel_vrr_regs.h.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_vrr.c | 1 +
drivers/gpu/drm/i915/display/intel_vrr_regs.h | 114 ++
drivers/gpu/drm/i915/i915_reg.h | 103
.
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/i915_reg.h | 183
1 file changed, 93 insertions(+), 90 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 15ad35178f1a..295689d163c5
)
- Replace vrr.enable flag to cmrr.enable, mistakenly added. (Ankit)
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_vrr.c | 17 +
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
intel_dp_compute_as_sdp.
--v4:
- Use drm_mode_vrefresh instead of manual calculation (Ankit).
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915
-v4:
- Removing RFC tag.
--v5:
- CMRR handling in co-existatnce of LRR and DRRS.
--v7:
- Rebase on top of AS SDP merge.
--v8:
- Remove cmrr_enabling/disabling and update commit message. (Ankit)
--v9:
- Revert removed line(Ankit).
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/
cmrr.enable.(Ankit)
- Add TODO: for to address target refresh rate precision as future
enhancement.
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_display.c | 1 +
.../drm/i915/display/intel_display_device.h | 1 +
drivers/gpu/drm/i915/display
Add target_rr_divider to structure representing AS SDP.
It is valid only in FAVT mode, sink device ignores the bit in AVT
mode.
--v2:
- Update commit header and send patch to dri-devel.
Signed-off-by: Mitul Golani
Reviewed-by: Arun R Murthy
---
include/drm/display/drm_dp_helper.h | 1 +
1
Add support of pack and unpack for target_rr_divider.
--v2:
- Set Target Refresh Rate Divider bit when related
AS SDP bit is set (Ankit).
--v3:
- target_rr_divider is bools so set accordingly (Ankit).
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display
name to intel_vrr_regs.h instead of reg.h (Jani)
--v7:
- Remove adding CMRR flag to vrr_ctl register during set_transcoder_timing,
as it is already being done during intel_vrr_enable. (Ankit)
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display
Move VRR related register definitions to a separate file called
intel_vrr_regs.h.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_vrr.c | 1 +
drivers/gpu/drm/i915/display/intel_vrr_regs.h | 112 ++
drivers/gpu/drm/i915/i915_reg.h | 101
Update the indentation for the VRR register definition and
its bits, and fix checkpatch issues to ensure smooth movement
of registers and bits.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/i915_reg.h | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers
.
-v12:
- Add patch to fix check patch issues for VRR related registers
in i915_reg.h then move them to intel_vrr_regs.h with separate
patch.
-v13:
- Reverted unrelated patches while rebase.
Mitul Golani (9):
gpu/drm/i915: Update indentation for VRR registers and bits
drm/i915: Separate VRR
Add support of pack and unpack for target_rr_divider.
--v2:
- Set Target Refresh Rate Divider bit when related
AS SDP bit is set (Ankit).
--v3:
- target_rr_divider is bools so set accordingly (Ankit).
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display
intel_dp_compute_as_sdp.
--v4:
- Use drm_mode_vrefresh instead of manual calculation (Ankit).
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915
Add target_rr_divider to structure representing AS SDP.
It is valid only in FAVT mode, sink device ignores the bit in AVT
mode.
--v2:
- Update commit header and send patch to dri-devel.
Signed-off-by: Mitul Golani
Reviewed-by: Arun R Murthy
---
include/drm/display/drm_dp_helper.h | 1 +
1
name to intel_vrr_regs.h instead of reg.h (Jani)
--v7:
- Remove adding CMRR flag to vrr_ctl register during set_transcoder_timing,
as it is already being done during intel_vrr_enable. (Ankit)
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display
-v4:
- Removing RFC tag.
--v5:
- CMRR handling in co-existatnce of LRR and DRRS.
--v7:
- Rebase on top of AS SDP merge.
--v8:
- Remove cmrr_enabling/disabling and update commit message. (Ankit)
--v9:
- Revert removed line(Ankit).
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/
Move VRR related register definitions to a separate file called
intel_vrr_regs.h.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_vrr.c | 1 +
drivers/gpu/drm/i915/display/intel_vrr_regs.h | 112 ++
drivers/gpu/drm/i915/i915_reg.h | 101
Update the indentation for the VRR register definition and
its bits, and fix checkpatch issues to ensure smooth movement
of registers and bits.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/i915_reg.h | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers
From: Ville Syrjälä
---
integration-manifest | 28
1 file changed, 28 insertions(+)
create mode 100644 integration-manifest
diff --git a/integration-manifest b/integration-manifest
new file mode 100644
index ..d840964a2208
--- /dev/null
+++
From: Ville Syrjälä
It's probably a good idea to start protecting all macro arguments
to avoid any cargo-cult mistakes when people go looking for examples
of how to define these things.
Signed-off-by: Ville Syrjälä
Link:
.
-v12:
- Add patch to fix check patch issues for VRR related registers
in i915_reg.h then move them to intel_vrr_regs.h with separate
patch.
- Use drm_mode_vrefresh instead of manual refresh rate calculation.
Mitul Golani (7):
gpu/drm/i915: Update indentation for VRR registers and bits
drm/i915
intel_dp_compute_as_sdp.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_dp.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index ac81b172b1ec..be3b9ba943a5
cmrr.enable.(Ankit)
- Add TODO: for to address target refresh rate precision as future
enhancement.
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_display.c | 1 +
.../drm/i915/display/intel_display_device.h | 1 +
drivers/gpu/drm/i915/display
)
- Replace vrr.enable flag to cmrr.enable, mistakenly added. (Ankit)
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_vrr.c | 17 +
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
Add support of pack and unpack for target_rr_divider.
--v2:
- Set Target Refresh Rate Divider bit when related
AS SDP bit is set (Ankit).
--v3:
- target_rr_divider is bools so set accordingly (Ankit).
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display
Add target_rr_divider to structure representing AS SDP.
It is valid only in FAVT mode, sink device ignores the bit in AVT
mode.
--v2:
- Update commit header and send patch to dri-devel.
Signed-off-by: Mitul Golani
Reviewed-by: Arun R Murthy
---
include/drm/display/drm_dp_helper.h | 1 +
1
-v4:
- Removing RFC tag.
--v5:
- CMRR handling in co-existatnce of LRR and DRRS.
--v7:
- Rebase on top of AS SDP merge.
--v8:
- Remove cmrr_enabling/disabling and update commit message. (Ankit)
--v9:
- Revert removed line(Ankit).
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/
Move VRR related register definitions to a separate file called
intel_vrr_regs.h.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_vrr.c | 1 +
drivers/gpu/drm/i915/display/intel_vrr_regs.h | 113 ++
drivers/gpu/drm/i915/i915_reg.h | 100
name to intel_vrr_regs.h instead of reg.h (Jani)
--v7:
- Remove adding CMRR flag to vrr_ctl register during set_transcoder_timing,
as it is already being done during intel_vrr_enable. (Ankit)
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_display.c | 23
.
Mitul Golani (8):
drm/i915: Separate VRR related register definitions
drm/i915: Define and compute Transcoder CMRR registers
drm/i915: Update trans_vrr_ctl flag when cmrr is computed
drm/dp: Add refresh rate divider to struct representing AS SDP
drm/i915/display: Add support for pack
Add support of pack and unpack for target_rr_divider.
--v2:
- Set Target Refresh Rate Divider bit when related
AS SDP bit is set (Ankit).
--v3:
- target_rr_divider is bools so set accordingly (Ankit).
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_dp.c | 4
1 file
Compute vrr vsync params in case of FAVT as well instead of
only to AVT mode of operation.
--v2:
- Remove redundant computation for vrr_vsync_start
and vrr_vsync_end(Ankit).
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_vrr.c | 17 +
1 file changed, 9
Compute params for Adaptive Sync SDP when Fixed Average Vtotal
mode is enabled.
--v2:
Since vrr.enable is set in case of cmrr also, handle accordingly(Ankit).
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_dp.c | 17 +
1 file changed, 13 insertions(+), 4
-v4:
- Removing RFC tag.
--v5:
- CMRR handling in co-existatnce of LRR and DRRS.
--v7:
- Rebase on top of AS SDP merge.
--v8:
- Remove cmrr_enabling/disabling and update commit message. (Ankit)
--v9:
- Revert removed line(Ankit).
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_vr
Add target_rr_divider to structure representing AS SDP.
It is valid only in FAVT mode, sink device ignores the bit in AVT
mode.
--v2:
- Update commit header and send patch to dri-devel.
Signed-off-by: Mitul Golani
Reviewed-by: Arun R Murthy
---
include/drm/display/drm_dp_helper.h | 1 +
1
name to intel_vrr_regs.h instead of reg.h (Jani)
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_display.c | 23 ++-
.../drm/i915/display/intel_display_types.h| 6 +
drivers/gpu/drm/i915/display/intel_vrr.c | 22 ++
drivers/gpu/drm
and cmrr.enable are not mutually exclusive,
handle accordingly (Ankit).
- is_edp is not required inside is_cmrr_frac_required function (Ankit).
- Add video_mode_required flag for future enhancement.
- Correct cmrr_m/cmrr_n calculation.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display
Move VRR related register definitions to a separate file called
intel_vrr_regs.h.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_vrr.c | 1 +
drivers/gpu/drm/i915/display/intel_vrr_regs.h | 117 ++
drivers/gpu/drm/i915/i915_reg.h | 100
accordingly.
- is_edp is not required inside is_cmrr_frac_required function.
- Add video_mode_required flag for future enhancement.
- Correct cmrr_m/cmrr_n calculation.
- target_rr_divider is bools so handle accordingly.
Mitul Golani (8):
drm/i915: Separate VRR related register definitions
drm
-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_display_power.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index a860d88a65da..af2960c7e5b8 100644
--- a/drivers/gpu/drm
The dispcnlunit1_cp_xosc_clk should be de-asserted in display off
and only asserted in display on. But during observation it found
clk remains active in display OFF. As workaround, Display driver
shall execute set-reset sequence at the end of the Initialize
Sequence.
Wa_15013987218
Mitul Golani
Compute vrr vsync params in case of FAVT as well instead of
only to AVT mode of operation.
--v2:
- Remove redundant computation for vrr_vsync_start
and vrr_vsync_end(Ankit).
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_vrr.c | 17 +
1 file changed, 9
Set cmrr.enable flag during intel_vrr_compute_config.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_vrr.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
b/drivers/gpu/drm/i915/display/intel_vrr.c
index 07be70f7c536
Compute params for Adaptive Sync SDP when Fixed Average Vtotal
mode is enabled.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_dp.c | 17 +
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu
Add support of pack and unpack for target_rr_divider.
--v2:
- Set Target Refresh Rate Divider bit when related
AS SDP bit is set (Ankit).
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_dp.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/display
.
- Set cmrr.enable with a separate patch at last.
Mitul Golani (8):
drm/i915: Define and compute Transcoder CMRR registers
drm/i915: Update trans_vrr_ctl flag when cmrr is computed
drm/i915: Compute CMRR and calculate vtotal
Add refresh rate divider to struct representing AS SDP
drm/i915
-v4:
- Removing RFC tag.
--v5:
- CMRR handling in co-existatnce of LRR and DRRS.
--v7:
- Rebase on top of AS SDP merge.
--v8:
- Remove cmrr_enabling/disabling and update commit message. (Ankit)
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_vrr.c | 11 ---
1 file changed
on register offset. [Jani]
--v3:
- Removing RFC tag.
--v4:
- Update place holder for CMRR register definition. (Jani)
--v5:
- Add CMRR register definitions to a separate file intel_vrr_reg.h.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_display.c | 23
scanline precision.
--v6:
- Make CMRR a small subset of FAVT mode.
--v7:
- Update commit message to avoid confusion with Legacy VRR (Ankit).
- Add cmrr.enable in last, so remove from this patch.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_display.c | 1 +
.../drm/i915
Add target_rr_divider to structure representing AS SDP.
It is valid only in FAVT mode, sink device ignores the bit in AVT
mode.
Signed-off-by: Mitul Golani
Reviewed-by: Arun R Murthy
---
include/drm/display/drm_dp_helper.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/drm/display
1 - 100 of 380 matches
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