On 5/29/2015 10:51 PM, Daniel Vetter wrote:
On Fri, May 29, 2015 at 04:07:03PM +0530, Gaurav K Singh wrote:
During enable sequence for MIPI encoder in command mode, enable
MIPI display self-refresh mode bit in Pipe Ctrl reg.
Signed-off-by: Gaurav K Singh
Signed-off-by: Yogesh Mohan Marimuthu
Reviewed-by: Yogesh Mohan Marimuthu
Thank you,
Yogesh
On 3/9/2015 2:29 PM, Purushothaman, Vijay A wrote:
On 3/2/2015 11:37 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
The specs seem to be full of misinformation wrt. the Punit register
0x36. Some versions still show the old
Reviewed-by: Yogesh Mohan Marimuthu
Thank you,
Yogesh
On 3/9/2015 2:28 PM, Purushothaman, Vijay A wrote:
On 3/2/2015 11:37 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
Supposedly CHV can sustain a pixel clock of up to 95% of
cdclk, as opposed to the 90% limit that was used
