On 9/26/2024 2:46 PM, Jani Nikula wrote:
On Wed, 13 Dec 2023, Ankit Nautiyal wrote:
At the moment, while choosing the input bpc for DSC, we take into
account the max_requested_bpc property. This creates a problem, if the
max_requested_bpc is lower than the minimum bpc required by source with
On 10/2/2024 1:19 PM, Colin Ian King wrote:
There is a spelling mistake in a drm_WARN message. Fix it.
Signed-off-by: Colin Ian King
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/g
On 9/30/2024 10:05 PM, Ankit Nautiyal wrote:
This patch series attempts to implement basic support
for Ultrajoiner functionality.
Rev6:
-Upgrade the debugfs functionality to enable the joining of a
specified number of pipes.
-Modify the display helpers reliant on the pipe joiner mechanism
to u
On 10/1/2024 5:32 PM, Jani Nikula wrote:
On Mon, 30 Sep 2024, Ankit Nautiyal wrote:
Add macro to check if platform supports Ultrajoiner.
v2:
-Use check for DISPLAY_VER >= 20, and add bmg as a special case. (Ville)
-Add check for HAS_DSC. (Ville)
Signed-off-by: Ankit Nautiyal
Reviewed-by: V
On 9/30/2024 7:50 PM, Patchwork wrote:
Project List - Patchwork *Patch Details*
*Series:* Ultrajoiner basic functionality series (rev13)
*URL:* https://patchwork.freedesktop.org/series/133800/
*State:*failure
*Details:*
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133800v1
On 9/26/2024 7:13 PM, Ankit Nautiyal wrote:
This patch series introduces enhancements to debugfs for forcing pipe
joiner and prepares for the implementation of the ultrajoiner.
These patches are derived from the original series [1] focused on the
basic functionality of the ultra joiner. The deb
On 9/27/2024 2:08 PM, Ankit Nautiyal wrote:
Add compressed bpp limitations for ultrajoiner.
v2: Fix the case for 1 pipe. (Ankit)
v3: Refactor existing helper separately and add only ultrajoiner
limitation. (Ville)
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c |
On 9/26/2024 12:44 PM, Suraj Kandpal wrote:
Retry the first read and write to downstream at least 10 times
with a 50ms delay if not hdcp2 capable(dock decides to stop advertising
hdcp2 capability for some reason). The reason being that
during suspend resume Dock usually keep the HDCP2 registers
On 9/26/2024 4:49 PM, Ville Syrjälä wrote:
On Thu, Sep 26, 2024 at 12:56:31PM +0530, Ankit Nautiyal wrote:
Pass the current pipe into enabled_joiner_pipes(), and let it figure out
the proper bitmasks for us. Since the enabled_joiner_pipes now gets the
primary and secondary pipe wrt a given pip
On 9/26/2024 4:44 PM, Ville Syrjälä wrote:
On Thu, Sep 26, 2024 at 12:56:25PM +0530, Ankit Nautiyal wrote:
Currently we support joiner only for DP encoder.
Do not create the debugfs for joiner if DP does not support the joiner.
This will also help avoiding cases where config has eDP MSO, with
On 9/18/2024 12:00 PM, Ankit Nautiyal wrote:
Modify the iterators for enabling/disabling during modeset that works for
present and future joiner cases.
This patch series is a spin off from original series for ultrajoiner
basic functionality [1] and discussion on [2].
Few of the preparatory pat
On 9/12/2024 9:06 PM, Jani Nikula wrote:
On Thu, 12 Sep 2024, Jani Nikula wrote:
On Thu, 12 Sep 2024, Ankit Nautiyal wrote:
Add macros to check if platform supports bigjoiner/uncompressed joiner.
Replace the existing DISPLAY_VER checks with these.
Additionally use it before readout for join
On 9/16/2024 3:58 PM, Ankit Nautiyal wrote:
Currently few joiner helpers pass joiner flag to represent if bigjoiner
is used. To scale this for ultrajoiner, enhance these helpers to use num
of pipes instead of joiner flag. This new approach is adaptable to various
joiner configurations with 1 (n
On 9/17/2024 7:01 PM, Ville Syrjälä wrote:
On Tue, Sep 17, 2024 at 01:53:58PM +0530, Ankit Nautiyal wrote:
Joiners have specific enabling and disabling order dependent on primary
and secondary pipes. This becomes more complex with ultrajoiner where we
have ultrajoiner primary/secondary pipes i
On 9/17/2024 11:16 PM, Jani Nikula wrote:
On Tue, 17 Sep 2024, Ankit Nautiyal wrote:
LINK_N register has bits 31:24 for extended link N value used for
HDMI2.1 and for an alternate mode of operation of DP TG DDA
(Bspec:50488).
Add support for these extra bits.
v2: Drop extra link_n_ext membe
On 9/16/2024 8:36 PM, Ville Syrjälä wrote:
On Mon, Sep 16, 2024 at 05:54:12PM +0300, Ville Syrjälä wrote:
On Mon, Sep 16, 2024 at 01:09:42PM +0530, Nautiyal, Ankit K wrote:
On 9/12/2024 4:08 AM, Ville Syrjälä wrote:
On Wed, Sep 11, 2024 at 06:43:46PM +0530, Ankit Nautiyal wrote:
From
On 9/12/2024 4:08 AM, Ville Syrjälä wrote:
On Wed, Sep 11, 2024 at 06:43:46PM +0530, Ankit Nautiyal wrote:
From: Stanislav Lisovskiy
Ultrajoiner case requires special treatment where both reverse and
staight order iteration doesn't work(for instance disabling case requires
order to be: prima
On 9/12/2024 4:28 PM, Ville Syrjälä wrote:
On Thu, Sep 12, 2024 at 03:50:34PM +0530, Nautiyal, Ankit K wrote:
On 9/12/2024 1:47 AM, Ville Syrjälä wrote:
On Wed, Sep 11, 2024 at 06:43:37PM +0530, Ankit Nautiyal wrote:
In preparation of ultrajoiner, use number of joined pipes in the
On 9/12/2024 4:35 AM, Ville Syrjälä wrote:
On Wed, Sep 11, 2024 at 06:43:30PM +0530, Ankit Nautiyal wrote:
This patch series attempts to implement basic support
for Ultrajoiner functionality.
Rev6:
-Upgrade the debugfs functionality to enable the joining of a
specified number of pipes.
-Modif
On 9/12/2024 1:47 AM, Ville Syrjälä wrote:
On Wed, Sep 11, 2024 at 06:43:37PM +0530, Ankit Nautiyal wrote:
In preparation of ultrajoiner, use number of joined pipes in the
intel_dp_joiner_needs_dsc helper, instead of joiner flag.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/displ
On 9/12/2024 1:44 AM, Ville Syrjälä wrote:
On Wed, Sep 11, 2024 at 06:43:36PM +0530, Ankit Nautiyal wrote:
Currently intel_joiner_num_pipes is used to get num of pipes wrt num of
pipes joined. Simplify this by returning 1 when no joiner is used and
update the checks for no joiner case.
Signed
On 9/10/2024 5:16 PM, Ville Syrjälä wrote:
On Tue, Sep 10, 2024 at 11:12:30AM +0530, Nautiyal, Ankit K wrote:
On 9/9/2024 7:10 PM, Ville Syrjälä wrote:
On Mon, Sep 09, 2024 at 11:10:16AM +0530, Nautiyal, Ankit K wrote:
On 9/6/2024 8:24 PM, Ville Syrjälä wrote:
On Fri, Sep 06, 2024 at 05:46
On 9/9/2024 7:10 PM, Ville Syrjälä wrote:
On Mon, Sep 09, 2024 at 11:10:16AM +0530, Nautiyal, Ankit K wrote:
On 9/6/2024 8:24 PM, Ville Syrjälä wrote:
On Fri, Sep 06, 2024 at 05:46:11PM +0300, Ville Syrjälä wrote:
On Fri, Sep 06, 2024 at 06:27:54PM +0530, Ankit Nautiyal wrote:
At the
On 9/6/2024 10:09 PM, Ville Syrjälä wrote:
On Fri, Sep 06, 2024 at 07:30:16PM +0300, Ville Syrjälä wrote:
On Fri, Sep 06, 2024 at 06:28:03PM +0530, Ankit Nautiyal wrote:
From: Stanislav Lisovskiy
Add changes to DSC which are required for Ultrajoiner.
v2:
-Use correct helper for setting bit
On 9/6/2024 9:28 PM, Ville Syrjälä wrote:
On Fri, Sep 06, 2024 at 06:28:01PM +0530, Ankit Nautiyal wrote:
From: Stanislav Lisovskiy
Ultrajoiner mode has some new bits and states to be
read out from the hw. Lets make changes accordingly.
v2: Fix checkpatch warnings. (Ankit)
v3: Add separate
On 9/9/2024 2:01 PM, Nautiyal, Ankit K wrote:
On 9/6/2024 9:09 PM, Ville Syrjälä wrote:
On Fri, Sep 06, 2024 at 06:28:00PM +0530, Ankit Nautiyal wrote:
From: Stanislav Lisovskiy
Adding sanity checks for primary and secondary bigjoiner/uncompressed
bitmasks, should make it easier to spot
On 9/6/2024 9:09 PM, Ville Syrjälä wrote:
On Fri, Sep 06, 2024 at 06:28:00PM +0530, Ankit Nautiyal wrote:
From: Stanislav Lisovskiy
Adding sanity checks for primary and secondary bigjoiner/uncompressed
bitmasks, should make it easier to spot possible issues.
Signed-off-by: Stanislav Lisovsk
On 9/6/2024 8:59 PM, Ville Syrjälä wrote:
On Fri, Sep 06, 2024 at 06:27:59PM +0530, Ankit Nautiyal wrote:
From: Stanislav Lisovskiy
We need to add a new sanity checks and also do
some preparations for adding ultrajoiner hw state readout.
Lets first split reading of the uncompressed joiner an
On 9/6/2024 8:54 PM, Ville Syrjälä wrote:
On Fri, Sep 06, 2024 at 06:27:58PM +0530, Ankit Nautiyal wrote:
From: Stanislav Lisovskiy
In most of the cases we now try to avoid mentioning things like
"bigjoiner" or "ultrajoiner" trying to unify the API and refer
mostly to all this functionality
On 9/6/2024 8:22 PM, Ville Syrjälä wrote:
On Fri, Sep 06, 2024 at 06:27:56PM +0530, Ankit Nautiyal wrote:
In preparation of ultrajoiner, use number of joined pipes in the
intel_mode_valid_max_plane_size helper, instead of joiner flag.
Signed-off-by: Ankit Nautiyal
Reviewed-by: Suraj Kandpal
On 9/6/2024 8:24 PM, Ville Syrjälä wrote:
On Fri, Sep 06, 2024 at 05:46:11PM +0300, Ville Syrjälä wrote:
On Fri, Sep 06, 2024 at 06:27:54PM +0530, Ankit Nautiyal wrote:
At the moment, the debugfs for joiner allows only to force enable/disable
pipe joiner for 2 pipes. Modify it to force join '
Hi Ville,
Thanks for the comments and suggestions. Will remove the extra things
that are not required.
Please my response inline:
On 9/6/2024 8:16 PM, Ville Syrjälä wrote:
On Fri, Sep 06, 2024 at 06:27:54PM +0530, Ankit Nautiyal wrote:
At the moment, the debugfs for joiner allows only to fo
On 9/5/2024 6:52 PM, Jani Nikula wrote:
On Thu, 05 Sep 2024, Ankit Nautiyal wrote:
LINK_N register has bits 31:24 for extended link N value used for
HDMI2.1 and for an alternate mode of operation of DP TG DDA
(Bspec:50488).
Add support for these extra bits.
Please throw away the link_n_ext
On 9/3/2024 6:55 PM, Ville Syrjälä wrote:
On Mon, Sep 02, 2024 at 01:36:33PM +0530, Ankit Nautiyal wrote:
Currently VRR timing generator is used only when VRR is enabled by
userspace. From XELPD+, gradually move away from older timing
generator and use VRR timing generator for fixed refresh ra
On 9/3/2024 6:34 PM, Ville Syrjälä wrote:
On Mon, Sep 02, 2024 at 01:36:32PM +0530, Ankit Nautiyal wrote:
Do not program transcoder registers for VRR for the secondary pipe of
the joiner. Remove check to skip VRR for joiner case.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/displ
On 9/3/2024 6:32 PM, Ville Syrjälä wrote:
On Mon, Sep 02, 2024 at 01:36:31PM +0530, Ankit Nautiyal wrote:
As per Bspec:68925: Push enable must be set if not configuring for a
fixed refresh rate (i.e Vmin == Flipline == Vmax is not true).
Signed-off-by: Ankit Nautiyal
Reviewed-by: Mitul Golan
On 9/3/2024 6:15 PM, Ville Syrjälä wrote:
On Mon, Sep 02, 2024 at 01:36:27PM +0530, Ankit Nautiyal wrote:
Previously, TRANS_VRR_VSYNC was exclusively used for panels with
adaptive-sync SDP support in VRR scenarios. However, to drive fixed refresh
rates using the VRR Timing generator, we now ne
On 9/3/2024 6:21 PM, Ville Syrjälä wrote:
On Mon, Sep 02, 2024 at 01:36:24PM +0530, Ankit Nautiyal wrote:
Add fixed_rr member to struct vrr to represent the case where a
fixed refresh rate with VRR timing generator is required.
v2: Move get_config change where vrr.fixed is actually set. (Mitu
On 8/29/2024 8:17 PM, Jani Nikula wrote:
Use to_intel_display() instead of kdev_to_i915() in the HDCP component
API hooks. Avoid further drive-by changes at this point, and just
convert the display pointer to i915, and leave the struct intel_display
conversion for later.
The NULL error checkin
On 7/8/2024 8:52 PM, Animesh Manna wrote:
Coonector state is not used in lobf compute config, so removed it.
nitpick: s/coonector/connector and s/removed/remove
Add fixes tag.
With above fixed:
Reviewed-by: Ankit Nautiyal
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/displa
On 7/8/2024 8:52 PM, Animesh Manna wrote:
Panel Replay VSC SDP not getting sent when VRR is enabled
and W1 and W2 are 0. So Program Set Context Latency in
TRANS_SET_CONTEXT_LATENCY register to at least a value of 1.
The same is applicable for PSR1/PSR2 as well.
HSD: 14015406119
v1: Initial ve
On 8/30/2024 4:55 PM, Ville Syrjälä wrote:
On Fri, Aug 30, 2024 at 10:39:37AM +0530, Ankit Nautiyal wrote:
Move the function to configure dss_ctl for dual_link dsi to intel_dss
files. While at it, use struct intel_display wherever possible.
v2: Avoid modifying the code while movement. (Jani)
Thanks Ville for the comments.
Please my response inline:
On 8/30/2024 4:49 PM, Ville Syrjälä wrote:
On Fri, Aug 30, 2024 at 10:39:32AM +0530, Ankit Nautiyal wrote:
Cleanup register definitions for DSS CLT reg bits.
DSS_CTL
Will fix this in next version.
Replace the hand rolled (1<
---
On 8/26/2024 6:11 PM, Jani Nikula wrote:
On Mon, 26 Aug 2024, Ankit Nautiyal wrote:
Rename the helper is_pipe_dsc to intel_dsc_is_pipe_dsc to prepare for its
future use across multiple files. This change is a preliminary step towards
making the function non-static, enhancing its accessibility
On 8/26/2024 6:04 PM, Jani Nikula wrote:
On Mon, 26 Aug 2024, Ankit Nautiyal wrote:
Currently, DSS control is configured from various files; this change aims
to consolidate all DSS-related functionalities, such as display stream
splitting, joining, MSO configuration, and joining configuration
On 8/21/2024 7:11 PM, Ville Syrjälä wrote:
On Fri, Aug 16, 2024 at 01:53:20PM +0530, Nautiyal, Ankit K wrote:
On 7/18/2024 1:47 PM, Ankit Nautiyal wrote:
From: Stanislav Lisovskiy
In most of the cases we now try to avoid mentioning things like
"bigjoiner" or "ultrajoiner&q
On 7/18/2024 1:47 PM, Ankit Nautiyal wrote:
From: Stanislav Lisovskiy
In most of the cases we now try to avoid mentioning things like
"bigjoiner" or "ultrajoiner" trying to unify the API and refer
mostly to all this functionality as "joiner".
In majority cases that should be way to go.
Howeve
On 8/9/2024 5:11 PM, Suraj Kandpal wrote:
We are checking cp_irq_count from the wrong hdcp structure which
ends up giving timed out errors. We only increment the cp_irq_count
of the primary connector's hdcp structure but here in case of
multidisplay setup we end up checking the secondary connec
On 8/8/2024 10:24 AM, Nemesa Garg wrote:
In panel fitter/pipe scaler scenario the pch_pfit configuration
currently takes place before accounting for pipe_src width for
joiner. This causes issue when pch_pfit and joiner get enabled
together.
Introduce a new boolean flag need_joiner which is set
On 8/6/2024 7:29 PM, Jani Nikula wrote:
On Tue, 06 Aug 2024, Ankit Nautiyal wrote:
diff --git a/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.h
b/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.h
index 9f60bd9bacbe..288289ec593f 100644
--- a/drivers/gpu/drm/i915/display/intel_snps_hdmi_p
On 8/5/2024 11:55 AM, Nemesa Garg wrote:
Refactor pch_panel_fitting to use local variables for crtc_hdisplay
and crtc_vdisplay. This will help to adjust the hdisplay at one place
when big/ultra joiner is involved. Introduce local variables crtc_hdisplay
and crtc_vdisplay and update all referenc
On 8/5/2024 11:55 AM, Nemesa Garg wrote:
In panel fitter/pipe scaler scenario the pch_pfit configuration
currently takes place before accounting for pipe_src width for
joiner. This causes issue when pch_pfit and joiner get enabled
together.
Introduce a new boolean flag is_required which can be
On 7/30/2024 9:39 AM, Mitul Golani wrote:
AS SDP should be computed when VRR timing generator is also enabled.
Correct the compute condition to compute params of Adaptive sync SDP
when VRR timing genrator is enabled along with sink support indication.
--v2:
Modify if condition (Jani).
Fixes:
On 7/26/2024 3:23 PM, Nemesa Garg wrote:
In panel fitter/pipe scaler scenario the pch_pfit configuration
currently takes place before accounting for pipe_src width for
joiner. This causes issue when pch_pfit and joiner gets
typo: get
enabled together.
Introduce a new boolean flag is_requi
On 7/26/2024 3:23 PM, Nemesa Garg wrote:
Refactor pch_panel_fitting to use local variables for crtc_hdisplay
and crtc_vdisplay. This will help to adjust the hdisplay at one place
when big/ultra joiner is involved. Introduce local variables crtc_hdisplay
and crtc_vdisplay and update all referenc
On 7/26/2024 2:20 PM, Mitul Golani wrote:
AS SDP should be computed when VRR timing generator is also enabled.
Correct the compute condition to compute params of Adaptive sync SDP
when VRR timing genrator is enabled along with sink support indication.
--v2:
Modify if condition (Jani).
Signed-
On 7/23/2024 9:58 AM, Suraj Kandpal wrote:
Clear VSC SDP if intel_dp_set_infoframes is called from post ddi disable
routine i.e with the variable of enable as false. This is to avoid
an infoframes.enable mismatch issue which is caused when pipe is
connected to eDp which has psr then connected t
On 7/5/2024 3:13 PM, Nemesa Garg wrote:
In panel fitter/pipe scaler scenario the pch_pfit configuration
currently takes place before we account for bigjoiner.
So once the calculation for bigjoiner is done, proper values
of width and height can be used for panel fitting.
I think this seems to
On 7/16/2024 9:36 AM, Golani, Mitulkumar Ajitkumar wrote:
-Original Message-
From: Nautiyal, Ankit K
Sent: Tuesday, July 9, 2024 8:57 AM
To: intel-gfx@lists.freedesktop.org
Cc: jani.nik...@linux.intel.com; ville.syrj...@linux.intel.com; Golani,
Mitulkumar Ajitkumar
Subject: [PATCH
On 7/16/2024 9:33 AM, Golani, Mitulkumar Ajitkumar wrote:
-Original Message-
From: Nautiyal, Ankit K
Sent: Tuesday, July 9, 2024 8:57 AM
To: intel-gfx@lists.freedesktop.org
Cc: jani.nik...@linux.intel.com; ville.syrj...@linux.intel.com; Golani,
Mitulkumar Ajitkumar
Subject: [PATCH
On 7/9/2024 12:30 AM, Imre Deak wrote:
Dump the descriptor of the detected LTTPRs in non-transparent mode to
help the debugging related to LTTPRs easier.
v2: Use drm_dp_dump_lttpr_desc() instead of the driver specific
equivalent.
Reviewed-by: Ville Syrjälä # v1
Signed-off-by: Imre Deak
LGTM
Reviewed-by: Ankit Nautiyal
On 7/9/2024 12:30 AM, Imre Deak wrote:
Add a helper to dump the DPCD descriptor for an LTTPR PHY. This is based
on [1] and [2] moving the helper to DRM core as suggested by Ville.
[1] https://lore.kernel.org/all/20240703155937.1674856-5-imre.d...@intel.com
[2]
LGTM.
Reviewed-by: Ankit Nautiyal
On 7/9/2024 12:30 AM, Imre Deak wrote:
Nothing depends on the cached LTTPR mode, however for consistency keep
it up-to-date with the value programmed to the DPCD register.
Reviewed-by: Ville Syrjälä
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/displa
LGTM.
Reviewed-by: Ankit Nautiyal
On 7/9/2024 12:30 AM, Imre Deak wrote:
After detection the cached LTTPR count can be checked to determine if
LTTPRs in non-transparent mode were detected. Reset the cached LTTPR
count if the reported number of LTTPRs is invalid to ensure the above
checks work
LGTM
Reviewed-by: Ankit Nautiyal
On 7/9/2024 12:30 AM, Imre Deak wrote:
Switching to transparent mode leads to a loss of link synchronization,
so prevent doing this on an active link. This happened at least on an
Intel N100 system / DELL UD22 dock, the LTTPR residing either on the
host or the
On 7/9/2024 12:30 AM, Imre Deak wrote:
Regularly retraining a link during an atomic commit happens with the
given pipe/link already disabled and hence intel_dp->link_trained being
false. Ensure this also for retraining a DP SST link via direct calls to
the link training functions (vs. an actual
On 7/10/2024 2:07 PM, Lisovskiy, Stanislav wrote:
On Wed, Jul 03, 2024 at 02:21:48PM +0530, Nautiyal, Ankit K wrote:
On 6/26/2024 1:48 PM, Stanislav Lisovskiy wrote:
Implement required changes for mode validation and compute config,
to support Ultrajoiner.
This also includes required DSC
On 6/26/2024 1:48 PM, Stanislav Lisovskiy wrote:
Implement required changes for mode validation and compute config,
to support Ultrajoiner.
This also includes required DSC changes and checks.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +-
driv
On 6/26/2024 1:48 PM, Stanislav Lisovskiy wrote:
Implement required changes for mode validation and compute config,
to support Ultrajoiner.
This also includes required DSC changes and checks.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +-
driv
, June 26, 2024 8:13 AM
To: Nautiyal, Ankit K ; Runyan, Arthur J
Cc: intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915/dp: Wait more before rearming FIFO underrun
during retrain
On Wed, Jun 26, 2024 at 02:06:24PM +0530, Ankit Nautiyal wrote:
During
On 6/28/2024 12:00 AM, Jani Nikula wrote:
On Thu, 27 Jun 2024, "Nautiyal, Ankit K" wrote:
On 6/26/2024 3:37 PM, Jani Nikula wrote:
On Wed, 26 Jun 2024, Ankit Nautiyal wrote:
Try SNPS_PHY HDMI tables computed using the algorithm, before using
consolidated tables.
Signed-off
On 6/26/2024 3:42 PM, Jani Nikula wrote:
On Wed, 26 Jun 2024, Ankit Nautiyal wrote:
Include the intel_pll_algorithm for xe driver.
Not how this works. Please build every commit before submitting and
you'll see the build is broken at patch 2.
git rebase -i $tip -x make
BR,
Jani.
Apologies
On 6/26/2024 3:40 PM, Jani Nikula wrote:
On Wed, 26 Jun 2024, Ankit Nautiyal wrote:
Add support for computing C10 HDMI PLLS using the HDMI PLL algorithm.
Try C10 HDMI tables computed with the algorithm, before using the
consolidated tables.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/dr
On 6/26/2024 3:37 PM, Jani Nikula wrote:
On Wed, 26 Jun 2024, Ankit Nautiyal wrote:
Try SNPS_PHY HDMI tables computed using the algorithm, before using
consolidated tables.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_snps_phy.c | 20 ---
1 file ch
On 6/26/2024 3:34 PM, Jani Nikula wrote:
On Wed, 26 Jun 2024, Ankit Nautiyal wrote:
Add helper _intel_phy_compute_hdmi_tmds_pll to calculate the necessary
parameters for configuring the HDMI PLL for SNPS MPLLB and C10 PHY.
The pll parameters are computed for desired pixel clock, curve data
a
On 6/12/2024 3:24 PM, Mitul Golani wrote:
Update calculation to avoid overflow.
Fixes: 1676ecd303ac ("drm/i915: Compute CMRR and calculate vtotal")
Cc: Mitul Golani
Cc: Ankit Nautiyal
Cc: Suraj Kandpal
Cc: Jani Nikula
Cc: Stephen Rothwell
Signed-off-by: Mitul Golani
Reviewed-by: Ankit
On 6/12/2024 3:24 PM, Mitul Golani wrote:
Describe newly added parameter target_rr_divider in struct
drm_dp_as_sdp.
Fixes: a20c6d954d75 ("drm/dp: Add refresh rate divider to struct representing AS
SDP")
Cc: Mitul Golani
Cc: Arun R Murthy
Cc: Suraj Kandpal
Cc: Ankit Nautiyal
Cc: Jani Nikul
On 6/11/2024 5:35 PM, Mitul Golani wrote:
Compute trans vrr vsync params only when either VRR or CMRR
is enabled.
Fixes: 5922f45329cd ("drm/i915/display: Compute vrr vsync params")
Cc: Mitul Golani
Cc: Ankit Nautiyal
Cc: Suraj Kandpal
Cc: Jani Nikula
Signed-off-by: Mitul Golani
---
driv
On 6/10/2024 8:18 AM, Mitul Golani wrote:
Move VRR related register definitions to a separate file called
intel_vrr_regs.h.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_vrr.c | 1 +
drivers/gpu/drm/i915/display/intel_vrr_regs.h | 111 ++
driver
Subject: drm/i915 should suffice.
Reviewed-by: Ankit Nautiyal
On 6/10/2024 8:18 AM, Mitul Golani wrote:
Update the indentation for the VRR register definition and
its bits, and fix checkpatch issues to ensure smooth movement
of registers and bits.
--v2:
- Keep XELPD_VRR_CTL_VRR_GUARDBAND(x)
On 6/7/2024 8:59 AM, Nautiyal, Ankit K wrote:
On 6/5/2024 10:31 PM, Mitul Golani wrote:
Update the indentation for the VRR register definition and
its bits, and fix checkpatch issues to ensure smooth movement
of registers and bits.
Signed-off-by: Mitul Golani
LGTM
Reviewed-by: Ankit
On 6/5/2024 10:31 PM, Mitul Golani wrote:
Update the indentation for the VRR register definition and
its bits, and fix checkpatch issues to ensure smooth movement
of registers and bits.
Signed-off-by: Mitul Golani
LGTM
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/i915_reg.h |
On 6/3/2024 11:18 AM, Mitul Golani wrote:
Add register definitions for Transcoder Fixed Average
Vtotal mode/CMRR function, with the necessary bitfields.
Compute these registers when CMRR is enabled, extending
Adaptive refresh rate capabilities.
--v2:
- Use intel_de_read64_2x32 in intel_vrr_get
On 6/3/2024 11:18 AM, Mitul Golani wrote:
Move VRR related register definitions to a separate file called
intel_vrr_regs.h.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_vrr.c | 1 +
drivers/gpu/drm/i915/display/intel_vrr_regs.h | 113 ++
driver
On 6/3/2024 11:19 AM, Mitul Golani wrote:
Compute params for Adaptive Sync SDP when Fixed Average Vtotal
mode is enabled.
--v2:
Since vrr.enable is set in case of cmrr also, handle accordingly(Ankit).
--v3:
- Since vrr.enable is set in case of cmrr also, handle
accordingly(Ankit).
- check cmr
On 5/30/2024 11:34 AM, Mitul Golani wrote:
Add register definitions for Transcoder Fixed Average
Vtotal mode/CMRR function, with the necessary bitfields.
Compute these registers when CMRR is enabled, extending
Adaptive refresh rate capabilities.
--v2:
- Use intel_de_read64_2x32 in intel_vrr_ge
On 5/30/2024 11:34 AM, Mitul Golani wrote:
Compute vrr vsync params in case of FAVT as well instead of
only to AVT mode of operation.
--v2:
- Remove redundant computation for vrr_vsync_start
and vrr_vsync_end(Ankit).
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_vrr.c
On 5/30/2024 11:34 AM, Mitul Golani wrote:
Compute params for Adaptive Sync SDP when Fixed Average Vtotal
mode is enabled.
--v2:
Since vrr.enable is set in case of cmrr also, handle accordingly(Ankit).
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_dp.c | 17 +++
On 5/30/2024 11:34 AM, Mitul Golani wrote:
Add support of pack and unpack for target_rr_divider.
--v2:
- Set Target Refresh Rate Divider bit when related
AS SDP bit is set (Ankit).
--v3:
- target_rr_divider is bools so set accordingly (Ankit).
Signed-off-by: Mitul Golani
LGTM.
Reviewed-by
On 5/30/2024 11:34 AM, Mitul Golani wrote:
Compute Fixed Average Vtotal/CMRR with resepect to
userspace VRR enablement. Also calculate required
parameters in case of CMRR is enabled. During
intel_vrr_compute_config, CMRR is getting enabled
based on userspace has enabled Variable refresh mode
w
On 5/30/2024 11:34 AM, Mitul Golani wrote:
Add/update trans_vrr_ctl flag when crtc_state->cmrr.enable
is set, With this commit setting the stage for subsequent
CMRR enablement.
--v2:
- Check pipe active state in cmrr enabling. [Jani]
- Remove usage of bitwise OR on booleans. [Jani]
- Revert un
On 5/28/2024 3:04 PM, Nautiyal, Ankit K wrote:
On 5/24/2024 3:54 PM, Mitul Golani wrote:
Compute Fixed Average Vtotal/CMRR with resepect to
userspace VRR enablement. Also calculate required
parameters in case of CMRR is enabled. During
intel_vrr_compute_config, CMRR is getting enabled
based
On 5/27/2024 1:56 PM, Animesh Manna wrote:
From: Jouni Högander
eDP1.5 adds some more bits into DP_RECEIVER_ALPM_CAP and
DP_RECEIVER_ALPM_CONFIG registers. Add definitions for these.
Signed-off-by: Jouni Högander
---
include/drm/display/drm_dp.h | 5 -
1 file changed, 4 insertions(+)
On 5/24/2024 3:54 PM, Mitul Golani wrote:
Compute params for Adaptive Sync SDP when Fixed Average Vtotal
mode is enabled.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_dp.c | 17 +
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/drivers/g
On 5/24/2024 3:54 PM, Mitul Golani wrote:
Add support of pack and unpack for target_rr_divider.
--v2:
- Set Target Refresh Rate Divider bit when related
AS SDP bit is set (Ankit).
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_dp.c | 4
1 file changed, 4 insertion
On 5/24/2024 3:54 PM, Mitul Golani wrote:
Add target_rr_divider to structure representing AS SDP.
It is valid only in FAVT mode, sink device ignores the bit in AVT
mode.
Add prefix : drm/dp, also need to send to dri-devel.
Regards,
Ankit
Signed-off-by: Mitul Golani
Reviewed-by: Arun R
On 5/24/2024 3:54 PM, Mitul Golani wrote:
Compute Fixed Average Vtotal/CMRR with resepect to
userspace VRR enablement. Also calculate required
parameters in case of CMRR is enabled. During
intel_vrr_compute_config, CMRR is getting enabled
based on userspace has enabled Variable refresh mode
wi
On 5/24/2024 3:54 PM, Mitul Golani wrote:
Add/update trans_vrr_ctl flag when crtc_state->cmrr.enable
is set, With this commit setting the stage for subsequent
CMRR enablement.
--v2:
- Check pipe active state in cmrr enabling. [Jani]
- Remove usage of bitwise OR on booleans. [Jani]
- Revert unr
On 5/9/2024 1:28 PM, Mitul Golani wrote:
Compute vrr vsync params in case of FAVT as well instead of
only to AVT mode of operation.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_vrr.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/dis
On 5/9/2024 1:28 PM, Mitul Golani wrote:
Add support of pack and unpack for target_rr_divider.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_dp.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gp
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