, it meant the w/a was not actually active. So fix that.
Fixes: 104bcfae57d8 ("drm/i915/arl: Enable Wa_14019159160 for ARL")
Cc: John Harrison
Cc: Vinay Belgaumkar
Cc: Daniele Ceraolo Spurio
Cc: Andi Shyti
Cc: Lucas De Marchi
Cc: Rodrigo Vivi
Cc: Matt Roper
Cc: Jonathan Cavitt
Cc: Nir
On 8/7/2024 12:05 PM, Andi Shyti wrote:
In preparation for the upcoming partial memory mapping feature,
we want to make sure that when looking for a node we consider
also the offset and not just the starting address of the virtual
memory node.
Signed-off-by: Andi Shyti
Reviewed-by: Nirmoy
inning
of the object.
Based on a patch by Chris Wilson.
Signed-off-by: Andi Shyti
Cc: Chris Wilson
Cc: Lionel Landwerlin
Reviewed-by: Nirmoy Das
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 4 +++-
drivers/gpu/drm/i915/i915_mm.c | 12 +++-
drivers/gpu/drm/i
g/drm/i915/kernel/-/issues/11704
Reviewed-by: Nirmoy Das
---
drivers/gpu/drm/i915/intel_memory_region.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_memory_region.c
b/drivers/gpu/drm/i915/intel_memory_region.c
index 172dfa7c3588b..d40
On 7/17/2024 5:25 PM, Dan Carpenter wrote:
On Wed, Jul 17, 2024 at 05:05:55PM +0200, Nirmoy Das wrote:
On 7/12/2024 11:41 PM, Jonathan Cavitt wrote:
Prevent a NULL pointer access in intel_memory_regions_hw_probe.
Fixes: 05da7d9f717b ("drm/i915/gem: Downgrade stolen lmem setup wa
On 7/17/2024 5:30 PM, Cavitt, Jonathan wrote:
-Original Message-
From: Nirmoy Das
Sent: Wednesday, July 17, 2024 8:22 AM
To: Cavitt, Jonathan ;
intel-gfx@lists.freedesktop.org
Cc: Gupta, saurabhg ; dan.carpen...@linaro.org;
chris.p.wil...@linux.intel.com; Andi Shyti
Subject: Re
On 7/17/2024 5:11 PM, Cavitt, Jonathan wrote:
-Original Message-
From: Nirmoy Das
Sent: Wednesday, July 17, 2024 8:06 AM
To: Cavitt, Jonathan ;
intel-gfx@lists.freedesktop.org
Cc: Gupta, saurabhg ; dan.carpen...@linaro.org;
chris.p.wil...@linux.intel.com; Andi Shyti
Subject: Re
_ERR_OR_NULL(mem) instead of IS_ERR().
Regards,
Nirmoy
+ if (mem) { /* Skip on non-fatal errors */
+ mem->id = i;
+ i915->mm.regions[i] = mem;
+ }
}
for (i = 0; i < ARRAY_SIZE(i915->mm.regions); i++) {
Hi Andi,
On 6/27/2024 12:04 PM, Andi Shyti wrote:
Hi Nirmoy,
On Wed, Jun 26, 2024 at 04:33:18PM +0200, Nirmoy Das wrote:
We report object allocation failures to userspace with ENOMEM
so add __GFP_NOWARN to remove superfluous oom warnings.
I think this should be the default behavior.
Yes
Hi Rodrigo,
On 6/26/2024 5:50 PM, Rodrigo Vivi wrote:
On Wed, Jun 26, 2024 at 05:36:43PM +0200, Nirmoy Das wrote:
Hi Rodrigo,
On 6/26/2024 5:24 PM, Rodrigo Vivi wrote
Hi Rodrigo,
On 6/26/2024 5:24 PM, Rodrigo Vivi wrote:
On Wed, Jun 26, 2024 at 04:33:18PM +0200, Nirmoy Das wrote:
We report object allocation failures to userspace with ENOMEM
so add __GFP_NOWARN to remove superfluous oom warnings.
Closes:https://gitlab.freedesktop.org/drm/i915/kernel
We report object allocation failures to userspace with ENOMEM
so add __GFP_NOWARN to remove superfluous oom warnings.
Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4936
Cc: Andi Shyti
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/i915_scatterlist.c | 8
1 file
On 6/11/2024 3:58 PM, Tvrtko Ursulin wrote:
On 10/06/2024 10:24, Nirmoy Das wrote:
Hi Andi,
On 6/7/2024 4:51 PM, Andi Shyti wrote:
The forcewake count and domains listing is multi process critical
and the uncore provides a spinlock for such cases.
Lock the forcewake evaluation section in
, below seems to be correct one.
Fixes: 9dd4b065446a ("drm/i915/gt: Move pm debug files into a gt aware
debugfs")
Cc: # v5.6+
Reviewed-by: Nirmoy Das
Regards,
Nirmoy
---
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 4
1 file changed, 4 insertions(+)
diff --git a/d
On 5/24/2024 1:58 AM, Andi Shyti wrote:
Following the guidelines it takes 3 seconds to perform an FLR
reset. Let's give it a bit more slack because this time can
change depending on the platform and on the firmware
Signed-off-by: Andi Shyti
Reviewed-by: Nirmoy Das
---
Hi,
In this s
Hi Andi,
On 5/21/2024 12:56 PM, Andi Shyti wrote:
Hi Nirmoy,
On Fri, May 17, 2024 at 10:13:37PM +0200, Nirmoy Das wrote:
Hi Andi,
On 5/17/2024 9:34 PM, Andi Shyti wrote:
Hi Nirmoy,
On Fri, May 17, 2024 at 04:00:02PM +0200, Nirmoy Das wrote:
On 5/17/2024 1:25 PM, Andi
Hi Andi,
On 5/17/2024 9:34 PM, Andi Shyti wrote:
Hi Nirmoy,
On Fri, May 17, 2024 at 04:00:02PM +0200, Nirmoy Das wrote:
On 5/17/2024 1:25 PM, Andi Shyti wrote:
If we timeout while waiting for an FLR reset, there is nothing we
can do and i915 doesn't have any control on it. In any cas
he GPU
is usable without a cold reboot.
This is a serious issue and should be report as an error. I think we
need to create a HW ticket to understand
why is FLR reset fails.
Regards,
Nirmoy
and the function returns void.
We don't need to be alarmed, therefore, print the timeout
On 5/17/2024 1:53 PM, Jani Nikula wrote:
On Fri, 17 May 2024, Nirmoy Das wrote:
Hi Jani,
On 5/17/2024 9:39 AM, Jani Nikula wrote:
On Thu, 16 May 2024, Nirmoy Das wrote:
The previous commit 'commit 8d4ba9fc1c6c ("drm/i915/selftests: Pick
"previous commit" is a fairly
Hi Jani,
On 5/17/2024 9:39 AM, Jani Nikula wrote:
On Thu, 16 May 2024, Nirmoy Das wrote:
The previous commit 'commit 8d4ba9fc1c6c ("drm/i915/selftests: Pick
"previous commit" is a fairly vague reference once this gets
committed. It's not going to be "pre
ofik
Cc: Jonathan Cavitt
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
index 65a931ea
Simplify child iteration using for_each_child macro
instead of using manual for loop. There is no functional
change.
Cc: John Harrison
Cc: Tvrtko Ursulin
Signed-off-by: Nirmoy Das
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 64 ++-
1 file changed, 33 insertions(+), 31
: 32eb6bcfdda9 ("drm/i915: Make request allocation caches global")
Also need Cc: # v5.2+
With those:
Reviewed-by: Nirmoy Das
Nirmoy
Signed-off-by: Jiasheng Jiang
---
drivers/gpu/drm/i915/i915_scheduler.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
dif
On 5/7/2024 7:10 PM, Rodrigo Vivi wrote:
On Tue, May 07, 2024 at 10:54:11AM +0200, Janusz Krzysztofik wrote:
On Tuesday, 7 May 2024 09:30:15 GMT+2 Nirmoy Das wrote:
Hi Janusz,
Just realized we need Fixes tag for this.
Fixes: 1f33dc0c1189 ("drm/i915: Remove extra multi-gt pm-refer
Hi Janusz,
Just realized we need Fixes tag for this.
Fixes: 1f33dc0c1189 ("drm/i915: Remove extra multi-gt pm-references")
Regards,
Nirmoy
On 5/6/2024 8:02 PM, Janusz Krzysztofik wrote:
This reverts commit 1f33dc0c1189efb9ae19c6fc22b64dd3e26261fb.
There was a patch supposed
est.
Restoring the extra GT0 PM wakeref removed from i915_gem_do_execbuffer()
processing path seems to fix this issue.
Closes:https://gitlab.freedesktop.org/drm/intel/-/issues/10608
Signed-off-by: Janusz Krzysztofik
Cc: Rodrigo Vivi
Cc: Nirmoy Das
Reviewed-by: Nirmoy Das
---
drivers/gpu/d
veness is limited to MTL topology.
perhaps the safer path for this case indeed. something that could be really
limited to a single platform would be better.
I agree with Rodrigo here. it would be safe revert the mentioned patch
now and think about more robust solution
later on as the issue is
are no more engines awake,
disarm the breadcrumb and go to sleep.
Fixes: 9d5612ca165a ("drm/i915/gt: Defer enabling the breadcrumb interrupt to after
submission")
Closes: https://gitlab.freedesktop.org/drm/intel/issues/10026
Signed-off-by: Chris Wilson
Cc: Andrzej Hajda
Cc: # v
Managing Directors: Christin Eisenschmid, Sharon Heck, Tiffany Doon Silva
Chairperson of the Supervisory Board: Nicole Lau
Registered Office: Munich
Commercial Register: Amtsgericht Muenchen HRB 186928
From: Andi Shyti
Sent: Wednesday, April 24, 2024 7:06 PM
To: Nir
Hi Andi,
On 4/23/2024 11:32 AM, Andi Shyti wrote:
Hi Nirmoy,
On Mon, Apr 22, 2024 at 10:19:51PM +0200, Nirmoy Das wrote:
Currently intel_gt_reset() kills the GuC and then resets requested
engines. This is problematic because there is a dedicated CSB FIFO
which only GuC can access and if that
i
Do we have a IGT for partial FB mmap test ? Would be nice to have one
but this patch looks good to me.
Reviewed-by: Nirmoy Das
Regards,
Nirmoy
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
i915->engine_uabi_class_count[uabi_class]++;
Shouldn't this be i915->engine_uabi_class_count[uabi_class] =
class_instance[uabi_class]; ?
What I see is that this patch mainly adding this class_instance array
and rest looks the same.
May be it make sense to add ot
should be killed only after resetting
the requested engines and before calling intel_gt_init_hw().
v2: Improve commit message(John)
Cc: John Harrison
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/intel_reset.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff
-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
.../drm/i915/gt/intel_execlists_submission.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt.c| 2 +-
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 2 +-
drivers/gpu/drm/i915/gt/intel_reset.c | 35
Hi John,
On 4/19/2024 1:38 AM, John Harrison wrote:
On 4/18/2024 10:10, Nirmoy Das wrote:
Currently intel_gt_reset() happens as follows:
reset_prepare() ---> Sends GDRST to GuC, GuC is in GS_MIA_IN_RESET
do_reset()
intel_gt_reset_all_engines()
*_engine_reset_prepare() -->RES
Hi John,
On 4/19/2024 1:27 AM, John Harrison wrote:
On 4/18/2024 10:10, Nirmoy Das wrote:
intel_engine_reset() not only reset a engine but also
tries to recover it so give it a proper name without
any functional changes.
Not seeing what the difference is. If this was a super low level
Hi John.
On 4/19/2024 1:27 AM, John Harrison wrote:
On 4/18/2024 10:10, Nirmoy Das wrote:
__intel_gt_reset() is really for resetting engines though
the name might suggest something else. So add two helper functions
to remove confusions with no functional changes.
Technically you only added one
_IN_RESET with FW loaded.
Fix the issue by sanitizing the GuC only after resetting requested
engines and before intel_gt_init_hw().
Note intel_uc_reset_finish() and intel_uc_reset() are nop when
guc submission is disabled.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/intel_res
intel_engine_reset() not only reset a engine but also
tries to recover it so give it a proper name without
any functional changes.
Signed-off-by: Nirmoy Das
---
.../drm/i915/gem/selftests/i915_gem_context.c | 2 +-
.../drm/i915/gt/intel_execlists_submission.c | 2 +-
drivers/gpu/drm/i915/gt
__intel_gt_reset() is really for resetting engines though
the name might suggest something else. So add two helper functions
to remove confusions with no functional changes.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
.../drm/i915/gt
Hi John,
On 4/17/2024 2:37 AM, John Harrison wrote:
On 4/15/2024 09:44, Nirmoy Das wrote:
Currently intel_gt_reset() happens as follows:
reset_prepare() ---> Sends GDRST to GuC, GuC is in GS_MIA_IN_RESET
do_reset()
__intel_gt_reset()
*_engine_reset_prepare() -->RESET_CTL e
set(ptr_b, 0, SZ_2M);
Do we need this extra memset() ? Otherwise
Reviewed-by: Nirmoy Das
+ munmap(ptr_b, SZ_2M);
+ }
+
+ gem_close(i915, handle);
+}
+
static int mmap_gtt_version(int i915)
{
int gtt_version = -1;
@@ -931,6 +1010,11 @@ igt_main
rbage if the surface is L3:XD dirty.
Testcase: igt@xe-pat@display-vs-wb-transient
Has the IGT patch for this been sent yet?
Yes, the test seems to be available
https://gitlab.freedesktop.org/drm/igt-gpu-tools/-/blob/master/tests/intel/xe_pat.c#L728
Regards,
Nirmoy
If not, we s
nit_hw() --> GuC FW loading happens, GuC comes out of
GS_MIA_IN_RESET.
Fix the above flow so that GuC reset happens after all the
engines reset is done.
Cc: John Harrison
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/intel_reset.c | 9 --
drivers/gpu/drm/i915/gt/uc/intel_
beginning
of the object.
I quickly tried
https://gitlab.freedesktop.org/llandwerlin/igt-gpu-tools/-/tree/wip/gem_mmap_offset-partial-unmap?ref_type=heads
that didn't work for GTT.
Please make sure a proper IGT test is available for this as this looks
very risky change.
Regards,
Ni
Hi Bala,
On 4/3/2024 1:22 PM, Balasubramani Vivekanandan wrote:
From: Nirmoy Das
Display surfaces can be tagged as transient by mapping it using one of
the various L3:XD PAT index modes on Xe2. The expectation is that KMD
needs to request transient data flush at the start of flip sequence to
ay-vs-wb-transient
Signed-off-by: Matthew Auld
Signed-off-by: Balasubramani Vivekanandan
Acked-by: Nirmoy Das
---
drivers/gpu/drm/i915/display/intel_display.c | 3 +++
.../gpu/drm/i915/display/intel_frontbuffer.c | 2 ++
drivers/gpu/drm/i915/display/intel_tdf.h
On 4/3/2024 1:22 PM, Balasubramani Vivekanandan wrote:
From: Matthew Auld
Needed in an upcoming patch, where we want GT level print, but only
which to trigger once to avoid flooding dmesg.
Signed-off-by: Matthew Auld
Signed-off-by: Balasubramani Vivekanandan
Reviewed-by: Nirmoy Das
There is new fixup patch(PR#630) which modifies this patch. Could you
please bring that in as well.
Regards,
Nirmoy
On 4/3/2024 12:51 PM, Balasubramani Vivekanandan wrote:
From: Nirmoy Das
Display surfaces can be tagged as transient by mapping it using one of
the various L3:XD PAT index
d circular locking issue on busyness
flush")
Signed-off-by: John Harrison
Cc: Zhanjun Dong
Cc: John Harrison
Cc: Andi Shyti
Cc: Daniel Vetter
Cc: Daniel Vetter
Cc: Rodrigo Vivi
Cc: Nirmoy Das
Cc: Tvrtko Ursulin
Cc: Umesh Nerlige Ramappa
Cc: Andrzej Hajda
Cc: Matt Roper
Cc: Jona
ded. Limit it to DG2 onwards.
I would use "Limit it to platforms that need WAs" as those WA are only
needed till 12.71, otherwise
Reviewed-by: Nirmoy Das
Fixes: 9bb66c179f50 ("drm/i915: Reserve some kernel space per vm")
Signed-off-by: Andi Shyti
Cc: Andrzej Hajda
Hi Andi,
On 3/26/2024 12:12 PM, Andi Shyti wrote:
Hi Nirmoy,
...
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index a2195e28b625..57a2dda2c3cc 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem
t, area->vm_end - area->vm_start,
- obj->mm.pages->sgl, iomap);
+ obj->mm.pages->sgl, 0, iomap);
Why don't we need partial mmap for CPU but only for GTT ?
Sounds like this also need to be cover by a IGT tests. Don't we need
the
total amount of the VM space. Add it back when the user requests
the GTT size through ioctl (I915_CONTEXT_PARAM_GTT_SIZE).
Fixes: 9bb66c179f50 ("drm/i915: Reserve some kernel space per vm")
Signed-off-by: Andi Shyti
Cc: Andrzej Hajda
Cc: Chris Wilson
Cc: Lionel Landwerlin
Cc: Micha
p;
I915_BO_FLAG_STRUCT_PAGE" which is very i915 specific.
So I think this will not work and will cause regression in existing
program which are trying to do the same with valid BO. Unfortunately I
don't have any idea how to better detect that at this moment.
Regards,
Nirmoy
+
which is
adjusted(reduced by a page).
This patch might cause silent error as it is not removing WABB which is
using the reserved page to add dummy blt and if userspace is using that
page then it will be overwritten.
Regards,
Nirmoy
, we should be able to continue working without issues.
On 3/12/2024 3:28 PM, Andi Shyti wrote:
Hi Nirmoy,
On Tue, Mar 12, 2024 at 12:18:15PM +0100, Nirmoy Das wrote:
Caching mode is HW dependent so pick a correct one using
intel_gt_coherent_map_type().
Cc: Andi Shyti
Cc: Janusz Krzysztofik
Cc: Jonathan Cavitt
Closes: https
Caching mode is HW dependent so pick a correct one using
intel_gt_coherent_map_type().
Cc: Andi Shyti
Cc: Janusz Krzysztofik
Cc: Jonathan Cavitt
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/10249
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
fix (Rodrigo).
Signed-off-by: Janusz Krzysztofik
Cc: Nirmoy Das
Cc: Rodrigo Vivi
Reviewed-by: Nirmoy Das
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 18 --
1 file changed, 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/
rcular locking dependency,
take care of acquiring the wakeref before VM mutex when both are needed.
v7: Add inline comments with justifications for:
- using untracked variants of intel_gt_pm_get/put() (Nirmoy),
- using async variant of _put(),
- not getting the wakeref in case of a g
On 3/5/2024 3:35 PM, Janusz Krzysztofik wrote:
This reverts commit 7a2280e8dcd2f1f436db9631287c0b21cf6a92b0, obsoleted
by "drm/i915/vma: Fix UAF on destroy against retire race".
Signed-off-by: Janusz Krzysztofik
Cc: Nirmoy Das
Reviewed-by: Nirmoy Das
---
drivers/gpu/drm/i915/
ma_pin_ww() (Rodrigo).
v4: Refresh on top of commit 5e4e06e4087e ("drm/i915: Track gt pm
wakerefs") (Andi),
- for more easy backporting, split out removal of former insufficient
workarounds and move them to separate patches (Nirmoy).
- clean up commit message and description a
Hi Andi,
On 2/29/2024 4:28 PM, Andi Shyti wrote:
Hi Nirmoy,
On Thu, Feb 29, 2024 at 02:29:18PM +0100, Nirmoy Das wrote:
Add missing doc for struct drm_i915_reset_stats.
Cc: Andi Shyti
Signed-off-by: Nirmoy Das
Reviewed-by: Andi Shyti
Thanks, merged to din.
Nirmoy
Thanks,
Andi
Add missing doc for struct drm_i915_reset_stats.
Cc: Andi Shyti
Signed-off-by: Nirmoy Das
---
include/uapi/drm/i915_drm.h | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 2ee338860b7e
On 2/28/2024 2:24 PM, Tvrtko Ursulin wrote:
On 27/02/2024 09:26, Nirmoy Das wrote:
Hi Tvrtko,
On 2/27/2024 10:04 AM, Tvrtko Ursulin wrote:
On 21/02/2024 11:52, Nirmoy Das wrote:
Merged it to drm-intel-gt-next with s/check/Check
Shouldn't this have had:
Fixes: ed29c2691188 (&quo
Hi Tvrtko,
On 2/27/2024 10:04 AM, Tvrtko Ursulin wrote:
On 21/02/2024 11:52, Nirmoy Das wrote:
Merged it to drm-intel-gt-next with s/check/Check
Shouldn't this have had:
Fixes: ed29c2691188 ("drm/i915: Fix userptr so we do not have to worry
about obj->mm.lock, v7.&qu
Merged it to drm-intel-gt-next with s/check/Check
On 2/19/2024 1:50 PM, Nirmoy Das wrote:
Error in mmu_interval_notifier_insert() can leave a NULL
notifier.mm pointer. Catch that and return early.
Cc: Andi Shyti
Cc: Shawn Lee
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/gem
Hi Rodrigo,
On 2/19/2024 9:12 PM, Rodrigo Vivi wrote:
On Mon, Feb 19, 2024 at 01:50:47PM +0100, Nirmoy Das wrote:
Error in mmu_interval_notifier_insert() can leave a NULL
notifier.mm pointer. Catch that and return early.
Cc: Andi Shyti
Cc: Shawn Lee
Signed-off-by: Nirmoy Das
---
drivers/gpu
Error in mmu_interval_notifier_insert() can leave a NULL
notifier.mm pointer. Catch that and return early.
Cc: Andi Shyti
Cc: Shawn Lee
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem
Hi Janusz,
There seems to be a regression in CI related to this:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129026v2/bat-dg1-7/igt@gem_lmem_swapping@random-engi...@lmem0.html#dmesg-warnings1053
Please have a look.
Regards,
Nirmoy
On 1/24/2024 6:13 PM, Janusz Krzysztofik wrote
On 1/19/2024 11:47 AM, Nirmoy Das wrote:
On 1/19/2024 12:12 AM, Ville Syrjälä wrote:
On Wed, Jan 17, 2024 at 06:46:24PM +0100, Nirmoy Das wrote:
On 1/17/2024 3:13 PM, Michał Winiarski wrote:
On Tue, Jan 16, 2024 at 09:56:25AM +0200, Ville Syrjala wrote:
From: Ville Syrjälä
Now that the
On 1/19/2024 12:12 AM, Ville Syrjälä wrote:
On Wed, Jan 17, 2024 at 06:46:24PM +0100, Nirmoy Das wrote:
On 1/17/2024 3:13 PM, Michał Winiarski wrote:
On Tue, Jan 16, 2024 at 09:56:25AM +0200, Ville Syrjala wrote:
From: Ville Syrjälä
Now that the GGTT PTE updates go straight to GSMBASE
ell)?
v2: Keep using MI_UPDATE_GTT on VM guests
Cc: Paz Zcharya
Cc: Nirmoy Das
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/gt/intel_gtt.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c
b/drivers/gpu/drm/i915/gt/in
: Paz Zcharya
Reviewed-by: Andrzej Hajda
Signed-off-by: Ville Syrjälä
Acked-by: Nirmoy Das
---
drivers/gpu/drm/i915/display/intel_plane_initial.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c
b/drivers/gpu/drm/i915/di
On 1/16/2024 8:56 AM, Ville Syrjala wrote:
From: Ville Syrjälä
0x108100 and 0x1080c0 have been around since snb. Rename the
defines appropriately.
Cc: Paz Zcharya
Reviewed-by: Andrzej Hajda
Signed-off-by: Ville Syrjälä
Acked-by: Nirmoy Das
---
drivers/gpu/drm/i915/gem
tting a working
display now depends on a lot more extra components working correctly
TODO: MI_UPDATE_GTT might be interesting as an optimization
though, so perhaps someone should look into always using it
(assuming the GPU is alive and well)?
v2: Keep using MI_UPDATE_GTT on VM guests
Cc: Paz Zcharya
for the initial setup. Once
command submission is up we should switch to MI_UPDATE_GTT
which at least shouldn't hang the whole machine.
v2: Don't use direct GSM/DSM access on guests
Add w/a number
Cc: Paz Zcharya
Cc: Nirmoy Das
Cc: Joonas Lahtinen
Reviewed-by: Andrzej Hajda
Reviewed
rjälä
Reviewed-by: Nirmoy Das
---
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 4
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 3 ---
2 files changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index d2440c7
harya
Reviewed-by: Andrzej Hajda
Signed-off-by: Ville Syrjälä
Acked-by: Nirmoy Das
---
drivers/gpu/drm/i915/display/intel_fbdev_fb.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_region.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 17 +
dri
: Nirmoy Das
---
drivers/gpu/drm/i915/intel_memory_region.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_memory_region.c
b/drivers/gpu/drm/i915/intel_memory_region.c
index b2708f8cac2a..52d998e5c21a 100644
--- a/drivers/gpu/drm/i915
On 1/12/2024 4:12 PM, Ville Syrjälä wrote:
On Wed, Jan 10, 2024 at 11:49:47AM +0100, Nirmoy Das wrote:
Hi Ville,
Apologies, but I lost track of this series after I returned from sick leave.
On 12/15/2023 11:59 AM, Ville Syrjala wrote:
From: Ville Syrjälä
On MTL accessing stolen memory via
On 1/10/2024 11:49 AM, Nirmoy Das wrote:
Hi Ville,
Apologies, but I lost track of this series after I returned from sick
leave.
Please ignore the uncontextual "but" in the previous response. I need to
disable auto correct options.
Regards,
Nirmoy
On 12/15/2023 11:59
d w/a numbers and whatnot
Cc: Paz Zcharya
Cc: Nirmoy Das
Cc: Radhakrishna Sripada
Cc: Joonas Lahtinen
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 11 ++-
drivers/gpu/drm/i915/gt/intel_ggtt.c | 13 -
2 files changed, 22 insertions(
On 12/6/2023 9:46 PM, Andi Shyti wrote:
Get the guc reference from the ce using the ce_to_guc() helper.
Just a leftover from previous cleanups.
Signed-off-by: Andi Shyti
Reviewed-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
1 file changed, 1 insertion
On 12/6/2023 9:46 PM, Andi Shyti wrote:
Get the guc reference from the gt using the gt_to_guc() helper.
Signed-off-by: Andi Shyti
Reviewed-by: Nirmoy Das
---
drivers/gpu/drm/i915/i915_debugfs_params.c | 2 +-
drivers/gpu/drm/i915/selftests/intel_scheduler_helpers.c | 4
On 12/6/2023 9:46 PM, Andi Shyti wrote:
Get the guc reference from the gt using the gt_to_guc() helper.
Signed-off-by: Andi Shyti
Reviewed-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c | 4 +--
drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c | 3 +-
drivers/gpu/drm
/ directory.
Signed-off-by: Andi Shyti
Reviewed-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_ggtt.c | 9 +++--
drivers/gpu/drm/i915/gt/intel_gt.h| 5 +
drivers/gpu/drm/i915/gt/intel_gt_irq.c| 6
Hi John,
On 12/5/2023 8:50 PM, John Harrison wrote:
On 12/5/2023 02:39, Nirmoy Das wrote:
Hi John,
On 12/5/2023 10:10 AM, John Harrison wrote:
On 12/5/2023 00:52, Nirmoy Das wrote:
gen8_engine_reset_prepare() can fail when HW fails to set
RESET_CTL_READY_TO_RESET bit. In some cases this is
Hi Tvrtko,
On 12/5/2023 11:05 AM, Tvrtko Ursulin wrote:
On 05/12/2023 08:50, Nirmoy Das wrote:
Hi Tvrtko,
On 12/5/2023 9:34 AM, Tvrtko Ursulin wrote:
On 01/12/2023 15:44, Nirmoy Das wrote:
gen8_engine_reset_prepare() can fail when HW fails to set
RESET_CTL_READY_TO_RESET bit. In some
Hi John,
On 12/5/2023 10:10 AM, John Harrison wrote:
On 12/5/2023 00:52, Nirmoy Das wrote:
gen8_engine_reset_prepare() can fail when HW fails to set
RESET_CTL_READY_TO_RESET bit. In some cases this is not fatal
error as driver will retry.
Convert the log to a trace log for debugging without
commit message(Tvrtko)
Cc: Tvrtko Ursulin
Cc: John Harrison
Cc: Andi Shyti
Cc: Andrzej Hajda
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5591
Signed-off-by: Nirmoy Das
Reviewed-by: Andi Shyti
Reviewed-by: Andrzej Hajda
---
drivers/gpu/drm/i915/gt/intel_reset.c | 8
1
Hi Tvrtko,
On 12/5/2023 9:34 AM, Tvrtko Ursulin wrote:
On 01/12/2023 15:44, Nirmoy Das wrote:
gen8_engine_reset_prepare() can fail when HW fails to set
RESET_CTL_READY_TO_RESET bit. In some cases this is not fatal
error as driver will retry.
Let the caller of gen8_engine_reset_prepare
Harrison
Cc: Andi Shyti
Cc: Andrzej Hajda
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5591
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/intel_reset.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
b/drivers
On 11/15/2023 1:10 PM, Andrzej Hajda wrote:
Trace requires new-line at the end of message (in opposition to printk),
otherwise trace dump becomes messy.
Signed-off-by: Andrzej Hajda
Reviewed-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 2 +-
1 file changed, 1 insertion
://gitlab.freedesktop.org/drm/intel/-/issues/8489
Fixes: bec68cc9ea42d8 ("drm/i915: Prepare for multiple GTs")
Signed-off-by: Andrzej Hajda
Reviewed-by: Nirmoy Das
---
- Link to v1:
https://lore.kernel.org/r/20231114-dont_clean_gt_on_error_path-v1-1-37f2fa827...@intel.com
---
drive
On 11/6/2023 1:45 PM, Jani Nikula wrote:
On Wed, 25 Oct 2023, Nirmoy Das wrote:
Handle platforms with multiple GTs by iterate over all GTs.
Add a Fixes commit so this gets propagated for MTL support.
Fixes: 213c43676beb ("drm/i915/mtl: Remove the 'force_probe' requirement f
On 10/31/2023 3:18 PM, Jani Nikula wrote:
On Tue, 31 Oct 2023, Nirmoy Das wrote:
On 10/31/2023 1:45 PM, Jani Nikula wrote:
+void i915_gpu_error_debugfs_register(struct drm_i915_private *i915)
+{
+ struct drm_minor *minor = i915->drm.primary;
+
+ debugfs_create_f
Reviewed-by: Nirmoy Das
---
drivers/gpu/drm/i915/i915_gpu_error.c | 75 -
drivers/gpu/drm/i915/i915_gpu_error.h | 17 +++---
drivers/gpu/drm/i915/i915_sysfs.c | 79 +--
3 files changed, 86 insertions(+), 85 deletions(-)
diff --git a
ps = {
+ .owner = THIS_MODULE,
+ .open = i915_error_state_open,
+ .read = gpu_state_read,
+ .write = i915_error_state_write,
+ .llseek = default_llseek,
+ .release = gpu_state_release,
+};
+
+void i915_gpu_error_debugfs_register(struct dr
On 10/31/2023 1:45 PM, Jani Nikula wrote:
Not needed outside of i915_gpu_error.c.
Signed-off-by: Jani Nikula
Reviewed-by: Nirmoy Das
---
drivers/gpu/drm/i915/i915_gpu_error.c | 8
drivers/gpu/drm/i915/i915_gpu_error.h | 5 -
2 files changed, 4 insertions(+), 9 deletions
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