t's a different story).
Are we sure we prefer to do this instead?
Signed-off-by: Chris Wilson
Cc: Oscar Mateo
Cc: Mika Kuoppala
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_debugfs.c | 25 ++
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gp
On 5/29/2018 7:59 AM, Michal Wajdeczko wrote:
Hi,
On Fri, 25 May 2018 23:59:35 +0200, Oscar Mateo
wrote:
GuC interface has been redesigned (or cleaned up, rather) starting
with Gen11, as a stepping stone towards a new branching strategy
that helps maintain backwards compatibility with
Prevents an error in the GAM unit. Also known as WaGamTlbPendError
References: HSDES#1406463099
References: HSDES#1406465643
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++--
drivers/gpu/drm/i915/intel_workarounds.c | 7 +++
2 files changed, 10 insertions
Enables blend optimization for floating point RTs
v2: Rebased on top of the WA refactoring
v3: Added References (Mika)
References: HSDES#1406393558
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_workarounds.c | 3
Apparently HW did not whitelist this register properly.
Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.
References: HSDES#1305642430
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915
Redirects the state cache to the CS Command buffer section for
performance reasons.
v2: Rebased
v3: Rebased on top of the WA refactoring
v3: Added References (Mika)
References: HSDES#1604325460
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 1
WA refactoring
v4: Rebased on top of whitelist reg refactoring (Michel)
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_workarounds.c | 4
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915
Disable blend embellishment in RCC.
Also, some other registers style fixed in passing.
v2: Rebased on top of the WA refactoring
v3: Added References (Mika)
v4:
- Fixed in B0
- Mentioned style fixes in commit message
References: HSDES#2006665173
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
of the WA refactoring
v4: Rebased on top of whitelist reg refactoring (Michel)
v5: Added References (Mika)
References: HSDES#1804860039
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gp
on top of the WA whitelist reg refactoring (Michel)
v5: Added References (Mika)
References: HSDES#1405764967
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/intel_workarounds.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
The remaining WA patches that haven't been merged to date, plus
two new ones (WaEnablePreemptionGranularityControlByUMD &
Wa_1406463099).
Oscar Mateo (11):
drm/i915/icl: WaDisableImprovedTdlClkGating
drm/i915/icl: WaEnableStateCacheRedirectToCS
drm/i915/icl: Wa_2006665173
drm
of the WA refactoring
v4: Rebased on top of the whitelist reg refactoring (Michel)
v5: Added References (Mika)
References: HSDES#1804860157
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gp
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1fb86bd..42835d79 100644
--- a
Added References (Mika)
v7: Fixed in B0
References: HSDES#2006611047
Signed-off-by: Oscar Mateo
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++--
drivers/gpu/drm/i915/intel_workarounds.c | 7 +++
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/driv
for the KMD and one
for clients of the GuC (which, in our case, happens to be the KMD
as well). SLPC interface files will come at a later date.
Could we get eyes on the new interface header files, to make sure the
GuC team is moving in the right direction?
Signed-off-by: Oscar Mateo
Cc: Joonas
:
- Renamed sanitize_mcr to calculate_s_ss_select. (Oscar)
- calculate s/ss selector instead of whole mcr. (Oscar)
v9:
- Updated function name (Oscar)
- Remove redundant variables (Oscar)
v10:
- Separate pre-GEN10 and GEN11 mask. (Oscar)
Cc: Oscar Mateo
Cc: Michel Thierry
Cc: Joonas Lahtinen
Cc
more local variables for clearer
logic (Ursulin)
Cc: Oscar Mateo
Cc: Michel Thierry
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Mika Kuoppala
Cc: Tvrtko Ursulin
Signed-off-by: Yunwei Zhang
Reviewed-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 4
drivers/gpu/drm
On 5/18/2018 3:40 PM, Yunwei Zhang wrote:
WaProgramMgsrForCorrectSliceSpecificMmioReads applies for Icelake as
well.
References: HSD#1405586840, BSID#0575
v2:
- GEN11 mask is different from its predecessors. (Oscar)
- Better separate GEN10 and GEN11. (Oscar)
Cc: Oscar Mateo
Cc: Michel
On 5/17/2018 3:59 PM, Paulo Zanoni wrote:
Em Qui, 2018-05-17 às 10:04 -0700, Oscar Mateo Lozano escreveu:
On 5/17/2018 9:55 AM, Michel Thierry wrote:
On 5/16/2018 4:39 PM, Paulo Zanoni wrote:
Em Qui, 2018-05-10 às 14:59 -0700, Oscar Mateo escreveu:
Stop reading some now deprecated
:
- Renamed sanitize_mcr to calculate_s_ss_select. (Oscar)
- calculate s/ss selector instead of whole mcr. (Oscar)
Cc: Oscar Mateo
Cc: Michel Thierry
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Mika Kuoppala
Cc: Tvrtko Ursulin
Signed-off-by: Yunwei Zhang
---
drivers/gpu/drm/i915/i915_drv.h
On 5/18/2018 11:13 AM, Yunwei Zhang wrote:
WaProgramMgsrForCorrectSliceSpecificMmioReads applies for Icelake as
well.
References: HSD#1405586840, BSID#0575
Cc: Oscar Mateo
Cc: Michel Thierry
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Mika Kuoppala
Cc: Tvrtko Ursulin
Signed-off-by: Yunwei
On 5/17/2018 9:55 AM, Michel Thierry wrote:
On 5/16/2018 4:39 PM, Paulo Zanoni wrote:
Em Qui, 2018-05-10 às 14:59 -0700, Oscar Mateo escreveu:
Stop reading some now deprecated interrupt registers in both
debugfs and error state. Instead, read the new equivalents in the
Gen11 interrupt
On 05/16/2018 04:05 AM, Mika Kuoppala wrote:
Oscar Mateo writes:
Revert to the legacy implementation.
v2: GEN7_ROW_CHICKEN2 is masked
v3:
- Rebased
- Renamed to Wa_2006611047
- A0 and B0 only
v4:
- Add spaces around '<<' (and fix the surrounding code as well)
of PM ISR & IIR
Suggested-by: Paulo Zanoni
Signed-off-by: Oscar Mateo
Cc: Tvrtko Ursulin
Cc: Daniele Ceraolo Spurio
Cc: Sagar Arun Kamble
Cc: Vinay Belgaumkar
---
drivers/gpu/drm/i915/i915_debugfs.c | 34 --
drivers/gpu/drm/i915/i915
opted for leaving
them out. See gen11_service_one_iir() for more info.
v2: else if !!! (Paulo)
v3: another else if (Vinay)
v4:
- Rebased
- Renamed patch
- Improved the ordering of GENs
- Improved the printing of per-GEN info
Suggested-by: Paulo Zanoni
Signed-off-by: Oscar Mateo
Cc: Tvrtk
On 05/04/2018 03:26 PM, John Spotswood wrote:
On Wed, 2018-05-02 at 12:03 -0700, Oscar Mateo wrote:
The register to check for correct HuC authentication by the GuC
has changed in Icelake. Look into the right register & bit.
v2: rebased.
v3: rebased.
v4: Fix I915_PARAM_HUC_STATUS as
Added References (Mika)
v7: Fixed in B0
References: HSDES#2006611047
Signed-off-by: Oscar Mateo
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++--
drivers/gpu/drm/i915/intel_workarounds.c | 7 +++
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/driv
#1405766107
Signed-off-by: Oscar Mateo
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_reg.h | 4
drivers/gpu/drm/i915/intel_workarounds.c | 7 +++
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index
on top of the WA whitelist reg refactoring (Michel)
v5: Added References (Mika)
References: HSDES#1405764967
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/intel_workarounds.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
WA refactoring
v4: Rebased on top of whitelist reg refactoring (Michel)
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_workarounds.c | 4
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915
)
- Do not apply together with another WA for the same
register (not worth the hassle)
v6:
- Rebased
- C, not lisp (Chris)
References: HSDES#1604223664
Signed-off-by: Oscar Mateo
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_reg.h | 6 ++
drivers/gpu/drm/i915
reference to WA that got merged with this
References: HSDES#1406681710
References: HSDES#1406680159
References: HSDES#2201832410
Signed-off-by: Oscar Mateo
Cc: Mika Kuoppala
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_workarounds.c | 5 +
1 file changed, 5 insertions(+)
diff
Disable MSC clock gating to prevent data corruption.
BSpec: 19257
v2: Rebased on top of the WA refactoring
v3: Added References (Mika)
v4:
- Rebased
- C, not lisp (Chris)
- A0 only (Mika)
References: HSDES#1405779004
Signed-off-by: Oscar Mateo
Reviewed-by: Mika Kuoppala
---
drivers/gpu
icl_init_clock_gating, since it's not a WA (Rodrigo)
v5: C, not lisp (Chris)
Signed-off-by: Oscar Mateo
Cc: Praveen Paneri
Cc: Mika Kuoppala
Reviewed-by: Sagar Arun Kamble
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_pm.c | 9 -
2
Revert to the legacy implementation to avoid a system hang.
v2: Correct the address for GAMW_ECO_DEV_RW_IA_REG
v3: Renamed to Wa_220166154
v4: Rebased on top of the WA refactoring
v5: Added References (Mika)
v6:
- Rebased
- C, not lisp (Chris)
References: HSDES#220166154
Signed-off-by: Oscar
Disable blend embellishment in RCC.
Also, some other registers style fixed in passing.
v2: Rebased on top of the WA refactoring
v3: Added References (Mika)
v4:
- Fixed in B0
- Mentioned style fixes in commit message
References: HSDES#2006665173
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
Disable CGPSF unit clock gating to prevent an issue.
v2: Rebased on top of the WA refactoring
v3: Added References (Mika)
v4:
- Rebased
- C, not lisp (Chris)
- Remove unintentional whitespaces (Mika)
- Fixed in C0 (Mika)
References: HSDES#1406838659
Signed-off-by: Oscar Mateo
Reviewed
of the WA refactoring
v4: Rebased on top of the whitelist reg refactoring (Michel)
v5: Added References (Mika)
References: HSDES#1804860157
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gp
Enables blend optimization for floating point RTs
v2: Rebased on top of the WA refactoring
v3: Added References (Mika)
References: HSDES#1406393558
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_workarounds.c | 3
Avoids an undefined LLC behavior.
BSpec: 9613
v2: Renamed to Wa_1405733216
v3: Spaces around '<<' and fix surrounding code
v4: Rebased on top of the WA refactoring
v5: Added References (Mika)
v6:
- Rebased
- C, not lisp (Chris)
References: HSDES#1405733216
Signed-off
Signed-off-by: Oscar Mateo
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_reg.h | 5 +
drivers/gpu/drm/i915/intel_workarounds.c | 5 +
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 81f1a8c..7fe505c
: Oscar Mateo
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_reg.h | 4 +++-
drivers/gpu/drm/i915/intel_workarounds.c | 5 +
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 950ec8e..7cb2ddc
also related
References: HSDES#1405476379
References: HSDES#2006612137
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 5 +
drivers/gpu/drm/i915/intel_workarounds.c | 7 +++
2 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915
List of GT workarounds for Icelake that we have been carrying in internal.
Applied lots of review comments from Mika and stamped rv-b's from him and
Rodrigo.
Oscar Mateo (22):
drm/i915/icl: Introduce initial Icelake Workarounds
drm/i915/icl: Enable Sampler DFR
drm/i91
Redirects the state cache to the CS Command buffer section for
performance reasons.
v2: Rebased
v3: Rebased on top of the WA refactoring
v3: Added References (Mika)
References: HSDES#1604325460
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 1
of the WA refactoring
v4: Rebased on top of whitelist reg refactoring (Michel)
v5: Added References (Mika)
References: HSDES#1804860039
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gp
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e41076f..c3e464c 100644
--- a
icelake_init_clock_gating()
from Paulo Zanoni
- Squashed with this patch:
drm/i915/icl: WaForceEnableNonCoherent
from Oscar Mateo
- WaPushConstantDereferenceHoldDisable is now Wa_1604370585 and
applies to B0 as well.
- WaPipeControlBefore3DStateSamplePattern WABB was being
The default GAPZ arbitrer priority value at power-on has been found
to be incorrect.
v2: Now renamed to Wa_1405543622
v3: Rebased on top of the WA refactoring
v4: Added HSDES reference number (Mika)
v5:
- Rebased
- C, not lisp (Chris)
References: HSDES#1405543622
Signed-off-by: Oscar Mateo
On 5/2/2018 1:40 PM, Chris Wilson wrote:
Quoting Oscar Mateo (2018-05-02 21:33:59)
List of GT workarounds for Icelake that we have been carrying in internal.
(Is (checkpatch
(((going to complain)
(that this isn't))
(lisp?
-Chris
Maybe. Or maybe checkpatch has
of the WA refactoring
v4: Rebased on top of the whitelist reg refactoring (Michel)
v5: Added References (Mika)
References: HSDES#1804860157
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gp
WA refactoring
v4: Rebased on top of whitelist reg refactoring (Michel)
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_workarounds.c | 4
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915
The default GAPZ arbitrer priority value at power-on has been found
to be incorrect.
v2: Now renamed to Wa_1405543622
v3: Rebased on top of the WA refactoring
v4: Added HSDES reference number (Mika)
References: HSDES#1405543622
Signed-off-by: Oscar Mateo
Reviewed-by: Mika Kuoppala
---
drivers
Enables blend optimization for floating point RTs
v2: Rebased on top of the WA refactoring
v3: Added References (Mika)
References: HSDES#1406393558
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_workarounds.c | 3
This workarounds an issue with insufficient storage for the
CL2 and SF units.
v2: Renamed to Wa_1405766107
v3: Wrapped the commit message
v4: Rebased on top of the WA refactoring
v5: Added References (Mika)
References: HSDES#1405766107
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers
Avoids a hang during soft reset.
v2: Rebased on top of the WA refactoring
v3: Added References (Mika)
References: HSDES#1405476379
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 5 +
drivers/gpu/drm/i915/intel_workarounds.c | 8
2
Avoids an undefined LLC behavior.
BSpec: 9613
v2: Renamed to Wa_1405733216
v3: Spaces around '<<' and fix surrounding code
v4: Rebased on top of the WA refactoring
v5: Added References (Mika)
References: HSDES#1405733216
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
driv
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a9866df..d36cf61 100644
--- a
Redirects the state cache to the CS Command buffer section for
performance reasons.
v2: Rebased
v3: Rebased on top of the WA refactoring
v3: Added References (Mika)
References: HSDES#1604325460
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 1
of the WA refactoring
v4: Rebased on top of whitelist reg refactoring (Michel)
v5: Added References (Mika)
References: HSDES#1804860039
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gp
on top of the WA whitelist reg refactoring (Michel)
v5: Added References (Mika)
References: HSDES#1405764967
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/intel_workarounds.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
Disable I2M Write for performance reasons.
v2: Rebased on top of the WA refactoring
v3: Added References (Mika)
References: HSDES#1604302699
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 4 +++-
drivers/gpu/drm/i915/intel_workarounds.c | 5
icl_init_clock_gating, since it's not a WA (Rodrigo)
Cc: Rodrigo Vivi
Cc: Praveen Paneri
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
Reviewed-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_pm.c | 9 -
2 files changed, 11 insertions(
Disable blend embellishment in RCC.
v2: Rebased on top of the WA refactoring
v3: Added References (Mika)
References: HSDES#2006665173
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 18 +++---
drivers/gpu/drm/i915/intel_workarounds.c
Disable CGPSF unit clock gating to prevent an issue.
v2: Rebased on top of the WA refactoring
v3: Added References (Mika)
References: HSDES#1406838659
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 13 -
drivers/gpu/drm/i915
Cc: Rodrigo Vivi
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/intel_workarounds.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gpu/drm/i915/intel_workarounds.c
index 38e3776..ffb0e30 100644
--- a/drivers/gpu
Added References (Mika)
References: HSDES#2006611047
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++--
drivers/gpu/drm/i915/intel_workarounds.c | 7 +++
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg
Disable MSC clock gating to prevent data corruption.
BSpec: 19257
v2: Rebased on top of the WA refactoring
v3: Added References (Mika)
References: HSDES#1405779004
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915
)
- Do not apply together with another WA for the same
register (not worth the hassle)
References: HSDES#1604223664
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 6 ++
drivers/gpu/drm/i915/intel_workarounds.c | 10 ++
2 files changed
List of GT workarounds for Icelake that we have been carrying in internal.
Oscar Mateo (22):
drm/i915/icl: Introduce initial Icelake Workarounds
drm/i915/icl: Enable Sampler DFR
drm/i915/icl: WaGAPZPriorityScheme
drm/i915/icl: WaL3BankAddressHashing
drm/i915/icl
Revert to the legacy implementation to avoid a system hang.
v2: Correct the address for GAMW_ECO_DEV_RW_IA_REG
v3: Renamed to Wa_220166154
v4: Rebased on top of the WA refactoring
v5: Added References (Mika)
References: HSDES#220166154
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers
Adjust default GAM TLB partitioning for performance reasons.
v2: Only touch the bits that we really need
v3: Rebased on top of the WA refactoring
v4:
- Added References (Mika)
- Rebased
References: HSDES#220260670
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915
icelake_init_clock_gating()
from Paulo Zanoni
- Squashed with this patch:
drm/i915/icl: WaForceEnableNonCoherent
from Oscar Mateo
- WaPushConstantDereferenceHoldDisable is now Wa_1604370585 and
applies to B0 as well.
- WaPipeControlBefore3DStateSamplePattern WABB was being
On 5/2/2018 3:23 AM, Mika Kuoppala wrote:
Oscar Mateo writes:
Revert to an L3 non-hash model, for performance reasons.
v2:
- Place the WA name above the actual change
- Improve the register naming
v3:
- Rebased
- Renamed to Wa_1604223664
v4: Rebased on top of the WA refactoring
Obviously the subject is wrong: it should say 0/5 instead of 0/8 (I
copied the subject from the cover letter meant from internal, without
realizing the number of patches was different).
On 5/2/2018 12:03 PM, Oscar Mateo wrote:
Bare minimum number of patches to get the GuC to authenticate the
0)
v6: Use the latest firmware (v26.171)
v7: Rebased (remove guc-core-family)
v8: Use the latest firmware (v27.182)
v9: Use the latest firmware (v27.185)
Signed-off-by: Michel Thierry
Signed-off-by: Oscar Mateo
Cc: Michal Wajdeczko
Cc: John Spotswood
Cc: Tony Ye
Cc: Joonas Lahtinen
Cc: Danie
The register to check for correct HuC authentication by the GuC
has changed in Icelake. Look into the right register & bit.
v2: rebased.
v3: rebased.
v4: Fix I915_PARAM_HUC_STATUS as well (Tony)
v5: Fix duplicate Cc
BSpec: 19686
Signed-off-by: Oscar Mateo
Cc: Tony Ye
Cc: Vinay Belgaumkar
Sanitize the enable_guc option so that we can enable HuC authentication,
but nothing else. The firmware interface has changed quite dramatically
in Gen11, so it will take a while before we can submit workloads to the
GuC with guarantees.
Signed-off-by: Oscar Mateo
Cc: Joonas Lahtinen
Cc: Michal
This patch adds the support to load HuC on ICL.
Version 8.02.2678
v2 (James): Rebase
Signed-off-by: Oscar Mateo
Cc: Tony Ye
Cc: Vinay Belgaumkar
Cc: Michel Thierry
Cc: Joonas Lahtinen
Cc: Michal Wajdeczko
Cc: John Spotswood
Cc: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_huc_fw.c
Bare minimum number of patches to get the GuC to authenticate the
HuC correctly (i915.enable_guc=2).
Oscar Mateo (5):
drm/i915/icl/guc: Do not allow GuC submission on Icelake for now
drm/i915/icl/guc: Pass the bare minimum GuC init parameters for
Icelake
drm/i915/icl/guc: Define the GuC
Only enough to achieve HuC authentication. No GuC submission
or any other feature for the time being.
v2: Fix extra space
Signed-off-by: Oscar Mateo
Cc: Joonas Lahtinen
Cc: Michal Wajdeczko
Cc: John Spotswood
Cc: Tony Ye
Cc: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_guc.c | 10
On 04/30/2018 04:34 PM, John Spotswood wrote:
On Fri, 2018-04-27 at 14:31 -0700, Oscar Mateo wrote:
A GuC firmware for Icelake is now available. Let's use it.
v2: Split out the Cannonlake stuff in a separate patch (Michal)
v3: Rebased
v4:
- Rebased
- Split out MODULE_FIRMWARE
On 04/30/2018 04:29 PM, John Spotswood wrote:
On Fri, 2018-04-27 at 14:31 -0700, Oscar Mateo wrote:
Only enough to achieve HuC authentication. No GuC submission
or any other feature for the time being.
Signed-off-by: Oscar Mateo
Cc: Joonas Lahtinen
Cc: Michal Wajdeczko
Cc: John Spotswood
On 04/26/2018 08:01 AM, Mika Kuoppala wrote:
Oscar Mateo writes:
Inherit workarounds from previous platforms that are still valid for
Icelake.
v2: GEN7_ROW_CHICKEN2 is masked
v3:
- Since it has been fixed already in upstream, removed the TODO
comment about WA_SET_BIT for
On 04/26/2018 08:27 AM, Mika Kuoppala wrote:
Oscar Mateo writes:
The default GAPZ arbitrer priority value at power-on has been found
to be incorrect.
v2: Now renamed to Wa_1405543622
v3: Rebased on top of the WA refactoring
I have suggested that when implementing workarounds,
authors
Bare minimum number of patches to get the GuC to authenticate the
HuC correctly (i915.enable_guc=2).
Oscar Mateo (5):
drm/i915/icl/guc: Do not allow GuC submission on Icelake for now
drm/i915/icl/guc: Pass the bare minimum GuC init parameters for
Icelake
drm/i915/icl/guc: Define the GuC
Sanitize the enable_guc option so that we can enable HuC authentication,
but nothing else. The firmware interface has changed quite dramatically
in Gen11, so it will take a while before we can submit workloads to the
GuC with guarantees.
Signed-off-by: Oscar Mateo
Cc: Joonas Lahtinen
Cc: Michal
0)
v6: Use the latest firmware (v26.171)
v7: Rebased (remove guc-core-family)
v8: Use the latest firmware (v27.182)
Cc: Michal Wajdeczko
Cc: John Spotswood
Cc: Tony Ye
Cc: Joonas Lahtinen
Cc: Daniele Ceraolo Spurio
Signed-off-by: Michel Thierry
Signed-off-by: Oscar Mateo
---
drivers/gp
The register to check for correct HuC authentication by the GuC
has changed in Icelake. Look into the right register & bit.
v2: rebased.
v3: rebased.
v4: Fix I915_PARAM_HUC_STATUS as well (Tony)
BSpec: 19686
Signed-off-by: Oscar Mateo
Cc: Tony Ye
Cc: Vinay Belgaumkar
Cc: Michel Thierry
This patch adds the support to load HuC on ICL.
Version 8.02.2678
v2 (James): Rebase
Signed-off-by: Oscar Mateo
Cc: Tony Ye
Cc: Vinay Belgaumkar
Cc: Michel Thierry
Cc: Joonas Lahtinen
Cc: Michal Wajdeczko
Cc: John Spotswood
---
drivers/gpu/drm/i915/intel_huc_fw.c | 11 +++
1 file
Only enough to achieve HuC authentication. No GuC submission
or any other feature for the time being.
Signed-off-by: Oscar Mateo
Cc: Joonas Lahtinen
Cc: Michal Wajdeczko
Cc: John Spotswood
Cc: Tony Ye
---
drivers/gpu/drm/i915/intel_guc.c | 10 --
drivers/gpu/drm/i915
: Michel Thierry
Signed-off-by: Rodrigo Vivi
Signed-off-by: Michel Thierry
Signed-off-by: Oscar Mateo
Cc: Tvrtko Ursulin
Cc: Daniele Ceraolo Spurio
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_irq.c | 6 ++--
drivers/gpu/drm/i915/intel_drv.h | 3 ++
drivers/gpu/drm/i915/intel_lrc.c
On 04/20/2018 01:53 PM, Rodrigo Vivi wrote:
On Fri, Apr 20, 2018 at 01:49:45PM -0700, Oscar Mateo wrote:
On 04/20/2018 01:46 PM, Rodrigo Vivi wrote:
On Fri, Apr 20, 2018 at 01:33:54PM -0700, Oscar Mateo wrote:
Disable GWL clock gating to prevent two different issues that
might cause hangs
On 04/20/2018 02:26 PM, Rodrigo Vivi wrote:
On Fri, Apr 20, 2018 at 01:52:24PM -0700, Oscar Mateo wrote:
On 04/20/2018 01:48 PM, Rodrigo Vivi wrote:
On Fri, Apr 20, 2018 at 01:33:46PM -0700, Oscar Mateo wrote:
Sampler Dynamic Frequency Rebalancing (DFR) aims to reduce Sampler
power by
On 04/20/2018 01:48 PM, Rodrigo Vivi wrote:
On Fri, Apr 20, 2018 at 01:33:46PM -0700, Oscar Mateo wrote:
Sampler Dynamic Frequency Rebalancing (DFR) aims to reduce Sampler
power by dynamically changing its clock frequency in low-throughput
conditions. This patches enables it by default on
On 04/20/2018 01:46 PM, Rodrigo Vivi wrote:
On Fri, Apr 20, 2018 at 01:33:54PM -0700, Oscar Mateo wrote:
Disable GWL clock gating to prevent two different issues that
might cause hangs.
Please notice that one of the issues is pre-production only.
v2: Rebased on top of the WA refactoring
Cc
of the WA refactoring
v4: Rebased on top of the whitelist reg refactoring (Michel)
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gp
Disable MSC clock gating to prevent data corruption.
BSpec: 19257
v2: Rebased on top of the WA refactoring
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_workarounds.c | 6 ++
2 files changed, 7 insertions
Revert to the legacy implementation to avoid a system hang.
v2: Correct the address for GAMW_ECO_DEV_RW_IA_REG
v3: Renamed to Wa_220166154
v4: Rebased on top of the WA refactoring
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu
Disable I2M Write for performance reasons.
v2: Rebased on top of the WA refactoring
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 4 +++-
drivers/gpu/drm/i915/intel_workarounds.c | 5 +
2 files changed, 8 insertions(+), 1 deletion(-)
diff
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