Re: [Intel-gfx] [PATCH] drm/i915/cnl: WaForceContextSaveRestoreNonCoherent

On 09/28/2017 01:56 PM, Oscar Mateo wrote: On 09/28/2017 02:46 AM, Chris Wilson wrote: Stealing the thread for another gem_workarounds conundrum. After a reset, we lose the RING_FORCE_TO_NONPRIV registers. If they where in the context image as we presumed, the values would be retained

Re: [Intel-gfx] [PATCH] drm/i915/cnl: WaForceContextSaveRestoreNonCoherent

On 09/28/2017 02:46 AM, Chris Wilson wrote: Stealing the thread for another gem_workarounds conundrum. After a reset, we lose the RING_FORCE_TO_NONPRIV registers. If they where in the context image as we presumed, the values would be retained and they can be read back from before reset, so

Re: [Intel-gfx] [PATCH] drm/i915/cnl: Avoid WA_SET_BIT_MASK on write-only CNL_HDC_CHICKEN0.

On 09/27/2017 02:17 PM, Rodrigo Vivi wrote: On Wed, Sep 27, 2017 at 09:08:10PM +, Oscar Mateo wrote: On 09/27/2017 02:01 PM, Rodrigo Vivi wrote: On CNL, HDC_CHICKEN0 "is write-only from LRI command. However, it is readable for context save." So we have no ways to check the

Re: [Intel-gfx] [PATCH] drm/i915/cnl: Avoid WA_SET_BIT_MASK on write-only CNL_HDC_CHICKEN0.

xt). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102943 Fixes: acfb5554c769 ("drm/i915/cnl: WaForceContextSaveRestoreNonCoherent") Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com> Cc: Oscar Mateo <oscar.ma...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.u

Re: [Intel-gfx] [PATCH] drm/i915/cnl: WaForceContextSaveRestoreNonCoherent

evious platforms, but the change for CNL is more on the register offset. But also BSpec doesn't mention the bit 15 as set on gen9 platforms and mark bit as reserved on CNL. Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com> Cc: Oscar Mateo <oscar.ma...@intel.com> Signed-off-by: Rodri

Re: [Intel-gfx] [PATCH] drm/i915/cnl: Fix SSEU Device Status.

since this change also needs review. Cc: Oscar Mateo <oscar.ma...@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.v...@intel.com> --- drivers/gpu/drm/i915/i915_debugfs.c | 54 +++-- drivers/gpu/drm/i915/i915_reg.h | 6 + 2 files changed, 5

[Intel-gfx] [PATCH] drm/i915/cnl: Add Gen10 LRC size

The total size of the context has decreased with the removal of the URB_ATOMIC section. BSpec indicates 16750 DWORDs (17 pages), plus one page for PPHWSP, and I'm throwing an extra page for precaution. Signed-off-by: Oscar Mateo <oscar.ma...@intel.com> Cc: Rodrigo Vivi <rodrigo.v...@inte

Re: [Intel-gfx] [PATCH 08/10] drm/i915/guc: Fix GuC HW/SW state cleanup in unload path

On 09/21/2017 12:09 PM, Sagar Arun Kamble wrote: On 9/22/2017 12:03 AM, Oscar Mateo wrote: On 09/17/2017 05:17 AM, Sagar Arun Kamble wrote: Teardown of GuC HW/SW state was not properly done in unload path. guc_submission_disable was called as part of intel_uc_fini_hw which happens post

Re: [Intel-gfx] [PATCH 08/10] drm/i915/guc: Fix GuC HW/SW state cleanup in unload path

On 09/17/2017 05:17 AM, Sagar Arun Kamble wrote: Teardown of GuC HW/SW state was not properly done in unload path. guc_submission_disable was called as part of intel_uc_fini_hw which happens post gem_unload in the i915_driver_unload path. s/i915_gem_fini/i915_gem_cleanup as it looks more

Re: [Intel-gfx] [PATCH 2/2] drm/i915/cnl: Fix SSEU Device Status.

status function. v3: Consider s_max = 6 and ss_max=4 to run over all possible slices and subslices possible by spec. Although no real hardware will have that many slices/subslices. To match with sseu info init. Even better :) Cc: Oscar Mateo <oscar.ma...@intel.com> Sign

Re: [Intel-gfx] [PATCH 2/2] drm/i915/cnl: Fix SSEU Device Status.

status function. Cc: Oscar Mateo <oscar.ma...@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.v...@intel.com> Reviewed-by: Oscar Mateo <oscar.ma...@intel.com> --- drivers/gpu/drm/i915/i915_debugfs.c | 54 +++-- drivers/gpu/drm/i915/i915_reg.h

Re: [Intel-gfx] [PATCH 1/2] drm/i915/cnl: Add support slice/subslice/eu configs

d by Oscar. Cc: Oscar Mateo <oscar.ma...@intel.com> Signed-off-by: Ben Widawsky <b...@bwidawsk.net> Signed-off-by: Rodrigo Vivi <rodrigo.v...@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 8 +++ drivers/gpu/drm/i915/intel_device_info.c | 37 +

Re: [Intel-gfx] [PATCH 1/2] drm/i915/cnl: Add support slice/subslice/eu configs

nd add proper the comment. v4: This v4 done by Rodrigo includes: - Consider all bits available: 6 bits for slices [27:22] and 4 for subslices [21:18]. Cc: Oscar Mateo <oscar.ma...@intel.com> Signed-off-by: Ben Widawsky <b...@bwidawsk.net> Signed-off-by: Rodrigo Vivi <r

Re: [Intel-gfx] [PATCH 1/2] drm/i915/cnl: Add support slice/subslice/eu configs

nd add proper the comment. Cc: Oscar Mateo <oscar.ma...@intel.com> Signed-off-by: Ben Widawsky <b...@bwidawsk.net> Signed-off-by: Rodrigo Vivi <rodrigo.v...@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 8 +++ drivers/gpu/drm/i915/

Re: [Intel-gfx] [PATCH 2/2] drm/i915/cnl: Fix SSEU Device Status.

of the die instead of other slices or anything like that. Also if subslice is disabled the information of eu ack for that is garbage, so let's skip checks for eu if subslice is disabled as we skip the subslice if slice is disabled. The rest is pretty much like gen9. Cc: Oscar Mateo <oscar

Re: [Intel-gfx] [PATCH] drm/i915: Move the context descriptor to an inline helper

files changed, 9 insertions(+), 8 deletions(-) Reviewed-by: Oscar Mateo <oscar.ma...@intel.com> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 5837b33f9705..7457783ed182 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915

[Intel-gfx] [PATCH 2/3] drm/i915/guc: Remove WQ_WORKLOAD_SHIFT define

We never used it in i915 and it's going to be removed in newer GuC firmwares anyway. Signed-off-by: Oscar Mateo <oscar.ma...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> --- drivers/gpu/drm/i915/intel_guc_fwif.h | 4 1 file changed, 4 deletions(-) diff --g

[Intel-gfx] [PATCH 1/3] drm/i915/guc: Name the default GuC scheduling policy

The default values for the default scheduling policy come from the GuC firmware itself. Transform the magic numbers into defines. Suggested-by: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Signed-off-by: Oscar Mateo <oscar.ma...@intel.com> --- drivers/gpu/drm/i915/i915_guc_submi

[Intel-gfx] [PATCH 3/3] drm/i915/guc: Small improvements to guc_wq_item_append

Spare some comments and other small style changes. Suggested-by: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Signed-off-by: Oscar Mateo <oscar.ma...@intel.com> --- drivers/gpu/drm/i915/i915_guc_submission.c | 15 +++ 1 file changed, 7 insertions(+), 8 deletions(-)

Re: [Intel-gfx] [PATCH] drm/i915: Transform WaInPlaceDecompressionHang to a simple reg write

On 09/07/2017 02:30 AM, Mika Kuoppala wrote: Oscar Mateo <oscar.ma...@intel.com> writes: Hey Mika, Regarding this patch: is there a consensus on where is the most appropriate place to apply workarounds? My understanding is that per-context workarounds (WAS_SET_BIT, etc.

Re: [Intel-gfx] [PATCH 1/6] drm/i915: Transform WaInPlaceDecompressionHang into a simple reg write

On 09/07/2017 04:03 AM, Michał Winiarski wrote: On Wed, Sep 06, 2017 at 05:15:49PM -0700, Oscar Mateo wrote: Afaict, GEN9_GAMT_ECO_REG_RW_IA does not live in the context, so writing it on every context creation is overkill (and wrong). v2: Missing end parenthesis Though

[Intel-gfx] [PATCH 2/6] drm/i915: Transform WaDisableI2mCycleOnWRPort into a simple reg write

GAMT_CHKN_BIT_REG does not live in the context. Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuopp...@intel.com> Cc: Rodrigo Vivi <rodrigo.v...@intel.com> Signed-off-by: Oscar Mateo <oscar.ma...@intel.com> Reviewed-by: Michał Winiarski <

[Intel-gfx] [PATCH 4/6] drm/i915: Transform WaDisableGafsUnitClkGating into a simple reg write

GEN7_UCGCTL4 does not live in the context. v2: Missing parenthesis Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuopp...@intel.com> Cc: Rodrigo Vivi <rodrigo.v...@intel.com> Signed-off-by: Oscar Mateo <oscar.ma...@intel.com> Reviewed-by: Michał

[Intel-gfx] [PATCH 3/6] drm/i915: WaPushConstantDereferenceHoldDisable needs to modify a masked register

So do it correctly. Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuopp...@intel.com> Cc: Rodrigo Vivi <rodrigo.v...@intel.com> Signed-off-by: Oscar Mateo <oscar.ma...@intel.com> Reviewed-by: Michał Winiarski <michal.winiar...@intel.com

[Intel-gfx] [PATCH 1/6] drm/i915: Transform WaInPlaceDecompressionHang into a simple reg write

com> Signed-off-by: Oscar Mateo <oscar.ma...@intel.com> Reviewed-by: Michał Winiarski <michal.winiar...@intel.com> --- drivers/gpu/drm/i915/intel_engine_cs.c | 25 +++-- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_

[Intel-gfx] [PATCH 6/6] drm/i915: Transform WaDisablePooledEuLoadBalancingFix into a simple register write

FF_SLICE_CS_CHICKEN2 does not belong to the context image. Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuopp...@intel.com> Cc: Rodrigo Vivi <rodrigo.v...@intel.com> Signed-off-by: Oscar Mateo <oscar.ma...@intel.com> Reviewed-by: Michał Winiarski <

[Intel-gfx] [PATCH 5/6] drm/i915: Transform WaDisableDynamicCreditSharing into a simple register write

GAMT_CHKN_BIT_REG does not live in the context image. Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuopp...@intel.com> Cc: Rodrigo Vivi <rodrigo.v...@intel.com> Signed-off-by: Oscar Mateo <oscar.ma...@intel.com> Reviewed-by: Michał Winiarski <

[Intel-gfx] [PATCH 5/6] drm/i915: Transform WaDisableDynamicCreditSharing into a simple register write

GAMT_CHKN_BIT_REG does not live in the context image. Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuopp...@intel.com> Cc: Rodrigo Vivi <rodrigo.v...@intel.com> Signed-off-by: Oscar Mateo <oscar.ma...@intel.com> --- drivers/gpu/drm/i915/intel_engin

[Intel-gfx] [PATCH 3/6] drm/i915: WaPushConstantDereferenceHoldDisable needs to modify a masked register

So do it correctly. Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuopp...@intel.com> Cc: Rodrigo Vivi <rodrigo.v...@intel.com> Signed-off-by: Oscar Mateo <oscar.ma...@intel.com> --- drivers/gpu/drm/i915/intel_engine_cs.c | 2 +- 1 file changed, 1

[Intel-gfx] [PATCH 6/6] drm/i915: Transform WaDisablePooledEuLoadBalancingFix into a simple register write

FF_SLICE_CS_CHICKEN2 does not belong to the context image. Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuopp...@intel.com> Cc: Rodrigo Vivi <rodrigo.v...@intel.com> Signed-off-by: Oscar Mateo <oscar.ma...@intel.com> --- drivers/gpu/drm/i915/intel

[Intel-gfx] [PATCH 2/6] drm/i915: Transform WaDisableI2mCycleOnWRPort into a simple reg write

GAMT_CHKN_BIT_REG does not live in the context. Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuopp...@intel.com> Cc: Rodrigo Vivi <rodrigo.v...@intel.com> Signed-off-by: Oscar Mateo <oscar.ma...@intel.com> --- drivers/gpu/drm/i915/intel_engine_

[Intel-gfx] [PATCH 1/6] drm/i915: Transform WaInPlaceDecompressionHang into a simple reg write

com> Signed-off-by: Oscar Mateo <oscar.ma...@intel.com> --- drivers/gpu/drm/i915/intel_engine_cs.c | 25 +++-- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index

[Intel-gfx] [PATCH 4/6] drm/i915: Transform WaDisableGafsUnitClkGating into a simple reg write

GEN7_UCGCTL4 does not live in the context. Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuopp...@intel.com> Cc: Rodrigo Vivi <rodrigo.v...@intel.com> Signed-off-by: Oscar Mateo <oscar.ma...@intel.com> --- drivers/gpu/drm/i915/intel_engine_cs.c | 9 +

Re: [Intel-gfx] [PATCH 64/67] drm/i915/cnl: WaThrottleEUPerfToAvoidTDBackPressure:cnl(pre-prod)

rivers/gpu/drm/i915/intel_engine_cs.c | 4 2 files changed, 5 insertions(+) Reviewed-by: Oscar Mateo <oscar.ma...@intel.com> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 67f306e..8b25119 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/

Re: [Intel-gfx] [PATCH] drm/i915: Transform WaInPlaceDecompressionHang to a simple reg write

On 09/06/2017 02:43 PM, Chris Wilson wrote: Quoting Oscar Mateo (2017-09-06 22:27:47) On 09/06/2017 02:19 PM, Chris Wilson wrote: Quoting Oscar Mateo (2017-09-06 22:12:11) Afaict, GEN9_GAMT_ECO_REG_RW_IA does not live in the context, so writing it on every context creation is overkill

Re: [Intel-gfx] [PATCH] drm/i915: Transform WaInPlaceDecompressionHang to a simple reg write

On 09/06/2017 02:19 PM, Chris Wilson wrote: Quoting Oscar Mateo (2017-09-06 22:12:11) Afaict, GEN9_GAMT_ECO_REG_RW_IA does not live in the context, so writing it on every context creation is overkill (and wrong). Cc: Mika Kuoppala <mika.kuopp...@intel.com> Cc: Rodrigo Vivi <

Re: [Intel-gfx] [PATCH] drm/i915: Transform WaInPlaceDecompressionHang to a simple reg write

On 09/06/2017 02:12 PM, Oscar Mateo wrote: Afaict, GEN9_GAMT_ECO_REG_RW_IA does not live in the context, so writing it on every context creation is overkill (and wrong). Cc: Mika Kuoppala <mika.kuopp...@intel.com> Cc: Rodrigo Vivi <rodrigo.v...@intel.com> Signed-off-by: Oscar Mat

[Intel-gfx] [PATCH] drm/i915: Transform WaInPlaceDecompressionHang to a simple reg write

Afaict, GEN9_GAMT_ECO_REG_RW_IA does not live in the context, so writing it on every context creation is overkill (and wrong). Cc: Mika Kuoppala <mika.kuopp...@intel.com> Cc: Rodrigo Vivi <rodrigo.v...@intel.com> Signed-off-by: Oscar Mateo <oscar.ma...@intel.com> --- dr

Re: [Intel-gfx] [PATCH] drm/i915/cnl: Add support slice/subslice/eu configs

[1][2] and [2][2]. - Inclusion of EU Per Subslice. - Commit message. Cc: Oscar Mateo <oscar.ma...@intel.com> Signed-off-by: Ben Widawsky <b...@bwidawsk.net> Signed-off-by: Rodrigo Vivi <rodrigo.v...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 5 +++

Re: [Intel-gfx] [PATCH] drm/i915/cnl: WA FtrEnableFastAnisoL1BankingFix

On 08/29/2017 04:07 PM, Rodrigo Vivi wrote: WA to enable HW L1 Banking fix that allows aniso to operate at full sample rate. Cc: Mika Kuoppala <mika.kuopp...@intel.com> Cc: Oscar Mateo <oscar.ma...@intel.com> Cc: Ben Widawsky <b...@bwidawsk.net> Cc: Anuj Phogat <anuj.pho

Re: [Intel-gfx] [PATCH] drm/i915/cnl: WaForceEnableNonCoherent

On 08/25/2017 12:41 AM, Michał Winiarski wrote: On Thu, Aug 24, 2017 at 03:42:05PM -0700, Oscar Mateo wrote: On 08/23/2017 03:02 PM, Rodrigo Vivi wrote: Must Force Non-Coherent whenever executing a 3D context. This is a workaround for a possible hang in the unlikely event a TLB

Re: [Intel-gfx] [PATCH] drm/i915/guc: Add GuC Load time to debugfs

Cc: Sujaritha On 08/24/2017 09:38 PM, Anusha Srivatsa wrote: Calculate the time that GuC takes to load. This information could be very useful in determining if GuC is taking unreasonably long time to load in a certain platforms. Cc: Oscar Mateo <oscar.ma...@intel.com> Cc: Michal Waj

Re: [Intel-gfx] [PATCH] drm/i915/cnl: WaForceEnableNonCoherent

anymore. A different reason to keep doing this is performance, though. Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com> Cc: Oscar Mateo <oscar.ma...@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.v...@intel.com> --- drivers/gpu/drm/i915/intel_engine_cs.c | 5 - 1 file cha

Re: [Intel-gfx] [PATCH] drm/i915: Allow null render state batchbuffers bigger than one page

On 08/23/2017 05:01 PM, Rodrigo Vivi wrote: On Tue, Jul 18, 2017 at 8:15 AM, Oscar Mateo <oscar.ma...@intel.com> wrote: On 07/14/2017 08:08 AM, Chris Wilson wrote: Quoting Oscar Mateo (2017-07-14 15:52:59) On 07/13/2017 03:28 PM, Rodrigo Vivi wrote: On Wed, May 3, 2017 at 9

[Intel-gfx] [PATCH] drm/i915: Create vfuncs for the reset/enable/disable GuC functions

ele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Signed-off-by: Oscar Mateo <oscar.ma...@intel.com> --- drivers/gpu/drm/i915/i915_guc_submission.c | 4 ++-- drivers/gpu/drm/i915/i915_irq.c| 18 -- drivers/gpu/drm/i915/intel_drv.h | 3 --- driver

[Intel-gfx] [PATCH 2/2] drm/i915: Create vfuncs for the reset/enable/disable GuC functions

Facilitates creating Gen-specific versions of these functions later on. Cc: Rodrigo Vivi <rodrigo.v...@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursu...@intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Si

[Intel-gfx] [PATCH 1/2] drm/i915: Make some RPS functions static

They are not used anywhere else. Also, fix a small typo in a comment. No functional changes. Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Rodrigo Vivi <rodrigo.v...@intel.com> Signed-off-by: Oscar Mateo <oscar.ma...@intel.com> --- drivers/gpu/drm/i915/i915_irq.c | 8

Re: [Intel-gfx] [PATCH] drm/i915/cnl: WaForceContextSaveRestoreNonCoherent

ffset has changed for CNL"? But also BSpec doesn't mention the bit 15 as set on gen9 platforms and mark bit as reserved on CNL. Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com> Cc: Oscar Mateo <oscar.ma...@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.v...@intel.com>

[Intel-gfx] [PATCH] drm/i915/cnl: WaPushConstantDereferenceHoldDisable

CS sometimes hangs on 3D Push Constant dispatches with the new deref enhancement logic in CNL. v2: Improve the commit message (Rodrigo) Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com> Signed-off-by: Oscar Mateo <oscar.ma...@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo

Re: [Intel-gfx] [PATCH] drm/i915/cnl: WaPushConstantDereferenceHoldDisable

Oops... forgot to add v2 tag. Hang on a second. On 08/23/2017 12:53 PM, Oscar Mateo wrote: CS sometimes hangs on 3D Push Constant dispatches with the new deref enhancement logic in CNL. Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com> Signed-off-by: Oscar Mateo <oscar.ma...@

[Intel-gfx] [PATCH] drm/i915/cnl: WaPushConstantDereferenceHoldDisable

CS sometimes hangs on 3D Push Constant dispatches with the new deref enhancement logic in CNL. Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com> Signed-off-by: Oscar Mateo <oscar.ma...@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.v...@intel.com> --- drivers/gpu/drm/i915/i91

[Intel-gfx] [PATCH] drm/i915/cnl: WaPushConstantDereferenceHoldDisable

Disable deref enhancement logic. Cc: Rodrigo Vivi <rodrigo.v...@intel.com> Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com> Signed-off-by: Oscar Mateo <oscar.ma...@intel.com> --- drivers/gpu/drm/i915/i915_reg.h| 1 + drivers/gpu/drm/i915/intel_engine_cs.c | 3 +++

Re: [Intel-gfx] [PATCH 1/4] drm/i915/cnl: Introduce initial Cannonlake Workarounds.

workarounds were changed to be A0 only so let's remove them. Cc: Oscar Mateo <oscar.ma...@intel.com> Cc: Mika Kuoppala <mika.kuopp...@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.v...@intel.com> --- Reviewed-by: Oscar Mateo <oscar.ma...@intel.com> drivers/gpu

Re: [Intel-gfx] [PATCH 4/4] drm/i915/cnl: Apply large line width optimization

omment to make clear it is not an Wa. Cc: Oscar Mateo <oscar.ma...@intel.com> Signed-off-by: Ben Widawsky <benjamin.widaw...@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.v...@intel.com> --- Reviewed-by: Oscar Mateo <oscar.ma...@intel.com> drivers/gpu/drm/i915/i915

Re: [Intel-gfx] [PATCH 4/4] drm/i915/cnl: Apply large line width optimization

On 07/05/2017 06:02 PM, Rodrigo Vivi wrote: This bit enables hardware that will change the approximation used for distances calculations for AA wide lines so that they are rendered more accurately. The default value for this bit leaves the legacy behavior. There is no good reason to not

Re: [Intel-gfx] [PATCH 2/4] drm/i915/cnl: Add WaDisableReplayBufferBankArbitrationOptimization

On 07/05/2017 06:02 PM, Rodrigo Vivi wrote: WA to disable replay buffer destination buffer arbitration optimization. Same Wa on previous platforms has a different name: WaToEnableHwFixForPushConstHWBug Signed-off-by: Rodrigo Vivi Reviewed-by: Mika Kuoppala

Re: [Intel-gfx] [PATCH 1/4] drm/i915/cnl: Introduce initial Cannonlake Workarounds.

/a that are not needed anymore. v5: Rebase on top of CFL. v6: Remove empty gen9_init_perctx_bb and gen9_init_indirectctx_bb since they don't carry any gen10 related W/a. (by Oscar). Also Remove A0 exclusive workaround. Cc: Oscar Mateo <oscar.ma...@intel.com> Cc: Mika Kuoppala <m

Re: [Intel-gfx] [PATCH v3 14/16] drm/i915/guc: Enable GuC interrupts when using CT

On 08/09/2017 09:24 AM, Michal Wajdeczko wrote: We will need them in G2H communication to properly handle responses and requests from the Guc. v2: keep irq enabled while disabling GuC logging (Oscar) Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Oscar Mateo <

Re: [Intel-gfx] [PATCH v2 14/16] drm/i915/guc: Enable GuC interrupts when using CT

On 08/07/2017 09:14 AM, Michal Wajdeczko wrote: We will need them in G2H communication to properly handle responses and requests from the Guc. Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Oscar Mateo <oscar.ma...@intel.com> Cc: Daniele Ceraolo Spurio <dan

Re: [Intel-gfx] [PATCH] drm/i915: Allow null render state batchbuffers bigger than one page

On 07/14/2017 08:08 AM, Chris Wilson wrote: Quoting Oscar Mateo (2017-07-14 15:52:59) On 07/13/2017 03:28 PM, Rodrigo Vivi wrote: On Wed, May 3, 2017 at 9:31 AM, Chris Wilson <ch...@chris-wilson.co.uk> wrote: On Wed, May 03, 2017 at 09:12:18AM +, Oscar Mateo wrote: On

Re: [Intel-gfx] [PATCH] drm/i915: Allow null render state batchbuffers bigger than one page

On 07/13/2017 03:28 PM, Rodrigo Vivi wrote: On Wed, May 3, 2017 at 9:31 AM, Chris Wilson <ch...@chris-wilson.co.uk> wrote: On Wed, May 03, 2017 at 09:12:18AM +, Oscar Mateo wrote: On 05/03/2017 08:52 AM, Mika Kuoppala wrote: Oscar Mateo [1]<oscar.ma...@intel.co

Re: [Intel-gfx] [PATCH] tools/null_state_gen: Add GEN10 golden context batch buffer creation

Device initialization failed (-22) [4.535390] i915 :00:02.0: Please file a bug at https://bugs.freedesktop.org/enter_bug.cgi?product=DRI against DRM/Intel providing the dmesg log by booting with drm.debug=0xf [4.535450] i915: probe of :00:02.0 failed with error -22 On Fri, Apr 28, 2017

Re: [Intel-gfx] [PATCH 1/2] drm/i915/guc: Get rid of the enable_guc_loading module parameter

On 05/18/2017 05:41 PM, Michal Wajdeczko wrote: On Fri, May 05, 2017 at 01:23:17PM +, Oscar Mateo wrote: The decission to enable GuC loading shouldn't be left to the user. Provided the HW supports the GuC, there are only two reasons to load it: - The user has requested GuC submission

[Intel-gfx] [PATCH v2] drm/i915/guc: Dump the GuC stage descriptor pool in debugfs

We are missing pieces of information that could be useful for GuC debugging. v2: Reuse some code (Joonas) Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Reviewed-by: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Signed-off-by: Oscar Mateo <oscar.ma...@intel.co

Re: [Intel-gfx] [RFC] drm/i915: Allow the UMD to configure their own power clock state

On 05/10/2017 01:28 PM, Daniel Vetter wrote: On Wed, May 10, 2017 at 2:59 PM, Joonas Lahtinen wrote: @@ -841,6 +847,11 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine) if (ret) return ret; + /* Allow the UMD to

Re: [Intel-gfx] [RFC] drm/i915: Allow the UMD to configure their own power clock state

On 05/10/2017 02:09 PM, Michał Winiarski wrote: On Wed, May 10, 2017 at 04:47:50PM +0300, Mika Kuoppala wrote: Oscar Mateo <oscar.ma...@intel.com> writes: This allows userspace to shutdown slices at will for performance/power reasons (because it doesn't have a use for more slices

[Intel-gfx] [PATCH] drm/i915/guc: Dump the GuC stage descriptor pool in debugfs

We are missing pieces of information that could be useful for GuC debugging. Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Signed-off-by: Oscar Mateo <oscar.ma...@intel.com> --- drivers/gpu/drm/i915/i

[Intel-gfx] [PATCH RFC 2/2] drm/i915/guc: Rename has_guc to has_uc

intel.com> Signed-off-by: Oscar Mateo <oscar.ma...@intel.com> --- drivers/gpu/drm/i915/i915_debugfs.c | 6 +++--- drivers/gpu/drm/i915/i915_drv.h | 6 +++--- drivers/gpu/drm/i915/i915_pci.c | 10 +- drivers/gpu/drm/i915/intel_guc_loader.c | 4 ++-- drivers/gpu/dr

[Intel-gfx] [PATCH 1/2] drm/i915/guc: Get rid of the enable_guc_loading module parameter

io <daniele.ceraolospu...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Signed-off-by: Oscar Mateo <oscar.ma...@intel.com> --- drivers/gpu/drm/i915/i915_debugfs.c | 10 -- drivers/gpu/drm/i915/i915_drv.c | 2 +- drivers/gpu/drm/i915/i915_drv.h

Re: [Intel-gfx] [PATCH v2] tests/pm_sseu: Re-enable the test

On 05/04/2017 08:37 AM, Petri Latvala wrote: On Wed, Apr 26, 2017 at 03:28:09AM -0700, Oscar Mateo wrote: This test got inadvertently disabled by commit 83884e97 (Restore "lib: Open debugfs files for the given DRM device") when the initialization order got changed (dbg_init befor

Re: [Intel-gfx] [RFC] tests/pm_sseu: Add subtest to verify UMD can configure render powerclock state

On 05/03/2017 04:53 PM, Chris Wilson wrote: On Wed, May 03, 2017 at 09:43:08AM +, Oscar Mateo wrote: On 05/03/2017 08:59 AM, Chris Wilson wrote: On Tue, May 02, 2017 at 03:08:27PM +, Oscar Mateo wrote: Cc: Dmitry Rogozhkin <dmitry.v.rogozh...@intel.com> Cc: Chris Wils

Re: [Intel-gfx] [PATCH] drm/i915: Use engine->context_pin() to report the intel_ring

entral i915_gem_request_alloc() and not require it in every engine->request_alloc() callback. Another small step towards simplification (of the core, but at a cost of handling error pointers in less important callers of engine->pin_context). Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Osc

Re: [Intel-gfx] [RFC] tests/pm_sseu: Add subtest to verify UMD can configure render powerclock state

On 05/03/2017 08:59 AM, Chris Wilson wrote: On Tue, May 02, 2017 at 03:08:27PM +, Oscar Mateo wrote: Cc: Dmitry Rogozhkin <dmitry.v.rogozh...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Signed-off-by: Oscar Mateo <oscar.ma...@intel.com> --- tes

Re: [Intel-gfx] [PATCH] drm/i915: Allow null render state batchbuffers bigger than one page

On 05/03/2017 08:52 AM, Mika Kuoppala wrote: Oscar Mateo <oscar.ma...@intel.com> writes: On 05/02/2017 09:17 AM, Mika Kuoppala wrote: Chris Wilson <ch...@chris-wilson.co.uk> writes: On Fri, Apr 28, 2017 at 09:11:06AM +, Oscar Mateo wrote: The new batchbuffer for C

Re: [Intel-gfx] [PATCH] drm/i915: New vfunc prepare_request

On 05/02/2017 08:59 AM, Chris Wilson wrote: On Mon, May 01, 2017 at 07:28:12AM +, Oscar Mateo wrote: On 04/29/2017 08:31 AM, Chris Wilson wrote: On Fri, Apr 28, 2017 at 05:26:09PM +, Oscar Mateo wrote: This will be more useful later to support platforms that need to emit HW

[Intel-gfx] [RFC] drm/i915: Allow the UMD to configure their own power clock state

This allows userspace to shutdown slices at will for performance/power reasons (because it doesn't have a use for more slices). Cc: Dmitry Rogozhkin <dmitry.v.rogozh...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Signed-off-by: Oscar Mateo <oscar.ma...@intel.com> --

[Intel-gfx] [RFC] tests/pm_sseu: Add subtest to verify UMD can configure render powerclock state

Cc: Dmitry Rogozhkin <dmitry.v.rogozh...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Signed-off-by: Oscar Mateo <oscar.ma...@intel.com> --- tests/pm_sseu.c | 105 1 file changed, 105 insertions(+) diff --git a

[Intel-gfx] [RFC] benchmarks/gem_slice_shutdown: microbenchmark for slice shutdown delays

Cc: Dmitry Rogozhkin <dmitry.v.rogozh...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Signed-off-by: Oscar Mateo <oscar.ma...@intel.com> --- benchmarks/Makefile.sources | 1 + benchmarks/gem_slice_shutdown.c | 295 2

Re: [Intel-gfx] [RFC 4/4] drm/i915: Expose RPCS (SSEU) configuration to userspace

On 05/02/2017 07:55 PM, Chris Wilson wrote: On Tue, May 02, 2017 at 10:33:19AM +, Oscar Mateo wrote: On 05/02/2017 11:49 AM, Chris Wilson wrote: We want to allow userspace to reconfigure the subslice configuration for its own use case. To do so, we expose a context parameter to allow

Re: [Intel-gfx] [RFC 4/4] drm/i915: Expose RPCS (SSEU) configuration to userspace

On 05/02/2017 11:49 AM, Chris Wilson wrote: We want to allow userspace to reconfigure the subslice configuration for its own use case. To do so, we expose a context parameter to allow adjustment of the RPCS register stored within the context image (and currently not accessible via LRI).

Re: [Intel-gfx] [PATCH] drm/i915: Allow null render state batchbuffers bigger than one page

On 05/02/2017 09:17 AM, Mika Kuoppala wrote: Chris Wilson <ch...@chris-wilson.co.uk> writes: On Fri, Apr 28, 2017 at 09:11:06AM +, Oscar Mateo wrote: The new batchbuffer for CNL surpasses the 4096 byte mark. Cc: Mika Kuoppala <mika.kuopp...@intel.com> Cc: Ben

Re: [Intel-gfx] [PATCH] drm/i915: New vfunc prepare_request

On 04/29/2017 08:31 AM, Chris Wilson wrote: On Fri, Apr 28, 2017 at 05:26:09PM +, Oscar Mateo wrote: This will be more useful later to support platforms that need to emit HW commands at the beginning of every request (more general than emitting things at the beginning of every batchbuffer

[Intel-gfx] [PATCH] drm/i915: New vfunc prepare_request

htinen <joonas.lahti...@linux.intel.com> Signed-off-by: Oscar Mateo <oscar.ma...@intel.com> --- drivers/gpu/drm/i915/intel_lrc.c| 17 - drivers/gpu/drm/i915/intel_ringbuffer.h | 1 + 2 files changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/dr

Re: [Intel-gfx] [PATCH 12/67] drm/i915/cnl: Introduce initial Cannonlake Workarounds.

On 04/06/2017 07:15 PM, Rodrigo Vivi wrote: Let's inherit workarounds from previous platforms that according to wa_database and BSpec are still valid for Cannonlake. v2: Add missed workarounds. v3: Rebase Cc: Mika Kuoppala Signed-off-by: Rodrigo Vivi

[Intel-gfx] [PATCH] tools/null_state_gen: Add GEN10 golden context batch buffer creation

BSpec), so update the comment in the code and in the commit message. Cc: Mika Kuoppala <mika.kuopp...@intel.com> Cc: Ben Widawsky <b...@bwidawsk.net> Signed-off-by: Oscar Mateo <oscar.ma...@intel.com> --- lib/gen10_render.h | 63 +++ tools/null_sta

[Intel-gfx] [PATCH 2/2] tools/null_state_gen: Add GEN10 golden context batch buffer creation

to modify things *inside* the offline-created bb). So maybe apply the WA for now and remove it once production chips are the norm? Cc: Mika Kuoppala <mika.kuopp...@intel.com> Cc: Ben Widawsky <b...@bwidawsk.net> Signed-off-by: Oscar Mateo <oscar.ma...@intel.com> ---

[Intel-gfx] [PATCH] drm/i915: Allow null render state batchbuffers bigger than one page

The new batchbuffer for CNL surpasses the 4096 byte mark. Cc: Mika Kuoppala <mika.kuopp...@intel.com> Cc: Ben Widawsky <b...@bwidawsk.net> Signed-off-by: Oscar Mateo <oscar.ma...@intel.com> --- drivers/gpu/drm/i915/i915_gem_render_state.c | 40 +++-

[Intel-gfx] [PATCH 1/2] tools/null_state_gen: Automatically generate the copyright header

Last bit to make the generated files directly usable in i915. Cc: Mika Kuoppala <mika.kuopp...@intel.com> Signed-off-by: Oscar Mateo <oscar.ma...@intel.com> --- tools/null_state_gen/intel_null_state_gen.c | 41 + 1 file changed, 41 insertions(+) diff -

[Intel-gfx] [PATCH v2] tests/pm_sseu: Re-enable the test

lt;petri.latv...@intel.com> Signed-off-by: Oscar Mateo <oscar.ma...@intel.com> --- tests/pm_sseu.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/tests/pm_sseu.c b/tests/pm_sseu.c index 317bb26..7d4b33c 100644 --- a/tests/pm_sseu.c +++ b/tests/pm_sseu.c @@ -187,6 +1

[Intel-gfx] [PATCH] tests/pm_sseu: Re-enable the test

This test got inadvertently disabled by commit 83884e97 (Restore "lib: Open debugfs files for the given DRM device"). Cc: Jeff McGee <jeff.mc...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Signed-off-by: Oscar Mateo <oscar.ma...@intel.com> --- tests/pm_sse

[Intel-gfx] [PATCH v4] drm/i915: Use the engine class to get the context size

intel.com> Cc: Rodrigo Vivi <rodrigo.v...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursu...@intel.com> Signed-off-by: Oscar Mateo <oscar.ma.

[Intel-gfx] [PATCH 5/5] drm/i915: Use the engine class to get the context size

: Chris Wilson <ch...@chris-wilson.co.uk> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursu...@intel.com> Signed-off-by: Oscar Mateo <oscar.ma...@intel.com> --- drivers/gpu/drm/i915/intel_lrc.c | 33 +

[Intel-gfx] [PATCH 1/5] drm/i915: Classify the engines in class + instance

ajdeczko <michal.wajdec...@intel.com> Signed-off-by: Oscar Mateo <oscar.ma...@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 8 drivers/gpu/drm/i915/intel_engine_cs.c | 14 ++ drivers/gpu/drm/i915/intel_ringbuffer.h | 4 3 files changed, 26 insertions(

[Intel-gfx] [PATCH 3/5] drm/i915: Generate the engine name based on the instance number

tko Ursulin <tvrtko.ursu...@intel.com> Reviewed-by: Michal Wajdeczko <michal.wajdec...@intel.com> Signed-off-by: Oscar Mateo <oscar.ma...@intel.com> --- drivers/gpu/drm/i915/intel_engine_cs.c | 5 +++-- drivers/gpu/drm/i915/intel_ringbuffer.h | 4 +++- drivers/gpu/drm/i9

[Intel-gfx] [PATCH 2/5] drm/i915: Use the same vfunc for BSD2 ring init

depends excusively on the engine class (a fact that we will use soon). v2: Commit message Cc: Paulo Zanoni <paulo.r.zan...@intel.com> Cc: Rodrigo Vivi <rodrigo.v...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com&

[Intel-gfx] [PATCH 4/5] drm/i915: Split the engine info table in two levels, using class + instance

> Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Reviewed-by: Michal Wajdeczko <michal.wajdec...@intel.com> Signed-off-by: Oscar Mateo <oscar.ma...@intel.com> Conflicts: drivers/gpu/drm/i915/intel_engine_cs.c --- drivers/gpu/drm/i915/intel_engine_cs.c | 65

[Intel-gfx] [PATCH 0/5] Classify the engines in class + instance (v5)

This refactoring helps simplify a few things here and there. Daniele Ceraolo Spurio (2): drm/i915: Classify the engines in class + instance drm/i915: Use the engine class to get the context size Oscar Mateo (3): drm/i915: Use the same vfunc for BSD2 ring init drm/i915: Generate

Re: [Intel-gfx] [PATCH 3/5] drm/i915: Generate the engine name based on the instance number

On 04/07/2017 10:11 AM, Chris Wilson wrote: On Fri, Apr 07, 2017 at 06:23:14PM +0200, Michal Wajdeczko wrote: On Fri, Apr 07, 2017 at 02:15:47AM -0700, Oscar Mateo wrote: Not really needed, but makes the next change a little bit more compact. v2: - Use zero-based numbering for engine

[Intel-gfx] [PATCH v5] drm/i915: Split the engine info table in two levels, using class + instance

: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Signed-off-by: Oscar Mateo <oscar.ma...@intel.com> --- drivers/gpu/drm/i915/intel_engine_cs.c | 65 ++ 1 file changed, 42 insertions(+), 23 delet

[Intel-gfx] [PATCH 2/5] drm/i915: Use the same vfunc for BSD2 ring init

depends excusively on the engine class (a fact that we will use soon). v2: Commit message Cc: Paulo Zanoni <paulo.r.zan...@intel.com> Cc: Rodrigo Vivi <rodrigo.v...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com&

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