Re: [Intel-gfx] [PATCH 1/3] drm/i915: Keep the ctx workarounds tightly packed

On 6/15/2018 1:59 AM, Chris Wilson wrote: For each platform, we have a few registers that rewritten with multiple values -- they are not part of a sequence, just different parts of a masked register set at different times (e.g. platform and gen workarounds). Consolidate these into a single

Re: [Intel-gfx] [RFC PATCH] drm/i915/guc: New interface files for GuC starting in Gen11

On 5/29/2018 7:59 AM, Michal Wajdeczko wrote: Hi, On Fri, 25 May 2018 23:59:35 +0200, Oscar Mateo wrote: GuC interface has been redesigned (or cleaned up, rather) starting with Gen11, as a stepping stone towards a new branching strategy that helps maintain backwards compatibility with

Re: [Intel-gfx] [PATCH v4 1/3] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

On 5/18/2018 3:39 PM, Yunwei Zhang wrote: WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO read into Slice/Subslice specific registers, MCR packet control register(0xFDC) needs to be programmed to point to any enabled slice/subslice pair. Otherwise, incorrect value

Re: [Intel-gfx] [PATCH v3 3/3] drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads

On 5/18/2018 3:41 PM, Yunwei Zhang wrote: L3Bank could be fused off in hardware for debug purpose, and it is possible that subslice is enabled while its corresponding L3Bank pairs are disabled. In such case, if MCR packet control register(0xFDC) is programed to point to a disabled bank pair, a

Re: [Intel-gfx] [PATCH v4 2/3] drm/i915/icl: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads

On 5/18/2018 3:40 PM, Yunwei Zhang wrote: WaProgramMgsrForCorrectSliceSpecificMmioReads applies for Icelake as well. References: HSD#1405586840, BSID#0575 v2: - GEN11 mask is different from its predecessors. (Oscar) - Better separate GEN10 and GEN11. (Oscar) Cc: Oscar Mateo

Re: [Intel-gfx] [PATCH] drm/i915/icl: Read the correct Gen11 interrupt registers

On 5/17/2018 3:59 PM, Paulo Zanoni wrote: Em Qui, 2018-05-17 às 10:04 -0700, Oscar Mateo Lozano escreveu: On 5/17/2018 9:55 AM, Michel Thierry wrote: On 5/16/2018 4:39 PM, Paulo Zanoni wrote: Em Qui, 2018-05-10 às 14:59 -0700, Oscar Mateo escreveu: Stop reading some now deprecated

Re: [Intel-gfx] [PATCH v2 1/3] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

On 5/18/2018 11:12 AM, Yunwei Zhang wrote: WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO read into Slice/Subslice specific registers, MCR packet control register(0xFDC) needs to be programmed to point to any enabled slice/subslice pair. Otherwise, incorrect value

Re: [Intel-gfx] [PATCH v2 2/3] drm/i915/icl: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads

On 5/18/2018 11:13 AM, Yunwei Zhang wrote: WaProgramMgsrForCorrectSliceSpecificMmioReads applies for Icelake as well. References: HSD#1405586840, BSID#0575 Cc: Oscar Mateo Cc: Michel Thierry Cc: Joonas Lahtinen

Re: [Intel-gfx] [PATCH] drm/i915/icl: Read the correct Gen11 interrupt registers

On 5/17/2018 9:55 AM, Michel Thierry wrote: On 5/16/2018 4:39 PM, Paulo Zanoni wrote: Em Qui, 2018-05-10 às 14:59 -0700, Oscar Mateo escreveu: Stop reading some now deprecated interrupt registers in both debugfs and error state. Instead, read the new equivalents in the Gen11 interrupt

Re: [Intel-gfx] [PATCH v2 00/22] Workarounds for Icelake

On 5/2/2018 1:40 PM, Chris Wilson wrote: Quoting Oscar Mateo (2018-05-02 21:33:59) List of GT workarounds for Icelake that we have been carrying in internal. (Is (checkpatch (((going to complain) (that this isn't)) (lisp? -Chris Maybe. Or maybe checkpatch has given

Re: [Intel-gfx] [PATCH 04/22] drm/i915/icl: WaL3BankAddressHashing

On 5/2/2018 3:23 AM, Mika Kuoppala wrote: Oscar Mateo writes: Revert to an L3 non-hash model, for performance reasons. v2: - Place the WA name above the actual change - Improve the register naming v3: - Rebased - Renamed to Wa_1604223664 v4: Rebased on

Re: [Intel-gfx] [PATCH v2 0/8] Enable HuC authentication in Icelake

Obviously the subject is wrong: it should say 0/5 instead of 0/8 (I copied the subject from the cover letter meant from internal, without realizing the number of patches was different). On 5/2/2018 12:03 PM, Oscar Mateo wrote: Bare minimum number of patches to get the GuC to authenticate the