Re: [Intel-gfx] [RFC 0/4] GPU/CPU timestamps correlation for relating OA samples with system events

On Thu, Dec 7, 2017 at 12:48 AM, Robert Bragg <rob...@sixbynine.org> wrote: > > at least from what I wrote back then it looks like I was seeing a drift of > a few milliseconds per second on SKL. I vaguely recall it being much worse > given the frequency constants we had for H

Re: [Intel-gfx] [RFC 0/4] GPU/CPU timestamps correlation for relating OA samples with system events

On Wed, Nov 15, 2017 at 12:13 PM, Sagar Arun Kamble < sagar.a.kam...@intel.com> wrote: > We can compute system time corresponding to GPU timestamp by taking a > reference point (CPU monotonic time, GPU timestamp) and then adding > delta time computed using timecounter/cyclecounter support in

Re: [Intel-gfx] [RFC 0/4] GPU/CPU timestamps correlation for relating OA samples with system events

On Tue, Dec 5, 2017 at 2:16 PM, Lionel Landwerlin < lionel.g.landwer...@intel.com> wrote: > Hey Sagar, > > Sorry for the delay looking into this series. > I've done some userspace/UI work in GPUTop to try to correlate perf > samples/tracepoints with i915 perf reports. > > I wanted to avoid having

[Intel-gfx] [PATCH v4 15/15] drm/i915/perf: remove perf.hook_lock

sed to be updated as part of a context pin hook. Signed-off-by: Robert Bragg <rob...@sixbynine.org> Reviewed-by: Matthew Auld <matthew.a...@intel.com> Acked-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 2 -- drivers/gpu/drm/

[Intel-gfx] [PATCH v4 14/15] drm/i915/perf: per-gen timebase for checking sample freq

(Ville) Initialize oa_sample_rate_hard_limit per-gen too (Lionel) Signed-off-by: Robert Bragg <rob...@sixbynine.org> Cc: Lionel Landwerlin <lionel.g.landwer...@linux.intel.com> Cc: Ville Syrjälä <ville.syrj...@linux.intel.com> Reviewed-by: Matthew Auld <matthew.a...@intel.

[Intel-gfx] [PATCH v4 12/15] drm/i915/perf: Add OA unit support for Gen 8+

captured via MI_REPORT_PERF_COUNT commands. As a result, for Gen8+, we always require the dev.i915.perf_stream_paranoid to be unset for any access to OA metrics if not root. Signed-off-by: Robert Bragg <rob...@sixbynine.org> Acked-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> ---

[Intel-gfx] [PATCH v4 11/15] drm/i915/perf: Add 'render basic' Gen8+ OA unit configs

xml > scripts/i915-perf-kernelgen.py $ make -C gputop-data -f Makefile.xml WHITELIST=RenderBasic v2: add newlines to debug messages + fix comment (Matthew Auld) Signed-off-by: Robert Bragg <rob...@sixbynine.org> Reviewed-by: Matthew Auld <matthew.a...@intel.com> Acked-by:

[Intel-gfx] [PATCH v4 10/15] drm/i915: expose _SUBSLICE_MASK GETPARM

Assuming a uniform mask across all slices, this enables userspace to determine the specific sub slices enabled. This information is required, for example, to be able to analyse some OA counter reports where the counter configuration depends on the HW sub slice configuration. Signed-off-by: Robert

[Intel-gfx] [PATCH v4 09/15] drm/i915: expose _SLICE_MASK GETPARM

Enables userspace to determine the number of slices enabled and also know what specific slices are enabled. This information is required, for example, to be able to analyse some OA counter reports where the counter configuration depends on the HW slice configuration. Signed-off-by: Robert Bragg

[Intel-gfx] [PATCH v4 08/15] drm/i915/perf: rate limit spurious oa report notice

that might be a large number of repeat notices. v2: (Chris) avoid inconsistent warning on throttle with printk_ratelimit() v3: (Matt) init and summarise with stream init/close not driver init/fini Signed-off-by: Robert Bragg <rob...@sixbynine.org> Reviewed-by: Matthew Auld <

[Intel-gfx] [PATCH v4 04/15] drm/i915/perf: no head/tail ref in gen7_oa_read

. Signed-off-by: Robert Bragg <rob...@sixbynine.org> Reviewed-by: Matthew Auld <matthew.a...@intel.com> --- drivers/gpu/drm/i915/i915_perf.c | 51 +++- 1 file changed, 19 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_perf.c b/dri

[Intel-gfx] [PATCH v4 07/15] drm/i915/perf: better pipeline aged/aging tail updates

callback (and then another to age). Signed-off-by: Robert Bragg <rob...@sixbynine.org> Reviewed-by: Matthew Auld <matthew.a...@intel.com> --- drivers/gpu/drm/i915/i915_perf.c | 41 ++-- 1 file changed, 23 insertions(+), 18 deletions(-) diff --git a/dri

[Intel-gfx] [PATCH v4 01/15] drm/i915/perf: fix gen7_append_oa_reports comment

If I'm going to complain about a back-to-front convention then the least I can do is not muddle the comment up too. Signed-off-by: Robert Bragg <rob...@sixbynine.org> Reviewed-by: Matthew Auld <matthew.a...@intel.com> --- drivers/gpu/drm/i915/i915_perf.c | 2 +- 1 file changed, 1 ins

[Intel-gfx] [PATCH v4 05/15] drm/i915/perf: improve tail race workaround

-by: Robert Bragg <rob...@sixbynine.org> Reviewed-by: Matthew Auld <matthew.a...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 60 - drivers/gpu/drm/i915/i915_perf.c | 277 ++- 2 files changed, 241 insertions(+), 96 deletions(-) diff --git a/dri

[Intel-gfx] [PATCH v4 06/15] drm/i915/perf: improve invalid OA format debug message

A minor improvement to debugging output Signed-off-by: Robert Bragg <rob...@sixbynine.org> Reviewed-by: Matthew Auld <matthew.a...@intel.com> --- drivers/gpu/drm/i915/i915_perf.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_perf

[Intel-gfx] [PATCH v4 02/15] drm/i915/perf: avoid poll, read, EAGAIN busy loops

have. Signed-off-by: Robert Bragg <rob...@sixbynine.org> Reviewed-by: Matthew Auld <matthew.a...@intel.com> --- drivers/gpu/drm/i915/i915_perf.c | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_

[Intel-gfx] [PATCH v4 03/15] drm/i915/perf: avoid read back of head register

towards re-working how the head and tail state is managed as part of an improved workaround for the tail register race condition. Signed-off-by: Robert Bragg <rob...@sixbynine.org> Reviewed-by: Matthew Auld <matthew.a...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 11 ++

[Intel-gfx] [PATCH v4 00/15] Enable OA unit for Gen 8 and 9 in i915 perf

change for gputop, mesa and igt. The series is longer just because I've included the gen7 prep patches (already reviewed) that I haven't landed yet but the gen8+ bits depend on. Regards, - Robert Robert Bragg (15): drm/i915/perf: fix gen7_append_oa_reports comment drm/i915/perf: avoid poll, read

Re: [Intel-gfx] [PATCH v2] drm/i915/perf: per-gen timebase for checking sample freq

On Wed, Apr 12, 2017 at 1:34 PM, Matthew Auld < matthew.william.a...@gmail.com> wrote: > On 5 April 2017 at 20:05, Robert Bragg <rob...@sixbynine.org> wrote: > > An oa_exponent_to_ns() utility and per-gen timebase constants where > were > > > recently removed wh

Re: [Intel-gfx] [PATCH v3 4/7] drm/i915/perf: Add OA unit support for Gen 8+

On Wed, Apr 12, 2017 at 12:33 PM, Matthew Auld <matthew.william.auld@gmail. com> wrote: > On 04/05, Robert Bragg wrote: > > Enables access to OA unit metrics for BDW, CHV, SKL and BXT which all > > share (more-or-less) the same OA unit design. > > > > Of particu

[Intel-gfx] [PATCH v2] drm/i915/perf: per-gen timebase for checking sample freq

(Ville) Initialize oa_sample_rate_hard_limit per-gen too (Lionel) Signed-off-by: Robert Bragg <rob...@sixbynine.org> Cc: Lionel Landwerlin <lionel.g.landwer...@linux.intel.com> Cc: Ville Syrjälä <ville.syrj...@linux.intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 1 + dr

Re: [Intel-gfx] [PATCH v3 6/7] drm/i915/perf: per-gen timebase for checking sample freq

On Wed, Apr 5, 2017 at 6:26 PM, Ville Syrjälä <ville.syrj...@linux.intel.com > wrote: > On Wed, Apr 05, 2017 at 06:17:36PM +0100, Lionel Landwerlin wrote: > > On 05/04/17 18:06, Ville Syrjälä wrote: > > > On Wed, Apr 05, 2017 at 05:23:19PM +0100, Robert Bragg wrote: >

[Intel-gfx] [PATCH v3 6/7] drm/i915/perf: per-gen timebase for checking sample freq

for Haswell. Signed-off-by: Robert Bragg <rob...@sixbynine.org> Cc: Lionel Landwerlin <lionel.g.landwer...@linux.intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_perf.c | 21 +++-- 2 files changed, 16 insertions(+), 6 deletions(-) diff --g

[Intel-gfx] [PATCH v3 4/7] drm/i915/perf: Add OA unit support for Gen 8+

captured via MI_REPORT_PERF_COUNT commands. As a result, for Gen8+, we always require the dev.i915.perf_stream_paranoid to be unset for any access to OA metrics if not root. Signed-off-by: Robert Bragg <rob...@sixbynine.org> --- drivers/gpu/drm/i915/i915_drv.h | 45 +- drivers/gpu/dr

[Intel-gfx] [PATCH v3 1/7] drm/i915: expose _SLICE_MASK GETPARM

Enables userspace to determine the number of slices enabled and also know what specific slices are enabled. This information is required, for example, to be able to analyse some OA counter reports where the counter configuration depends on the HW slice configuration. Signed-off-by: Robert Bragg

[Intel-gfx] [PATCH v3 7/7] drm/i915/perf: remove perf.hook_lock

sed to be updated as part of a context pin hook. Signed-off-by: Robert Bragg <rob...@sixbynine.org> --- drivers/gpu/drm/i915/i915_drv.h | 2 -- drivers/gpu/drm/i915/i915_perf.c | 32 ++-- 2 files changed, 10 insertions(+), 24 deletions(-) diff --git a/driver

[Intel-gfx] [PATCH v3 2/7] drm/i915: expose _SUBSLICE_MASK GETPARM

Assuming a uniform mask across all slices, this enables userspace to determine the specific sub slices enabled. This information is required, for example, to be able to analyse some OA counter reports where the counter configuration depends on the HW sub slice configuration. Signed-off-by: Robert

[Intel-gfx] [PATCH v3 3/7] drm/i915/perf: Add 'render basic' Gen8+ OA unit configs

xml > scripts/i915-perf-kernelgen.py $ make -C gputop-data -f Makefile.xml WHITELIST=RenderBasic v2: add newlines to debug messages + fix comment (Matthew Auld) Signed-off-by: Robert Bragg <rob...@sixbynine.org> Reviewed-by: Matthew Auld <matthew.a...@intel.com> --- drivers/gpu

[Intel-gfx] [PATCH v3 0/7] Enable OA unit for Gen 8 and 9 in i915 perf

Adds some R/Bs from from Matthew and some updates based on Matthew's feedback Notably the 'Add OA unit support for Gen 8+' patch now avoids duplicating lots of fiddly tail race workaround code by adding a vfunc for reading the OA tail pointer register. Robert Bragg (7): drm/i915: expose

[Intel-gfx] [PATCH v3] drm/i915/perf: rate limit spurious oa report notice

v3: (Matt) init and summarise with stream init/close not driver init/fini Signed-off-by: Robert Bragg <rob...@sixbynine.org> --- drivers/gpu/drm/i915/i915_drv.h | 6 ++ drivers/gpu/drm/i915/i915_perf.c | 28 +++- 2 files changed, 33 insertions(+), 1 deletion(-) d

Re: [Intel-gfx] [PATCH v2 5/5] drm/i915: Add more OA configs for BDW, CHV, SKL + BXT

On Mon, Mar 27, 2017 at 7:16 PM, Matthew Auld < matthew.william.a...@gmail.com> wrote: > On 03/23, Robert Bragg wrote: > > These are auto generated from an XML description of metric sets, > > currently maintained in gputop, ref: > > > > https://github.com/rib/g

Re: [Intel-gfx] [PATCH] drm/i915/perf: remove user triggerable warn

c688e1420d ("drm/i915: Add i915 perf infrastructure") > Signed-off-by: Matthew Auld <matthew.a...@intel.com> > Cc: Robert Bragg <rob...@sixbynine.org> > --- > drivers/gpu/drm/i915/i915_perf.c | 8 ++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > >

[Intel-gfx] [PATCH v2] drm/i915: Add 'render basic' Gen8+ OA unit configs

xml > scripts/i915-perf-kernelgen.py $ make -C gputop-data -f Makefile.xml WHITELIST=RenderBasic v2: add newlines to debug messages + fix comment (Matthew Auld) Signed-off-by: Robert Bragg <rob...@sixbynine.org> Reviewed-by: Matthew Auld <matthew.a...@intel.com> --- drivers/gpu

Re: [Intel-gfx] [PATCH v2 3/5] drm/i915: Add 'render basic' Gen8+ OA unit configs

On Fri, Mar 24, 2017 at 12:52 AM, Robert Bragg <rob...@sixbynine.org> wrote: > On Thu, Mar 23, 2017 at 8:48 PM, Matthew Auld > <matthew.william.a...@gmail.com> wrote: >> On 23 March 2017 at 20:18, Robert Bragg <rob...@sixbynine.org> wrote: >>> Adds a s

Re: [Intel-gfx] [PATCH v2 3/5] drm/i915: Add 'render basic' Gen8+ OA unit configs

On Thu, Mar 23, 2017 at 8:48 PM, Matthew Auld <matthew.william.a...@gmail.com> wrote: > On 23 March 2017 at 20:18, Robert Bragg <rob...@sixbynine.org> wrote: >> Adds a static OA unit, MUX, B Counter + Flex EU configurations for basic >> render metrics on Broadwell, Cher

[Intel-gfx] [PATCH v2 4/5] drm/i915: Add OA unit support for Gen 8+

captured via MI_REPORT_PERF_COUNT commands. As a result, for Gen8+, we always require the dev.i915.perf_stream_paranoid to be unset for any access to OA metrics if not root. Signed-off-by: Robert Bragg <rob...@sixbynine.org> --- drivers/gpu/drm/i915/i915_drv.h | 29 +- drivers/gpu/dr

[Intel-gfx] [PATCH v2 3/5] drm/i915: Add 'render basic' Gen8+ OA unit configs

xml > scripts/i915-perf-kernelgen.py $ make -C gputop-data -f Makefile.xml WHITELIST=RenderBasic Signed-off-by: Robert Bragg <rob...@sixbynine.org> --- drivers/gpu/drm/i915/Makefile | 8 +- drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/i915_oa_bd

[Intel-gfx] [PATCH v2 2/5] drm/i915: expose _SUBSLICE_MASK GETPARM

Assuming a uniform mask across all slices, this enables userspace to determine the specific sub slices enabled. This information is required, for example, to be able to analyse some OA counter reports where the counter configuration depends on the HW sub slice configuration. Signed-off-by: Robert

[Intel-gfx] [PATCH v2 1/5] drm/i915: expose _SLICE_MASK GETPARM

Enables userspace to determine the number of slices enabled and also know what specific slices are enabled. This information is required, for example, to be able to analyse some OA counter reports where the counter configuration depends on the HW slice configuration. Signed-off-by: Robert Bragg

[Intel-gfx] [PATCH v2 0/5] Enable OA unit for Gen 8 and 9 in i915 perf

: https://github.com/rib/linux In case anyone wants to take a look at the IGT tests so far they can be found here: https://github.com/rib/intel-gpu-tools/commits/wip/rib/i915-perf-tests Regards, - Robert Robert Bragg (5): drm/i915: expose _SLICE_MASK GETPARM drm/i915: expose _SUBSLICE_MASK

[Intel-gfx] [PATCH v2] drm/i915/perf: rate limit spurious oa report notice

that might be a large number of repeat notices. v2: (Chris) avoid inconsistent warning on throttle with printk_ratelimit() Signed-off-by: Robert Bragg <rob...@sixbynine.org> --- drivers/gpu/drm/i915/i915_drv.h | 6 ++ drivers/gpu/drm/i915/i915_perf.c | 17 - 2

Re: [Intel-gfx] [PATCH 3/6] drm/i915: Add uncore mmio api for per-context registers

On Thu, Feb 23, 2017 at 3:35 PM, Chris Wilson <ch...@chris-wilson.co.uk> wrote: > On Wed, Feb 22, 2017 at 04:36:31PM +0000, Robert Bragg wrote: >> Since the exponent for periodic OA counter sampling is maintained in a >> per-context register while we want to treat it as if it

Re: [Intel-gfx] [PATCH 6/6] drm/i915: Add more OA configs for BDW, CHV, SKL + BXT

On Wed, Mar 1, 2017 at 1:00 PM, Matthew Auld <matthew.william.a...@gmail.com> wrote: > On 02/22, Robert Bragg wrote: >> These are auto generated from an XML description of metric sets, >> currently maintained in gputop, ref: >> >> https://github.com/rib/

Re: [Intel-gfx] [PATCH 3/3] drm/i915/perf: rate limit spurious oa report notice

On Tue, Feb 28, 2017 at 1:33 PM, Chris Wilson <ch...@chris-wilson.co.uk> wrote: > On Tue, Feb 28, 2017 at 01:28:13PM +, Matthew Auld wrote: >> On 22 February 2017 at 15:25, Robert Bragg <rob...@sixbynine.org> wrote: >> > This change is pre-emptively aiming to avo

Re: [Intel-gfx] [PATCH 2/8] drm/i915: Expose OA sample source to userspace

nsition reasons for the OA unit writing a report. The reason field is overloaded as the RPT_ID field for MI_RPC reports so we need our own way of tracking the difference. > > Signed-off-by: Sourab Gupta <sourab.gu...@intel.com> > Signed-off-by: Robert Bragg <rob...@sixb

Re: [Intel-gfx] [PATCH 0/8] Collect command stream based OA reports using i915 perf

On Thu, Mar 16, 2017 at 6:14 AM, wrote: > From: Sourab Gupta > > This series adds framework for collection of OA reports associated with the > render command stream, which are collected around batchbuffer boundaries. > > Refloating the series

[Intel-gfx] [PATCH 2/6] drm/i915: expose _SUBSLICE_MASK GETPARM

Assuming a uniform mask across all slices, this enables userspace to determine the specific sub slices enabled. This information is required, for example, to be able to analyse some OA counter reports where the counter configuration depends on the HW sub slice configuration. Signed-off-by: Robert

[Intel-gfx] [PATCH 0/6] Enable OA unit for Gen 8 and 9 in i915 perf

: these patches are based on the patches I sent out to update the tail pointer race workaround for Haswell in i915 perf. Regards, - Robert Robert Bragg (6): drm/i915: expose _SLICE_MASK GETPARM drm/i915: expose _SUBSLICE_MASK GETPARM drm/i915: Add uncore mmio api for per-context registers drm/i915: Add

[Intel-gfx] [PATCH 1/6] drm/i915: expose _SLICE_MASK GETPARM

Enables userspace to determine the number of slices enabled and also know what specific slices are enabled. This information is required, for example, to be able to analyse some OA counter reports where the counter configuration depends on the HW slice configuration. Signed-off-by: Robert Bragg

[Intel-gfx] [PATCH 3/6] drm/i915: Add uncore mmio api for per-context registers

in this case and this adds a utility api to encapsulate what's required. Signed-off-by: Robert Bragg <rob...@sixbynine.org> --- drivers/gpu/drm/i915/i915_drv.h | 4 ++ drivers/gpu/drm/i915/i915_reg.h | 3 ++ drivers/gpu/drm/i915/intel_uncore.c | 73 ++

[Intel-gfx] [PATCH 4/6] drm/i915: Add 'render basic' Gen8+ OA unit configs

xml > scripts/i915-perf-kernelgen.py $ make -C gputop-data -f Makefile.xml WHITELIST=RenderBasic Signed-off-by: Robert Bragg <rob...@sixbynine.org> --- drivers/gpu/drm/i915/Makefile | 8 +- drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/i915_oa_bd

[Intel-gfx] [PATCH 5/6] drm/i915: Add OA unit support for Gen 8+

captured via MI_REPORT_PERF_COUNT commands. As a result, for Gen8+, we always require the dev.i915.perf_stream_paranoid to be unset for any access to OA metrics if not root. Signed-off-by: Robert Bragg <rob...@sixbynine.org> --- drivers/gpu/drm/i915/i915_drv.h | 14 + drivers/gpu/dr

[Intel-gfx] [PATCH 2/3] drm/i915/perf: better pipeline aged/aging tail updates

callback (and then another to age). Signed-off-by: Robert Bragg <rob...@sixbynine.org> --- drivers/gpu/drm/i915/i915_perf.c | 41 ++-- 1 file changed, 23 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_

[Intel-gfx] [PATCH 1/3] drm/i915/perf: improve invalid OA format debug message

A minor improvement to debugging output Signed-off-by: Robert Bragg <rob...@sixbynine.org> --- drivers/gpu/drm/i915/i915_perf.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index 383b57

[Intel-gfx] [PATCH 3/3] drm/i915/perf: rate limit spurious oa report notice

that might be a large number of repeat notices. Signed-off-by: Robert Bragg <rob...@sixbynine.org> --- drivers/gpu/drm/i915/i915_perf.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index d04eba

[Intel-gfx] [PATCH 0/3] Some minor i915-perf prep changes

A small set of i915 perf changes that could ideally land before the gen8+ patches I hope to send out soon. These are based on top of the gen7 tail pointer race workaround changes that were sent out recently. Robert Bragg (3): drm/i915/perf: improve invalid OA format debug message drm/i915

Re: [Intel-gfx] [PATCH v2] drm/i915: fix for WaDisableDopClockGating:bdw

On Mon, Feb 13, 2017 at 2:28 PM, Ville Syrjälä <ville.syrj...@linux.intel.com> wrote: > On Sun, Feb 12, 2017 at 01:32:52PM +0000, Robert Bragg wrote: >> This workaround for BDW was incomplete as it also requires EUTC clock >> gating to be disabled via UCGCTL1. >> >

[Intel-gfx] [PATCH v2 3/5] drm/i915/perf: avoid read back of head register

towards re-working how the head and tail state is managed as part of an improved workaround for the tail register race condition. Signed-off-by: Robert Bragg <rob...@sixbynine.org> Reviewed-by: Matthew Auld <matthew.a...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 11 ++

[Intel-gfx] [PATCH v2 0/5] drm/i915/perf: Improve handling of OA tail race

Folds in Matthew Auld's feedback and adds his RBs. Robert Bragg (5): drm/i915/perf: fix gen7_append_oa_reports comment drm/i915/perf: avoid poll, read, EAGAIN busy loops drm/i915/perf: avoid read back of head register drm/i915/perf: no head/tail ref in gen7_oa_read drm/i915/perf

[Intel-gfx] [PATCH v2 4/5] drm/i915/perf: no head/tail ref in gen7_oa_read

. Signed-off-by: Robert Bragg <rob...@sixbynine.org> Reviewed-by: Matthew Auld <matthew.a...@intel.com> --- drivers/gpu/drm/i915/i915_perf.c | 51 +++- 1 file changed, 19 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_perf.c b/dri

[Intel-gfx] [PATCH v2 5/5] drm/i915/perf: improve tail race workaround

-by: Robert Bragg <rob...@sixbynine.org> Reviewed-by: Matthew Auld <matthew.a...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 60 - drivers/gpu/drm/i915/i915_perf.c | 277 ++- 2 files changed, 241 insertions(+), 96 deletions(-) diff --git a/dri

[Intel-gfx] [PATCH v2 2/5] drm/i915/perf: avoid poll, read, EAGAIN busy loops

have. Signed-off-by: Robert Bragg <rob...@sixbynine.org> Reviewed-by: Matthew Auld <matthew.a...@intel.com> --- drivers/gpu/drm/i915/i915_perf.c | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_

[Intel-gfx] [PATCH v2 1/5] drm/i915/perf: fix gen7_append_oa_reports comment

If I'm going to complain about a back-to-front convention then the least I can do is not muddle the comment up too. Signed-off-by: Robert Bragg <rob...@sixbynine.org> Reviewed-by: Matthew Auld <matthew.a...@intel.com> --- drivers/gpu/drm/i915/i915_perf.c | 2 +- 1 file changed, 1 ins

[Intel-gfx] [PATCH v2] drm/i915: fix for WaDisableDopClockGating:bdw

This workaround for BDW was incomplete as it also requires EUTC clock gating to be disabled via UCGCTL1. v2: read modify write UCGTL1 in broadwell_init_clock_gating (Ville) Signed-off-by: Robert Bragg <rob...@sixbynine.org> Cc: Ville Syrjälä <ville.syrj...@linux.intel.com> --- dri

Re: [Intel-gfx] [PATCH] drm/i915: fix for WaDisableDopClockGating:bdw

On Wed, Feb 8, 2017 at 6:33 PM, Ville Syrjälä <ville.syrj...@linux.intel.com> wrote: > On Wed, Feb 08, 2017 at 06:10:31PM +0000, Robert Bragg wrote: >> This workaround for BDW was incomplete as it also requires EUTC clock >> gating to be disabled via UCGCTL1. > > IIRC t

[Intel-gfx] [PATCH] drm/i915: fix for WaDisableDopClockGating:bdw

This workaround for BDW was incomplete as it also requires EUTC clock gating to be disabled via UCGCTL1. Signed-off-by: Robert Bragg <rob...@sixbynine.org> --- drivers/gpu/drm/i915/intel_ringbuffer.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/intel_ringbuffe

[Intel-gfx] [PATCH v2 2/5] drm/i915/perf: avoid poll, read, EAGAIN busy loops

have. Signed-off-by: Robert Bragg <rob...@sixbynine.org> Reviewed-by: Matthew Auld <matthew.a...@intel.com> --- drivers/gpu/drm/i915/i915_perf.c | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_

[Intel-gfx] [PATCH v2 3/5] drm/i915/perf: avoid read back of head register

towards re-working how the head and tail state is managed as part of an improved workaround for the tail register race condition. Signed-off-by: Robert Bragg <rob...@sixbynine.org> Reviewed-by: Matthew Auld <matthew.a...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 11 ++

[Intel-gfx] [PATCH v2 5/5] drm/i915/perf: improve tail race workaround

-by: Robert Bragg <rob...@sixbynine.org> Reviewed-by: Matthew Auld <matthew.a...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 60 - drivers/gpu/drm/i915/i915_perf.c | 277 ++- 2 files changed, 241 insertions(+), 96 deletions(-) diff --git a/dri

[Intel-gfx] [PATCH v2 4/5] drm/i915/perf: no head/tail ref in gen7_oa_read

. Signed-off-by: Robert Bragg <rob...@sixbynine.org> Reviewed-by: Matthew Auld <matthew.a...@intel.com> --- drivers/gpu/drm/i915/i915_perf.c | 51 +++- 1 file changed, 19 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_perf.c b/dri

[Intel-gfx] [PATCH v2 1/5] drm/i915/perf: fix gen7_append_oa_reports comment

If I'm going to complain about a back-to-front convention then the least I can do is not muddle the comment up too. Signed-off-by: Robert Bragg <rob...@sixbynine.org> Reviewed-by: Matthew Auld <matthew.a...@intel.com> --- drivers/gpu/drm/i915/i915_perf.c | 2 +- 1 file changed, 1 ins

[Intel-gfx] [PATCH v2 0/5] drm/i915/perf: Improve handling of OA tail race

Folds in Matthew Auld's feedback; thanks. Robert Bragg (5): drm/i915/perf: fix gen7_append_oa_reports comment drm/i915/perf: avoid poll, read, EAGAIN busy loops drm/i915/perf: avoid read back of head register drm/i915/perf: no head/tail ref in gen7_oa_read drm/i915/perf: improve tail

[Intel-gfx] [PATCH 3/5] drm/i915/perf: avoid read back of head register

towards re-working how the head and tail state is managed as part of an improved workaround for the tail register race condition. Signed-off-by: Robert Bragg <rob...@sixbynine.org> --- drivers/gpu/drm/i915/i915_drv.h | 11 ++ drivers/gpu/drm/i915/i915_perf.

[Intel-gfx] [PATCH 4/5] drm/i915/perf: no head/tail ref in gen7_oa_read

. Signed-off-by: Robert Bragg <rob...@sixbynine.org> --- drivers/gpu/drm/i915/i915_perf.c | 51 +++- 1 file changed, 19 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index e85583d0bcff..4b3bab

[Intel-gfx] [PATCH 2/5] drm/i915/perf: avoid poll, read, EAGAIN busy loops

have. Signed-off-by: Robert Bragg <rob...@sixbynine.org> --- drivers/gpu/drm/i915/i915_perf.c | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index b0eec762b9b4..4bb7333dac45 100644 --- a/drive

[Intel-gfx] [PATCH 1/5] drm/i915/perf: fix gen7_append_oa_reports comment

If I'm going to complain about a back-to-front convention then the least I can do is not muddle the comment up too. Signed-off-by: Robert Bragg <rob...@sixbynine.org> --- drivers/gpu/drm/i915/i915_perf.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/dr

[Intel-gfx] [PATCH 5/5] drm/i915/perf: improve tail race workaround

-by: Robert Bragg <rob...@sixbynine.org> --- drivers/gpu/drm/i915/i915_drv.h | 59 - drivers/gpu/drm/i915/i915_perf.c | 275 ++- 2 files changed, 241 insertions(+), 93 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915

[Intel-gfx] [PATCH 0/5] drm/i915/perf: Improve handling of OA tail race

for gen8+ too. Robert Bragg (5): drm/i915/perf: fix gen7_append_oa_reports comment drm/i915/perf: avoid poll, read, EAGAIN busy loops drm/i915/perf: avoid read back of head register drm/i915/perf: no head/tail ref in gen7_oa_read drm/i915/perf: improve tail race workaround drivers/gpu/drm/i915

[Intel-gfx] [PATCH igt] igt/perf: improve robustness of polling/blocking tests

sts now both run for a lot longer (1000 x tick duration, or typically 10 seconds each) so that a single tick represents a much smaller proportion of the total duration (0.1%) and the stime thresholds are now set at 1% of the total duration. Signed-off-by: Robert Bragg <rob...@sixbynine.org> -

Re: [Intel-gfx] [PATCH] drm/i915/perf: More documentation hooked to i915.rst

On Thu, Dec 8, 2016 at 3:53 PM, Daniel Vetter <dan...@ffwll.ch> wrote: > On Wed, Dec 07, 2016 at 09:40:33PM +0000, Robert Bragg wrote: >> This adds a 'Perf' section to i915.rst with the following sub sections: >> - Overview >> - Comparison with Core Perf >> - i

Re: [Intel-gfx] [RFC v2] drm: Enable dynamic debug for DRM_[DEV]_DEBUG*

On Thu, Dec 8, 2016 at 12:17 AM, Daniel Vetter <dan...@ffwll.ch> wrote: > > On Wed, Dec 07, 2016 at 06:35:29PM +0000, Robert Bragg wrote: > > This is still missing corresponding documentation changes, and I haven't > > moved anything to drm_print.h yet, as suggested. > &

[Intel-gfx] [PATCH] drm/i915/perf: More documentation hooked to i915.rst

docs + other fixups (Matthew Auld) Signed-off-by: Robert Bragg <rob...@sixbynine.org> Reviewed-by: Matthew Auld <matthew.a...@intel.com> Cc: Daniel Vetter <daniel.vet...@ffwll.ch> --- Documentation/gpu/i915.rst | 91 + drivers/gpu/drm/i915/i915_drv.h | 151 +

Re: [Intel-gfx] [RFC] drm: Enable dynamic debug for DRM_[DEV]_DEBUG*

On Mon, Dec 5, 2016 at 4:31 PM, Daniel Vetter <dan...@ffwll.ch> wrote: > On Mon, Dec 05, 2016 at 11:24:44AM +0000, Robert Bragg wrote: > > Forgot to send to dri-devel when I first sent this out... > > > > The few times I've looked at using DRM_DEBUG messages, I haven't

[Intel-gfx] [RFC v2] drm: Enable dynamic debug for DRM_[DEV]_DEBUG*

und" Only single conditional call per message (macros expand to less code) Uses __dynamic_pr_debug/dev_dbg for dynamic formatting features Use module name for msg prefix like [drm] or [i915] Signed-off-by: Robert Bragg <rob...@sixbynine.org> Cc: dri-de...@lists.freedesktop.org Cc: Dan

Re: [Intel-gfx] [RFC 0/5] DRM logging tidy

On Tue, Dec 6, 2016 at 6:57 PM, Tvrtko Ursulin wrote: > From: Tvrtko Ursulin > > I wasn't here at the beginnings of DRM so I might have gotten this wrong, > however the existance of DRM_NAME suggested to me that the intention was to > allow

[Intel-gfx] [RFC] drm: Enable dynamic debug for DRM_[DEV]_DEBUG*

n this case. Previously some of non-dev drm debug macros were defined in terms of passing NULL to a dev version but that's avoided now due to this difference. Signed-off-by: Robert Bragg <rob...@sixbynine.org> Cc: dri-de...@lists.freedesktop.org Cc: Daniel Vetter <daniel.vet...@ffwll.ch>

[Intel-gfx] [PATCH] drm/i915/perf: More documentation hooked to i915.rst

docs + other fixups (Matthew Auld) Signed-off-by: Robert Bragg <rob...@sixbynine.org> Cc: Daniel Vetter <daniel.vet...@ffwll.ch> Cc: Matthew Auld <matthew.a...@intel.com> --- Documentation/gpu/i915.rst | 91 + drivers/gpu/drm/i915/i915_drv.h | 151 +++--

Re: [Intel-gfx] [PATCH] drm/i915/perf: More documentation hooked to i915.rst

On Thu, Dec 1, 2016 at 12:12 PM, Jani Nikula <jani.nik...@linux.intel.com> wrote: > On Wed, 30 Nov 2016, Daniel Vetter <dan...@ffwll.ch> wrote: > > On Tue, Nov 29, 2016 at 05:00:55PM +, Robert Bragg wrote: > >> +.. kernel-doc:: drivers/gpu/drm/i915/i

Re: [Intel-gfx] [PATCH] drm/i915/perf: More documentation hooked to i915.rst

On Nov 30, 2016 19:41, "Daniel Vetter" <dan...@ffwll.ch> wrote: > > On Tue, Nov 29, 2016 at 05:00:55PM +, Robert Bragg wrote: > > This adds a 'Perf' section to i915.rst with the following sub sections: > > - Overview > > - Comparison with Core Perf &

Re: [Intel-gfx] [PATCH] drm/i915/perf: use DRM_DEBUG for userspace issues

On Fri, Dec 2, 2016 at 8:35 AM, Daniel Vetter <dan...@ffwll.ch> wrote: > On Thu, Dec 01, 2016 at 05:21:52PM +0000, Robert Bragg wrote: > > Avoid using DRM_ERROR for conditions userspace can trigger with a bad > > config when opening a stream or from not reading data in

[Intel-gfx] [PATCH] drm/i915/perf: use DRM_DEBUG for userspace issues

is only a heuristic it's possible we might see this from time to time. Signed-off-by: Robert Bragg <rob...@sixbynine.org: Cc: Daniel Vetter <daniel.vet...@ffwll.ch> fix i915_perf dbg messages --- drivers/gpu/drm/i915/i915_perf.c | 42 1 file ch

[Intel-gfx] [RFC] drm: Enable dynamic debug for DRM_[DEV]_DEBUG*

sing NULL to a dev version but that's avoided now due to this difference. I haven't so far looked to see what affect these have on linked object sizes. Signed-off-by: Robert Bragg <rob...@sixbynine.org> Cc: Chris Wilson <ch...@chris-wilson.co.uk> --- drivers/gpu/drm/drm_drv.c | 47

[Intel-gfx] [PATCH] drm/i915/perf: More documentation hooked to i915.rst

This adds a 'Perf' section to i915.rst with the following sub sections: - Overview - Comparison with Core Perf - i915 Driver Entry Points - i915 Perf Stream - i915 Perf Observation Architecture Stream - All i915 Perf Internals Signed-off-by: Robert Bragg <rob...@sixbynine.org> Cc: Daniel

[Intel-gfx] [PATCH] drm/i915/perf: use DRM_INFO for userspace issues

. Signed-off-by: Robert Bragg <rob...@sixbynine.org: Cc: Daniel Vetter <daniel.vet...@ffwll.ch> --- drivers/gpu/drm/i915/i915_perf.c | 46 1 file changed, 23 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu

Re: [Intel-gfx] [PATCH v3] drm/i915/perf: Wrap 64bit divides in do_div()

y u64/u32, we need a u32/u64! > v3: div_u64() == u64/u32, div64_u64() == u64/u64 > > Reported-by: kbuild test robot <fengguang...@intel.com> > Fixes: d79651522e89 ("drm/i915: Enable i915 perf stream for Haswell OA > unit") > Signed-off-by: Chris Wilson

[Intel-gfx] [PATCH igt] igt/gem_exec_parse: generalise test_lri + debug info

ing tested. Signed-off-by: Robert Bragg <rob...@sixbynine.org> Cc: Chris Wilson <ch...@chris-wilson.co.uk> --- tests/gem_exec_parse.c | 102 + 1 file changed, 52 insertions(+), 50 deletions(-) diff --git a/tests/gem_exec_parse.c b/tests/

Re: [Intel-gfx] [PATCH] drm/i915/perf: Wrap 64bit divides in do_div()

On Nov 22, 2016 23:49, "Chris Wilson" <ch...@chris-wilson.co.uk> wrote: > > On Tue, Nov 22, 2016 at 11:32:38PM +, Robert Bragg wrote: > >Thanks for sending out. It looked good to me, but testing shows a 'divide > >error'. > > > >I ha

Re: [Intel-gfx] [PATCH] drm/i915/perf: Wrap 64bit divides in do_div()

stream for Haswell OA > unit") > Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> > Cc: Robert Bragg <rob...@sixbynine.org> > --- > drivers/gpu/drm/i915/i915_perf.c | 17 +++-- > 1 file changed, 11 insertions(+), 6 deletions(-) > > diff --g

[Intel-gfx] [PATCH igt] igt/gem_exec_parse: test_lri check init + add debug msg

now also double checks that the initial intel_register_write() takes before issuing the LRI. Signed-off-by: Robert Bragg <rob...@sixbynine.org> --- tests/gem_exec_parse.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/tests/gem_exec_parse.c b/tests/gem_exec_parse.c index cc2103a

Re: [Intel-gfx] [PATCH v2] drm/i915: don't whitelist oacontrol in cmd parser

On Tue, Nov 22, 2016 at 1:34 PM, Daniel Vetter <dan...@ffwll.ch> wrote: > On Tue, Nov 08, 2016 at 12:51:48PM +0000, Robert Bragg wrote: > > This v2 patch bumps the command parser version so it can be referenced in > > corresponding i-g-t gem_exec_parse changes. > > >

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