[Intel-gfx] [PATCH 1/8] drm/i915: Add i915 perf infrastructure

a stream will return an error. Signed-off-by: Robert Bragg <rob...@sixbynine.org> --- drivers/gpu/drm/i915/Makefile| 3 + drivers/gpu/drm/i915/i915_dma.c | 7 + drivers/gpu/drm/i915/i915_drv.h | 88 drivers/gpu/drm/i915/i915_perf.c

[Intel-gfx] [PATCH 7/8] drm/i915: add oa_event_min_timer_exponent sysctl

The minimal sampling period is now configurable via a dev.i915.oa_min_timer_exponent sysctl parameter. Following the precedent set by perf, the default is the minimum that won't (on its own) exceed the default kernel.perf_event_max_sample_rate default of 10 samples/s. Signed-off-by: Robert

[Intel-gfx] [PATCH 6/8] drm/i915: Add dev.i915.perf_event_paranoid sysctl option

Consistent with the kernel.perf_event_paranoid sysctl option that can allow non-root users to access system wide cpu metrics, this can optionally allow non-root users to access system wide OA counter metrics from Gen graphics hardware. Signed-off-by: Robert Bragg <rob...@sixbynine.

[Intel-gfx] [PATCH 4/8] drm/i915: Add i915 perf event for Haswell OA unit

Gen graphics hardware can be set up to periodically write snapshots of performance counters into a circular buffer via its Observation Architecture and this patch exposes that capability to userspace via the i915 perf interface. Cc: Chris Wilson <ch...@chris-wilson.co.uk> Signed-off-by:

[Intel-gfx] [PATCH 5/8] drm/i915: advertise available metrics via sysfs

. The is a globally unique ID for a specific OA unit configuration that can be reliably used as a key to lookup corresponding counter meta data and normalization equations. Signed-off-by: Robert Bragg <rob...@sixbynine.org> --- drivers/gpu/drm/i915/i915_drv.h| 2 ++ drivers/gpu/dr

[Intel-gfx] [PATCH 3/8] drm/i915: Add 'render basic' Haswell OA unit config

Adds a static OA unit, MUX + B Counter configuration for basic render metrics on Haswell. This is autogenerated from an internal XML description of metric sets. Signed-off-by: Robert Bragg <rob...@sixbynine.org> --- drivers/gpu/drm/i915/Makefile | 3 +- drivers/gpu/drm/i915/i915

[Intel-gfx] [PATCH 2/8] drm/i915: rename OACONTROL GEN7_OACONTROL

OACONTROL changes quite a bit for gen8, with some bits split out into a per-context OACTXCONTROL register. Rename now before add more gen7 OA registers Signed-off-by: Robert Bragg <rob...@sixbynine.org> --- drivers/gpu/drm/i915/i915_cmd_parser.c | 4 ++-- drivers/gpu/drm/i915/i915

[Intel-gfx] [PATCH 0/8] Enable Gen 7 Observation Architecture

-auld/linux/tree/wip/matt-auld/oa-4.4-dynamic-testing Regards, - Robert [1] https://github.com/rib/gputop https://github.com/rib/gputop/wiki/Build-Instructions Robert Bragg (8): drm/i915: Add i915 perf infrastructure drm/i915: rename OACONTROL GEN7_OACONTROL drm/i915: Add 'render basic

Re: [Intel-gfx] [PATCH 0/7] drm/i915: read out slice/subslice masks

s series; it just seems relevant to mention. Reviewed-by: Robert Bragg <rob...@sixbynine.org> Regards, - Robert On Wed, Oct 21, 2015 at 4:40 PM, Imre Deak <imre.d...@intel.com> wrote: > The per-slice/subslice INSTDONE patchset from Ben [1] will need the > subslice/slice masks in addi

Re: [Intel-gfx] [RFC 0/6] Non perf based Gen Graphics OA unit driver

On Fri, Oct 16, 2015 at 10:43 AM, Peter Zijlstra <pet...@infradead.org> wrote: > On Tue, Sep 29, 2015 at 03:39:03PM +0100, Robert Bragg wrote: >> - We're bridging two complex architectures >> >> To review this work I think it will be relevant to have a good >>

Re: [Intel-gfx] [RFC 0/6] Non perf based Gen Graphics OA unit driver

On Fri, Oct 16, 2015 at 11:33 AM, Peter Zijlstra wrote: > On Fri, Oct 16, 2015 at 12:02:28PM +0200, Ingo Molnar wrote: >> >> * Peter Zijlstra wrote: >> >> > > - We may be making some technical compromises a.t.m for the sake of >> > > using perf. >> >

Re: [Intel-gfx] [RFC 0/6] Non perf based Gen Graphics OA unit driver

On Wed, Sep 30, 2015 at 9:30 AM, Chris Wilson <ch...@chris-wilson.co.uk> wrote: > On Tue, Sep 29, 2015 at 03:39:03PM +0100, Robert Bragg wrote: > > Updating Mesa and GPU Top to experiment with this was straightforward > > given the similarity to the perf interface.

[Intel-gfx] [RFC 5/6] drm/i915: Add dev.i915.perf_event_paranoid sysctl option

Consistent with the kernel.perf_event_paranoid sysctl option that can allow non-root users to access system wide cpu metrics, this can optionally allow non-root users to access system wide OA counter metrics from Gen graphics hardware. Signed-off-by: Robert Bragg <rob...@sixbynine.

[Intel-gfx] [RFC 4/6] drm/i915: Add i915 perf event for Haswell OA unit

Gen graphics hardware can be set up to periodically write snapshots of performance counters into a circular buffer via its Observation Architecture and this patch exposes that capability to userspace via the i915 perf interface. Cc: Chris Wilson <ch...@chris-wilson.co.uk> Signed-off-by:

[Intel-gfx] [RFC 3/6] drm/i915: Add static '3D' Haswell OA unit config

Adds a static OA unit, MUX + B Counter configuration for basic '3D' metrics on Haswell. This is autogenerated from an internal XML description of metric sets. Signed-off-by: Robert Bragg <rob...@sixbynine.org> --- drivers/gpu/drm/i915/Makefile | 3 +- drivers/gpu/drm/i915/i915

[Intel-gfx] [RFC 6/6] drm/i915: add oa_event_min_timer_exponent sysctl

-by: Robert Bragg <rob...@sixbynine.org> --- drivers/gpu/drm/i915/i915_perf.c | 37 - 1 file changed, 28 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index ab82857..5ef7d92 100644 --- a/drivers/g

[Intel-gfx] [RFC 1/6] drm/i915: Add i915 perf infrastructure

types are supported yet so perf_event_open can currently only get as far as returning EINVAL for an unknown event type. Signed-off-by: Robert Bragg <rob...@sixbynine.org> --- drivers/gpu/drm/i915/Makefile| 3 + drivers/gpu/drm/i915/i915_dma.c | 7 + drivers/gpu/drm/i915/i915_drv.h

[Intel-gfx] [RFC 0/6] Non perf based Gen Graphics OA unit driver

Robert Bragg (6): drm/i915: Add i915 perf infrastructure drm/i915: rename OACONTROL GEN7_OACONTROL drm/i915: Add static '3D' Haswell OA unit config drm/i915: Add i915 perf event for Haswell OA unit drm/i915: Add dev.i915.perf_event_paranoid sysctl option drm/i915: add

[Intel-gfx] [RFC 2/6] drm/i915: rename OACONTROL GEN7_OACONTROL

OACONTROL changes quite a bit for gen8, with some bits split out into a per-context OACTXCONTROL register Signed-off-by: Robert Bragg <rob...@sixbynine.org> --- drivers/gpu/drm/i915/i915_cmd_parser.c | 4 ++-- drivers/gpu/drm/i915/i915_reg.h| 2 +- 2 files changed, 3 insertions

Re: [Intel-gfx] [RFC 7/8] drm/i915: Add support for forwarding execbuffer tags in timestamp sample metadata

On Wed, Aug 5, 2015 at 10:29 AM, Daniel Vetter dan...@ffwll.ch wrote: On Wed, Aug 05, 2015 at 10:17:55AM +0100, Chris Wilson wrote: On Wed, Aug 05, 2015 at 11:25:43AM +0530, sourab.gu...@intel.com wrote: @@ -555,10 +558,12 @@ static void forward_one_gen_pmu_sample(struct drm_i915_private

Re: [Intel-gfx] [RFC 7/8] drm/i915: Add support for forwarding execbuffer tags in timestamp sample metadata

On Wed, Aug 5, 2015 at 4:25 PM, Daniel Vetter dan...@ffwll.ch wrote: On Wed, Aug 05, 2015 at 02:59:03PM +0100, Robert Bragg wrote: On Wed, Aug 5, 2015 at 10:29 AM, Daniel Vetter dan...@ffwll.ch wrote: On Wed, Aug 05, 2015 at 10:17:55AM +0100, Chris Wilson wrote: On Wed, Aug 05, 2015 at 11:25

Re: [Intel-gfx] [RFC 8/8] drm/i915: Support for retrieving MMIO register values alongwith timestamps through perf

On Wed, Aug 5, 2015 at 6:55 AM, sourab.gu...@intel.com wrote: From: Sourab Gupta sourab.gu...@intel.com This patch adds support for retrieving MMIO register values alongwith timestamps and forwarding them to userspace through perf. The userspace can request upto 8 MMIO register values to be

Re: [Intel-gfx] [RFC 5/7] drm/i915: Wait for GPU to finish before event stop in Gen Perf PMU

Robert, any thoughts? I think a few pertinent details here that inform how we need to handle this are: 1) Almost all the pmu methods are called in atomic context (except event_init) as they are invoked via events/core.c via an inter-processor interrupt so waiting for a completion in

Re: [Intel-gfx] [RFC 5/7] drm/i915: Wait for GPU to finish before event stop in Gen Perf PMU

On Thu, Jun 25, 2015 at 9:27 AM, Gupta, Sourab sourab.gu...@intel.com wrote: On Thu, 2015-06-25 at 07:42 +, Daniel Vetter wrote: On Thu, Jun 25, 2015 at 06:02:35AM +, Gupta, Sourab wrote: On Mon, 2015-06-22 at 16:09 +, Daniel Vetter wrote: On Mon, Jun 22, 2015 at 02:22:54PM

Re: [Intel-gfx] [RFC 5/7] drm/i915: Wait for GPU to finish before event stop in Gen Perf PMU

On Thu, Jun 25, 2015 at 7:02 AM, Gupta, Sourab sourab.gu...@intel.com wrote: On Mon, 2015-06-22 at 16:09 +, Daniel Vetter wrote: On Mon, Jun 22, 2015 at 02:22:54PM +0100, Chris Wilson wrote: On Mon, Jun 22, 2015 at 03:25:07PM +0530, sourab.gu...@intel.com wrote: From: Sourab Gupta

Re: [Intel-gfx] [RFC 5/7] drm/i915: Wait for GPU to finish before event stop in Gen Perf PMU

On Thu, Jun 25, 2015 at 9:02 AM, Chris Wilson ch...@chris-wilson.co.uk wrote: On Thu, Jun 25, 2015 at 06:02:35AM +, Gupta, Sourab wrote: On Mon, 2015-06-22 at 16:09 +, Daniel Vetter wrote: On Mon, Jun 22, 2015 at 02:22:54PM +0100, Chris Wilson wrote: On Mon, Jun 22, 2015 at

Re: [Intel-gfx] [RFC PATCH 00/11] drm/i915: Expose OA metrics via perf PMU

On Wed, May 27, 2015 at 4:39 PM, wrote: On Thu, May 21, 2015 at 12:17:48AM +0100, Robert Bragg wrote: So for me the 'natural' way to represent this in perf would be through event groups. Create a perf event for every single event -- yes this is 53 events. So when I was first looking

[Intel-gfx] [RFC PATCH] perf: enable fsync to flush buffered samples

--- To allow for pmus that may have internal buffering (e.g. the hardware writes out data to a circular buffer which is only periodically forwarded to userspace via perf) this enables userspace to explicitly ensure it has received all samples before a point in time. Signed-off-by: Robert Bragg rob

Re: [Intel-gfx] [RFC PATCH 00/11] drm/i915: Expose OA metrics via perf PMU

On Tue, May 19, 2015 at 3:53 PM, Peter Zijlstra pet...@infradead.org wrote: On Fri, May 15, 2015 at 02:07:29AM +0100, Robert Bragg wrote: On Fri, May 8, 2015 at 5:24 PM, Peter Zijlstra pet...@infradead.org wrote: On Thu, May 07, 2015 at 03:15:43PM +0100, Robert Bragg wrote: I've changed

[Intel-gfx] [RFC PATCH v2] drm/i915: Expose PMU for Observation Architecture

. Only Haswell is supported currently. v2: - fix deadlock in init_oa_buffer error path - EBADF for bad drm fd, EINVAL for failure to lookup ctx - mmio write barriers, after OA reconfigure, before unlocks - use i915_mutex_lock_interruptible within event init Signed-off-by: Robert Bragg rob

[Intel-gfx] [RFC PATCH] squash: be more careful stopping oacontrol updates

This makes sure we've stopped touching oacontrol before we start resetting OA, PM and clock gating. Shouldn't strictly be needed since we know that oacontrol will have been disabled before we start destroying an event but it seems worth highlighting that update_oacontrol() could still be running

[Intel-gfx] [RFC PATCH v2] perf: Add PERF_EVENT_IOC_FLUSH ioctl

error status Signed-off-by: Robert Bragg rob...@sixbynine.org --- include/linux/perf_event.h | 7 +++ include/uapi/linux/perf_event.h | 1 + kernel/events/core.c| 5 + 3 files changed, 13 insertions(+) diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h

Re: [Intel-gfx] [RFC PATCH 00/11] drm/i915: Expose OA metrics via perf PMU

On Fri, May 8, 2015 at 5:21 PM, Peter Zijlstra pet...@infradead.org wrote: So I've not yet went through the entire series; but I'm wondering if its at all possible to re-use some of this work: lkml.kernel.org/r/1428453299-19121-1-git-send-email-suka...@linux.vnet.ibm.com That's for a Power8

Re: [Intel-gfx] [RFC PATCH 07/11] drm/i915: Expose PMU for Observation Architecture

On 7 May 2015 15:37, Chris Wilson ch...@chris-wilson.co.uk wrote: On Thu, May 07, 2015 at 03:15:50PM +0100, Robert Bragg wrote: +static int init_oa_buffer(struct perf_event *event) +{ + struct drm_i915_private *dev_priv = + container_of(event-pmu, typeof(*dev_priv

Re: [Intel-gfx] [RFC PATCH 07/11] drm/i915: Expose PMU for Observation Architecture

On 7 May 2015 15:58, Chris Wilson ch...@chris-wilson.co.uk wrote: On Thu, May 07, 2015 at 03:15:50PM +0100, Robert Bragg wrote: + /* We bypass the default perf core perf_paranoid_cpu() || + * CAP_SYS_ADMIN check by using the PERF_PMU_CAP_IS_DEVICE + * flag and instead

Re: [Intel-gfx] [RFC PATCH 00/11] drm/i915: Expose OA metrics via perf PMU

On Fri, May 8, 2015 at 5:24 PM, Peter Zijlstra pet...@infradead.org wrote: On Thu, May 07, 2015 at 03:15:43PM +0100, Robert Bragg wrote: I've changed the uapi for configuring the i915_oa specific attributes when calling perf_event_open(2) whereby instead of cramming lots of bitfields

[Intel-gfx] [RFC PATCH 04/11] perf: Add a PERF_RECORD_DEVICE event type

To allow for more extensible, device specific, perf record types this adds a generic PERF_RECORD_DEVICE type that can be used by device drivers. Driver developers can then document some driver-specific header to further detail such a record's type. Signed-off-by: Robert Bragg rob...@sixbynine.org

[Intel-gfx] [RFC PATCH 03/11] perf: Add PERF_EVENT_IOC_FLUSH ioctl

-by: Robert Bragg rob...@sixbynine.org --- include/linux/perf_event.h | 7 +++ include/uapi/linux/perf_event.h | 1 + kernel/events/core.c| 5 + 3 files changed, 13 insertions(+) diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h index 1af35b4..69a0cb9 100644

[Intel-gfx] [RFC PATCH 05/11] perf: allow drivers more control over event logging

This exports enough api to allow drivers to output their own PERF_RECORD_DEVICE events. Signed-off-by: Robert Bragg rob...@sixbynine.org --- include/linux/perf_event.h | 7 +++ kernel/events/core.c| 2 ++ kernel/events/internal.h| 9 - kernel/events/ring_buffer.c | 3

[Intel-gfx] [RFC PATCH 07/11] drm/i915: Expose PMU for Observation Architecture

. Only Haswell is supported currently. Signed-off-by: Robert Bragg rob...@sixbynine.org --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/i915_dma.c | 6 + drivers/gpu/drm/i915/i915_drv.h | 53 +++ drivers/gpu/drm/i915/i915_gem_context.c | 45 +- drivers

[Intel-gfx] [RFC PATCH 10/11] drm/i915: report OA buf overrun + report lost status

This adds two driver specific PERF_RECORD_DEVICE event types for reporting OA buffer overrun and report lost status bits to userspace. Signed-off-by: Robert Bragg rob...@sixbynine.org --- drivers/gpu/drm/i915/i915_oa_perf.c | 53 - include/uapi/drm/i915_drm.h

[Intel-gfx] [RFC PATCH 08/11] drm/i915: add OA config for 3D render counters

This enables access to some additional counters beyond the aggregating A counters, adding a '3D' metric set configuration useful while profiling 3D rendering workloads. Signed-off-by: Robert Bragg rob...@sixbynine.org --- drivers/gpu/drm/i915/i915_drv.h | 7 + drivers/gpu/drm/i915

[Intel-gfx] [RFC PATCH 01/11] perf: export perf_event_overflow

To support pmu drivers in loadable modules, such as the i915 driver Signed-off-by: Robert Bragg rob...@sixbynine.org --- kernel/events/core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/kernel/events/core.c b/kernel/events/core.c index 2fabc06..38c240c 100644 --- a/kernel/events/core.c

[Intel-gfx] [RFC PATCH 06/11] drm/i915: rename OACONTROL GEN7_OACONTROL

OACONTROL changes quite a bit for gen8, with some bits split out into a per-context OACTXCONTROL register Signed-off-by: Robert Bragg rob...@sixbynine.org --- drivers/gpu/drm/i915/i915_cmd_parser.c | 4 ++-- drivers/gpu/drm/i915/i915_reg.h| 2 +- 2 files changed, 3 insertions(+), 3

[Intel-gfx] [RFC PATCH 09/11] drm/i915: Add dev.i915.oa_event_paranoid sysctl option

Consistent with the kernel.perf_event_paranoid sysctl option that can allow non-root users to access system wide cpu metrics, this can optionally allow non-root users to access system wide OA counter metrics from Gen graphics hardware. Signed-off-by: Robert Bragg rob...@sixbynine.org --- drivers

[Intel-gfx] [RFC PATCH 00/11] drm/i915: Expose OA metrics via perf PMU

/ observability_performance_counters_haswell.pdf Kind regards, - Robert Robert Bragg (11): perf: export perf_event_overflow perf: Add PERF_PMU_CAP_IS_DEVICE flag perf: Add PERF_EVENT_IOC_FLUSH ioctl perf: Add a PERF_RECORD_DEVICE event type perf: allow drivers more control over event logging drm/i915: rename OACONTROL

[Intel-gfx] [RFC PATCH 02/11] perf: Add PERF_PMU_CAP_IS_DEVICE flag

The PERF_PMU_CAP_IS_DEVICE flag provides pmu drivers a way to declare that they only monitor device specific metrics and since they don't monitor any cpu metrics then perf should bypass any cpu centric security checks, as well as disallow cpu centric attributes. Signed-off-by: Robert Bragg rob

[Intel-gfx] [RFC PATCH 11/11] WIP: drm/i915: constrain unit gating while using OA

We are still investigating the detailed requirements here, but there are some constraints we need to apply on unit level clock gating for reliable metrics (in particular for a reliable sampling period). Signed-off-by: Robert Bragg rob...@sixbynine.org --- drivers/gpu/drm/i915/i915_oa_perf.c | 70

[Intel-gfx] [RFC PATCH 2/4] perf: Add PERF_PMU_CAP_IS_DEVICE flag

The PERF_PMU_CAP_IS_DEVICE flag provides pmu drivers a way to declare that they only monitor device specific metrics and since they don't monitor any cpu metrics then perf should bypass any cpu centric security checks, as well as disallow cpu centric attributes. Signed-off-by: Robert Bragg rob

[Intel-gfx] [RFC PATCH 4/4] drm/i915: Expose PMU for Observation Architecture

Gen graphics hardware can be set up to periodically write snapshots of performance counters into a circular buffer and this patch exposes that capability to userspace via the perf interface. Only Haswell is supported currently. Signed-off-by: Robert Bragg rob...@sixbynine.org --- drivers/gpu

[Intel-gfx] [RFC PATCH 1/4] perf: export perf_event_overflow

To support pmu drivers in loadable modules, such as the i915 driver Signed-off-by: Robert Bragg rob...@sixbynine.org --- kernel/events/core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/kernel/events/core.c b/kernel/events/core.c index 1425d07..3abb368 100644 --- a/kernel/events/core.c

[Intel-gfx] [RFC PATCH 0/4] perf pmu driver for OA counters

, - Robert Robert Bragg (4): perf: export perf_event_overflow perf: Add PERF_PMU_CAP_IS_DEVICE flag drm/i915: add api to pin/unpin context state drm/i915: Expose PMU for Observation Architecture drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/i915_dma.c | 2

[Intel-gfx] [RFC PATCH 3/4] drm/i915: add api to pin/unpin context state

This adds i915_gem_context_pin/unpin_state functions so that code outside i915_gem_context.c can pin/unpin a context without duplicating knowledge about the alignment constraints. Signed-off-by: Robert Bragg rob...@sixbynine.org --- drivers/gpu/drm/i915/i915_drv.h | 4 drivers/gpu

[Intel-gfx] [PATCH 1/9] intel_gpu_top: don't fclose NULL output

--- tools/intel_gpu_top.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c index b5cfda0..fef7f96 100644 --- a/tools/intel_gpu_top.c +++ b/tools/intel_gpu_top.c @@ -711,7 +711,8 @@ int main(int argc, char **argv) }

[Intel-gfx] [PATCH 2/9] intel_gpu_top: aim for 2000 samples per frame

The previous sample rate of ~167 per frame was rather low in relation to frequency of the events being measured and so for example the derived busy status could become quite unstable at times. --- tools/intel_gpu_top.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git

[Intel-gfx] [PATCH 6/9] intel_reg: add RING_CCID current context ID reg

--- lib/intel_reg.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/lib/intel_reg.h b/lib/intel_reg.h index 8a6e3f1..51430f4 100644 --- a/lib/intel_reg.h +++ b/lib/intel_reg.h @@ -671,6 +671,9 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define RING_NO_REPORT 0x

[Intel-gfx] [PATCH 5/9] intel_reg: rename RING_LEN RING_CTL

This register holds more than the length. This also renames the lsb to RING_ENABLED. --- lib/intel_reg.h | 7 ++- tools/intel_gpu_top.c | 2 +- 2 files changed, 3 insertions(+), 6 deletions(-) diff --git a/lib/intel_reg.h b/lib/intel_reg.h index 56459ea..8a6e3f1 100644 ---

[Intel-gfx] [PATCH 7/9] instdone: Add human readable names for HSW

--- lib/instdone.c | 28 ++-- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/lib/instdone.c b/lib/instdone.c index 99857e2..57b1635 100644 --- a/lib/instdone.c +++ b/lib/instdone.c @@ -381,23 +381,23 @@ init_g4x_instdone1(void) static void

[Intel-gfx] [PATCH 9/9] intel_gpu_top: hide absolute counter values

The absolute values of the pipeline statistic counters are more distracting than they are useful. --- tools/intel_gpu_top.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c index e5582fd..0ef26f8 100644 --- a/tools/intel_gpu_top.c

[Intel-gfx] [PATCH 0/9] intel-gpu-top improvements

of collecting this data, and more, from the kernel via the perf interface (building on work originally done by Chris Wilson last year) so these may just be stop-gap improvements if those experiments pan out. - Robert Robert Bragg (9): intel_gpu_top: don't fclose NULL output intel_gpu_top: aim

[Intel-gfx] [PATCH 4/9] intel_gpu_top: read max/current gt freq via sysfs

--- tools/intel_gpu_top.c | 31 +++ 1 file changed, 31 insertions(+) diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c index 7574ef0..3115b5e 100644 --- a/tools/intel_gpu_top.c +++ b/tools/intel_gpu_top.c @@ -39,6 +39,9 @@ #include sys/time.h #include

[Intel-gfx] [PATCH 3/9] intel_gpu_top: ignore out of range ring pointers

--- tools/intel_gpu_top.c | 9 + 1 file changed, 9 insertions(+) diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c index f60e58b..7574ef0 100644 --- a/tools/intel_gpu_top.c +++ b/tools/intel_gpu_top.c @@ -344,6 +344,15 @@ static void ring_sample(struct ring *ring)

[Intel-gfx] [PATCH 8/9] intel_gpu_top: account for per context statistics

to give us a way of detecting if the context changes. There is now a slightly clearer separation between collecting sample data into a fixed sized array and then handling analytics once per second before printing/outputing the results. Signed-off-by: Robert Bragg robert.br...@intel.com --- tools

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