Re: [Intel-gfx] [PATCH] drm/i915/icl, tgl: whitelist COMMON_SLICE_CHICKEN3 register

On 2/5/21 5:33 AM, Chris Wilson wrote: > Quoting Sagar Ghuge (2021-02-05 00:33:10) >> Adding this register to whitelist will allow UMD to toggle State Cache >> Perf fix disable chicken bit. >> >>"If this bit is enabled, RCC uses BTP+BTI as address tag in its

[Intel-gfx] [PATCH] drm/i915/icl, tgl: whitelist COMMON_SLICE_CHICKEN3 register

scoreboard. Bspec: 11333 Bspec: 45829 Signed-off-by: Sagar Ghuge --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 53f7838bd3c4..318302475c28 10