Re: [Intel-gfx] [PATCH 10/12] drm/i915: Compute display surface offset in the plane check hook for SKL+

Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasim...@intel.com> On Tuesday 03 May 2016 09:09 PM, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä <ville.syrj...@linux.intel.com> SKL has nasty limitations with the display surface offsets: * source x offset + width must

Re: [Intel-gfx] [PATCH 09/12] drm/i915: Make intel_adjust_tile_offset() work for linear buffers

Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasim...@intel.com> On Tuesday 03 May 2016 09:09 PM, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä <ville.syrj...@linux.intel.com> To make life less surprising we can make intel_adjust_tile_offset() deal with linear buf

Re: [Intel-gfx] [PATCH 07/12] drm/i915: Limit fb x offset due to fences

Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasim...@intel.com> On Tuesday 03 May 2016 09:09 PM, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä <ville.syrj...@linux.intel.com> If there's a fence on the object it will be aligned to the start of the object, and hence C

Re: [Intel-gfx] [PATCH 1/2] drm/i915/bxt: Set oscaledcompmethod to enable scale value

On 9/22/2015 6:32 PM, Imre Deak wrote: On ma, 2015-09-21 at 23:00 +0530, Sivakumar Thulasimani wrote: Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasim...@intel.com> On 9/18/2015 2:11 PM, Sonika Jindal wrote: Bspec update tells that we have to enable oscaledcompmethod i

Re: [Intel-gfx] [PATCH 2/2] drm/i915/bxt: eDP low vswing support

Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasim...@intel.com> On 9/18/2015 2:11 PM, Sonika Jindal wrote: Adding voltage swing table for edp to support low vswings. Signed-off-by: Sonika Jindal <sonika.jin...@intel.com> --- drivers/gpu/drm/i915/intel_

Re: [Intel-gfx] [PATCH 1/2] drm/i915/bxt: Set oscaledcompmethod to enable scale value

Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasim...@intel.com> On 9/18/2015 2:11 PM, Sonika Jindal wrote: Bspec update tells that we have to enable oscaledcompmethod instead of ouniqetrangenmethod for enabling scale value during swing programming. Also, scale value is 'don'

[Intel-gfx] [PATCH] Revert "drm/i915: Add eDP intermediate frequencies for CHV"

so reverting the patch that added it in the first place Cc: sta...@vger.kernel.org Reviewed-by: Ville Syrjälä <ville.syrj...@linux.intel.com> Signed-off-by: Sivakumar Thulasimani <sivakumar.thulasim...@intel.com> Signed-off-by: Jani Nikula <jani.nik...@intel.com> --- drivers/gpu/d

Re: [Intel-gfx] [PATCH 4/4] drm/i915: force full detect on sink count change

On 9/2/2015 2:43 PM, Daniel Vetter wrote: On Thu, Aug 27, 2015 at 02:18:32PM +0530, Sivakumar Thulasimani wrote: From: "Thulasimani,Sivakumar" <sivakumar.thulasim...@intel.com> This patch checks for changes in sink count between short pulse hpds and forces full detect when t

Re: [Intel-gfx] [PATCH] drm/i915: Check DP link status on long hpd too

On 8/20/2015 10:07 PM, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä We are no longer checkling the DP link status on long hpd. We used to do that from the .hot_plug() handler, but it was removed when MST got introduced. If there's no userspace we

Re: [Intel-gfx] [PATCH 4/4] drm/i915: force full detect on sink count change

On 9/1/2015 4:12 PM, Jani Nikula wrote: On Thu, 27 Aug 2015, Sivakumar Thulasimani <sivakumar.thulasim...@intel.com> wrote: From: "Thulasimani,Sivakumar" <sivakumar.thulasim...@intel.com> This patch checks for changes in sink count between short pulse hpds and f

Re: [Intel-gfx] [PATCH 2/4] drm/i915: read sink_count dpcd always

On 9/1/2015 3:59 PM, Jani Nikula wrote: On Thu, 27 Aug 2015, Sivakumar Thulasimani <sivakumar.thulasim...@intel.com> wrote: From: "Thulasimani,Sivakumar" <sivakumar.thulasim...@intel.com> This patch reads sink_count dpcd always and removes its read operation based o

Re: [Intel-gfx] [PATCH 2/4] drm/i915: read sink_count dpcd always

On 9/1/2015 6:45 PM, Jani Nikula wrote: On Tue, 01 Sep 2015, Sivakumar Thulasimani <sivakumar.thulasim...@intel.com> wrote: On 9/1/2015 3:59 PM, Jani Nikula wrote: On Thu, 27 Aug 2015, Sivakumar Thulasimani <sivakumar.thulasim...@intel.com> wrote: From: "Thul

Re: [Intel-gfx] [PATCH v2 4/7] drm/i915: add common intel_digital_port_connected function

On 8/27/2015 12:30 PM, Jani Nikula wrote: On Wed, 26 Aug 2015, Sivakumar Thulasimani sivakumar.thulasim...@intel.com wrote: On 8/20/2015 1:17 PM, Jani Nikula wrote: Add a common intel_digital_port_connected() that splits out to functions for different platforms. No functional changes. v2

Re: [Intel-gfx] [PATCH v2 4/7] drm/i915: add common intel_digital_port_connected function

On 8/27/2015 1:38 PM, Jani Nikula wrote: On Thu, 27 Aug 2015, Sivakumar Thulasimani sivakumar.thulasim...@intel.com wrote: On 8/27/2015 12:30 PM, Jani Nikula wrote: On Wed, 26 Aug 2015, Sivakumar Thulasimani sivakumar.thulasim...@intel.com wrote: On 8/20/2015 1:17 PM, Jani Nikula wrote

[Intel-gfx] [PATCH 2/4] drm/i915: read sink_count dpcd always

) Signed-off-by: Sivakumar Thulasimani sivakumar.thulasim...@intel.com --- drivers/gpu/drm/i915/intel_dp.c | 21 - 1 file changed, 8 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 76561e0..9e4e27d 100644

[Intel-gfx] [PATCH 3/4] drm/i915: Save sink_count for tracking changes to it

From: Thulasimani,Sivakumar sivakumar.thulasim...@intel.com sink count can change between short pulse hpd hence this patch adds a member variable to intel_dp so we can track any changes between short pulse interrupts. Signed-off-by: Sivakumar Thulasimani sivakumar.thulasim...@intel.com

[Intel-gfx] [PATCH 1/4] drm/i915: read dpcd 0 - 12 link_status always

and registers 0 to 12. Signed-off-by: Sivakumar Thulasimani sivakumar.thulasim...@intel.com --- drivers/gpu/drm/i915/intel_dp.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 8a66a44..76561e0

[Intel-gfx] [PATCH 4/4] drm/i915: force full detect on sink count change

for such events. v2: changed variable type from u8 to bool (Jani) return immediately if perform_full_detect is set(Siva) Signed-off-by: Sivakumar Thulasimani sivakumar.thulasim...@intel.com --- drivers/gpu/drm/i915/intel_dp.c | 27 ++- 1 file changed, 22 insertions(+), 5 deletions

[Intel-gfx] [PATCH 0/4] Detect DP displays based on sink count change

From: Thulasimani,Sivakumar sivakumar.thulasim...@intel.com These patches together help detect DP displays on short pulse HPD and pass the respective compliance test case (4.2.2.8) v2: modifed first patch so we will read sink_count independent of downstream ports availablility. v3: split first

Re: [Intel-gfx] [PATCH 1/3] drm/i915: read sink_count dpcd always

On 8/26/2015 3:17 PM, Jani Nikula wrote: On Tue, 25 Aug 2015, Sivakumar Thulasimani sivakumar.thulasim...@intel.com wrote: From: Thulasimani,Sivakumar sivakumar.thulasim...@intel.com This patch reads sink_count dpcd always and removes its read operation based on values in downstream port

Re: [Intel-gfx] [PATCH 3/3] drm/i915: force full detect on sink count change

On 8/26/2015 3:32 PM, Jani Nikula wrote: On Tue, 25 Aug 2015, Sivakumar Thulasimani sivakumar.thulasim...@intel.com wrote: From: Thulasimani,Sivakumar sivakumar.thulasim...@intel.com This patch checks for changes in sink count between short pulse hpds and forces full detect when

Re: [Intel-gfx] [PATCH 1/3] drm/i915: read sink_count dpcd always

On 8/26/2015 5:21 PM, Ville Syrjälä wrote: On Tue, Aug 25, 2015 at 05:20:36PM +0530, Sivakumar Thulasimani wrote: From: Thulasimani,Sivakumar sivakumar.thulasim...@intel.com This patch reads sink_count dpcd always and removes its read operation based on values in downstream port dpcd. Also

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Support DDI lane reversal for DP

On 8/18/2015 1:36 AM, Benjamin Tissoires wrote: On Aug 14 2015 or thereabouts, Stéphane Marchesin wrote: On Wed, Aug 5, 2015 at 12:34 PM, Benjamin Tissoires benjamin.tissoi...@redhat.com wrote: On Jul 30 2015 or thereabouts, Sivakumar Thulasimani wrote: On 7/29/2015 8:52 PM, Benjamin

Re: [Intel-gfx] [PATCH 3/3] drm/i915: force full detect on sink count change

On 8/26/2015 3:32 PM, Jani Nikula wrote: On Tue, 25 Aug 2015, Sivakumar Thulasimani sivakumar.thulasim...@intel.com wrote: From: Thulasimani,Sivakumar sivakumar.thulasim...@intel.com This patch checks for changes in sink count between short pulse hpds and forces full detect when

Re: [Intel-gfx] [PATCH v2 4/7] drm/i915: add common intel_digital_port_connected function

On 8/20/2015 1:17 PM, Jani Nikula wrote: Add a common intel_digital_port_connected() that splits out to functions for different platforms. No functional changes. v2: make the function return a boolean Signed-off-by: Jani Nikula jani.nik...@intel.com --- drivers/gpu/drm/i915/intel_dp.c | 41

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Support DDI lane reversal for DP

On 8/26/2015 7:59 PM, Benjamin Tissoires wrote: On Aug 26 2015 or thereabouts, Sivakumar Thulasimani wrote: On 8/18/2015 1:36 AM, Benjamin Tissoires wrote: On Aug 14 2015 or thereabouts, Stéphane Marchesin wrote: On Wed, Aug 5, 2015 at 12:34 PM, Benjamin Tissoires benjamin.tissoi

[Intel-gfx] [PATCH 0/3] Detect DP displays based on sink count change

From: Thulasimani,Sivakumar sivakumar.thulasim...@intel.com These patches together help detect DP displays on short pulse HPD and pass the respective compliance test case (4.2.2.8) v2: modifed first patch so we will read sink_count independent of downstream ports availablility.

[Intel-gfx] [PATCH 1/3] drm/i915: read sink_count dpcd always

dongle Signed-off-by: Sivakumar Thulasimani sivakumar.thulasim...@intel.com --- drivers/gpu/drm/i915/intel_dp.c | 33 ++--- 1 file changed, 14 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 8a66a44

[Intel-gfx] [PATCH 2/3] drm/i915: Save sink_count for tracking changes to it

From: Thulasimani,Sivakumar sivakumar.thulasim...@intel.com Sink count can change between short pulse hpd hence this patch adds a member variable to intel_dp so we can track any changes between short pulse interrupts. Signed-off-by: Sivakumar Thulasimani sivakumar.thulasim...@intel.com

[Intel-gfx] [PATCH 3/3] drm/i915: force full detect on sink count change

detection of hotplug and unplug of panels through dongles that give only short pulse for such events. Signed-off-by: Sivakumar Thulasimani sivakumar.thulasim...@intel.com --- drivers/gpu/drm/i915/intel_dp.c | 20 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/drivers

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Read sink_count dpcd always for short hpd

dropping this patch as i understood more about SINK_COUNT dpcd and DOWNSTREAM_PORT_PRESENT dpcd. will upload a new series with proper fix. On 8/17/2015 6:21 PM, Sivakumar Thulasimani wrote: From: Thulasimani,Sivakumar sivakumar.thulasim...@intel.com Compliance test 4.2.2.8 requires driver

Re: [Intel-gfx] [PATCH 3/4] drm/i915: Avoid TP3 on CHV

On 8/18/2015 12:14 PM, Jani Nikula wrote: On Tue, 18 Aug 2015, Sivakumar Thulasimani sivakumar.thulasim...@intel.com wrote: From: Thulasimani,Sivakumar sivakumar.thulasim...@intel.com This patch removes TP3 support on CHV since there is no support for HBR2 on this platform. v2: rename

Re: [Intel-gfx] [PATCH 3/4] drm/i915: Avoid TP3 on CHV

On 8/18/2015 12:42 PM, Jani Nikula wrote: On Tue, 18 Aug 2015, Sivakumar Thulasimani sivakumar.thulasim...@intel.com wrote: On 8/18/2015 12:14 PM, Jani Nikula wrote: On Tue, 18 Aug 2015, Sivakumar Thulasimani sivakumar.thulasim...@intel.com wrote: From: Thulasimani,Sivakumar

[Intel-gfx] [PATCH] drm/i915: Avoid TP3 on CHV

(Jani) Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Sivakumar Thulasimani sivakumar.thulasim...@intel.com --- drivers/gpu/drm/i915/intel_dp.c | 31 +++ 1 file changed, 23 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915

[Intel-gfx] [PATCH 1/4] Revert drm/i915: Add eDP intermediate frequencies for CHV

it in the first place Signed-off-by: Sivakumar Thulasimani sivakumar.thulasim...@intel.com --- drivers/gpu/drm/i915/intel_dp.c |6 -- 1 file changed, 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index b905c19..bfe0567 100644 --- a/drivers/gpu

[Intel-gfx] [PATCH 2/4] drm/i915: remove HBR2 from chv supported list

From: Thulasimani,Sivakumar sivakumar.thulasim...@intel.com This patch removes 5.4Gbps from supported link rate for CHV since it is not supported in it. v2: change the ordering for better readability (Ville) Signed-off-by: Sivakumar Thulasimani sivakumar.thulasim...@intel.com --- drivers/gpu

[Intel-gfx] [PATCH 0/4] HBR2 cleanup for CHV/SKL

From: Thulasimani,Sivakumar sivakumar.thulasim...@intel.com This patch series cleans up the code to remove HBR2 support for CHV since it is not supported on CHV. Also fixes a bug for SKL platforms where HBR2 is not supported. Thulasimani,Sivakumar (4): Revert drm/i915: Add eDP intermediate

[Intel-gfx] [PATCH 4/4] drm/i915: fix link rates reported for SKL

From: Thulasimani,Sivakumar sivakumar.thulasim...@intel.com This patch fixes the bug that SKL SKUs before B0 might return HBR2 as supported even though it is not supposed to be enabled on such platforms. Signed-off-by: Sivakumar Thulasimani sivakumar.thulasim...@intel.com --- drivers/gpu/drm

[Intel-gfx] [PATCH 3/4] drm/i915: Avoid TP3 on CHV

From: Thulasimani,Sivakumar sivakumar.thulasim...@intel.com This patch removes TP3 support on CHV since there is no support for HBR2 on this platform. Signed-off-by: Sivakumar Thulasimani sivakumar.thulasim...@intel.com --- drivers/gpu/drm/i915/intel_dp.c | 24 +--- 1 file

[Intel-gfx] [PATCH 1/2] drm/i915: Read sink_count dpcd always for short hpd

intel_dp_get_dpcd b) moving crtc enabled checks post sink_count read call Signed-off-by: Sivakumar Thulasimani sivakumar.thulasim...@intel.com --- drivers/gpu/drm/i915/intel_dp.c | 117 --- 1 file changed, 59 insertions(+), 58 deletions(-) diff --git a/drivers/gpu

[Intel-gfx] [PATCH 0/2] Detect DP displays based on sink count change

From: Thulasimani,Sivakumar sivakumar.thulasim...@intel.com These two patches together help detect DP displays on short pulse HPD and pass the respective compliance test case (4.2.2.8) Thulasimani,Sivakumar (2): drm/i915: Read sink_count dpcd always for short hpd drm/i915: Perform full

[Intel-gfx] [PATCH 2/2] drm/i915: Perform full detect on sink_count change

From: Thulasimani,Sivakumar sivakumar.thulasim...@intel.com This patch checks for changes in sink_count during short pulse hpd in check_link_status and forces full detect when sink_count changes. Compliance test 4.2.2.8 expects this behavior in compliant driver. Signed-off-by: Sivakumar

[Intel-gfx] [PATCH 2/2] drm/i915: Perform full detect on sink_count change

From: Thulasimani,Sivakumar sivakumar.thulasim...@intel.com This patch checks for changes in sink_count during short pulse hpd in check_link_status and forces full detect when sink_count changes. Compliance test 4.2.2.8 expects this behavior in compliant driver. Signed-off-by: Sivakumar

[Intel-gfx] [PATCH 0/2] Detect DP displays based on sink count change

From: Thulasimani,Sivakumar sivakumar.thulasim...@intel.com These two patches together help detect DP displays on short pulse HPD and pass the respective compliance test case (4.2.2.8) Thulasimani,Sivakumar (2): drm/i915: Read sink_count dpcd always for short hpd drm/i915: Perform full

[Intel-gfx] [PATCH 1/2] drm/i915: Read sink_count dpcd always for short hpd

intel_dp_get_dpcd b) moving crtc enabled checks post sink_count read call v2: avoid code movement with functionality changes (Ville) Signed-off-by: Sivakumar Thulasimani sivakumar.thulasim...@intel.com --- drivers/gpu/drm/i915/intel_dp.c | 20 1 file changed, 12 insertions(+), 8

Re: [Intel-gfx] [PATCH 4/4] drm/i915: fix link rates reported for SKL

On 8/17/2015 5:59 PM, Jani Nikula wrote: On Mon, 17 Aug 2015, Sivakumar Thulasimani sivakumar.thulasim...@intel.com wrote: From: Thulasimani,Sivakumar sivakumar.thulasim...@intel.com This patch fixes the bug that SKL SKUs before B0 might return HBR2 as supported even though

Re: [Intel-gfx] [PATCH 4/4] drm/i915: fix link rates reported for SKL

On 8/17/2015 6:11 PM, Ville Syrjälä wrote: On Mon, Aug 17, 2015 at 05:45:11PM +0530, Sivakumar Thulasimani wrote: From: Thulasimani,Sivakumar sivakumar.thulasim...@intel.com This patch fixes the bug that SKL SKUs before B0 might return HBR2 as supported even though it is not supposed

[Intel-gfx] [PATCH 4/4] drm/i915: fix link rates reported for SKL

...@linux.intel.com Signed-off-by: Sivakumar Thulasimani sivakumar.thulasim...@intel.com --- drivers/gpu/drm/i915/intel_dp.c | 19 +++ 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 8bc6361..32bf961 100644

[Intel-gfx] [PATCH 2/4] drm/i915: remove HBR2 from chv supported list

From: Thulasimani,Sivakumar sivakumar.thulasim...@intel.com This patch removes 5.4Gbps from supported link rate for CHV since it is not supported in it. v2: change the ordering for better readability (Ville) Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Sivakumar

[Intel-gfx] [PATCH 3/4] drm/i915: Avoid TP3 on CHV

-by: Sivakumar Thulasimani sivakumar.thulasim...@intel.com --- drivers/gpu/drm/i915/intel_dp.c | 24 +--- 1 file changed, 17 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 475d8cb..8bc6361 100644 --- a/drivers/gpu/drm

[Intel-gfx] [PATCH 0/4] HBR2 cleanup for CHV/SKL V2

From: Thulasimani,Sivakumar sivakumar.thulasim...@intel.com This patch series cleans up the code to remove HBR2 support for CHV since it is not supported on CHV. Also fixes a bug for SKL platforms where HBR2 is not supported. V2: Added RB from Ville Syrjälä patches 3 4 updated with comments

[Intel-gfx] [PATCH 1/4] Revert drm/i915: Add eDP intermediate frequencies for CHV

it in the first place Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Sivakumar Thulasimani sivakumar.thulasim...@intel.com --- drivers/gpu/drm/i915/intel_dp.c |6 -- 1 file changed, 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Read sink_count dpcd always for short hpd

On 8/17/2015 5:39 PM, Jani Nikula wrote: On Mon, 17 Aug 2015, Sivakumar Thulasimani sivakumar.thulasim...@intel.com wrote: From: Thulasimani,Sivakumar sivakumar.thulasim...@intel.com Compliance test 4.2.2.8 requires driver to read the sink_count for short pulse interrupt even when the panel

Re: [Intel-gfx] [PATCH 1/2] Revert drm/i915: Add eDP intermediate frequencies for CHV

On 8/14/2015 12:29 PM, Jani Nikula wrote: On Wed, 12 Aug 2015, Daniel Vetter dan...@ffwll.ch wrote: On Wed, Aug 12, 2015 at 04:02:17PM +0300, Ville Syrjälä wrote: On Wed, Aug 12, 2015 at 05:31:55PM +0530, Sivakumar Thulasimani wrote: On 8/12/2015 5:02 PM, Ville Syrjälä wrote: On Fri, Jul

Re: [Intel-gfx] [PATCH v2 5/7] drm/i915: Move intel_dp-lane_count into pipe_config

Reviewed-by: Sivakumar Thulasimani sivakumar.thulasim...@intel.com On Monday 06 July 2015 07:09 PM, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä ville.syrj...@linux.intel.com Currently we clobber intel_dp-lane_count in compute config, which means after a rejected modeset we may

Re: [Intel-gfx] [PATCH 1/7] drm/i915: Clean up DP/HDMI limited color range handling

sdvo is still using color_range name in it's functions. would be good to rename that as well along with dp hdmi done here. otherwise changes are fine Reviewed-by: Sivakumar Thulasimani sivakumar.thulasim...@intel.com On Monday 06 July 2015 05:40 PM, ville.syrj...@linux.intel.com wrote: From

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Dont enable hpd for eDP

On 8/12/2015 6:26 PM, Daniel Vetter wrote: On Mon, Aug 10, 2015 at 05:51:48PM +0530, Sivakumar Thulasimani wrote: On 8/10/2015 5:44 PM, Jani Nikula wrote: On Mon, 10 Aug 2015, Sivakumar Thulasimani sivakumar.thulasim...@intel.com wrote: On 8/10/2015 5:07 PM, Jani Nikula wrote: On Mon, 10

Re: [Intel-gfx] [PATCH] drm/i915: fix checksum write for automated test reply

Hi Daniel, any comments for the patch below ? regards, Sivakumar On Friday 07 August 2015 03:14 PM, Sivakumar Thulasimani wrote: From: Thulasimani,Sivakumar sivakumar.thulasim...@intel.com DP spec requires the checksum of the last block read to be written when replying to TEST_EDID_READ

Re: [Intel-gfx] [PATCH 1/2] Revert drm/i915: Add eDP intermediate frequencies for CHV

hi Ville, can you review these patches ? regards, Sivakumar On Friday 31 July 2015 11:32 AM, Sivakumar Thulasimani wrote: From: Thulasimani,Sivakumar sivakumar.thulasim...@intel.com This reverts commit fe51bfb95c996733150c44d21e1c9f4b6322a326. Author: Ville Syrjälä ville.syrj

Re: [Intel-gfx] [PATCH 1/2] Revert drm/i915: Add eDP intermediate frequencies for CHV

On 8/12/2015 5:02 PM, Ville Syrjälä wrote: On Fri, Jul 31, 2015 at 11:32:52AM +0530, Sivakumar Thulasimani wrote: From: Thulasimani,Sivakumar sivakumar.thulasim...@intel.com This reverts commit fe51bfb95c996733150c44d21e1c9f4b6322a326. Author: Ville Syrjälä ville.syrj...@linux.intel.com Date

Re: [Intel-gfx] [PATCH] drm/i915: Retry port as HDMI if dp_is_edp turns out to be false

hi Mengdong, is there any reason why you cannot modify VBT ? unless it is shipped version you can just flash the modified VBT along with BIOS. Chris, i would be even more surprised if VBIOS/GOP can enable some display when it is configured incorrectly in VBT. Give me a day to check

Re: [Intel-gfx] [PATCH] drm/i915: Retry port as HDMI if dp_is_edp turns out to be false

or have a quirk for this config since this seems to be reported atleast for now as suggested by Lukas i would recommend the first method, if we confirm the root cause is as explained above. On 8/10/2015 11:35 AM, Sivakumar Thulasimani wrote: hi Mengdong, is there any reason why you cannot

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Dont enable hpd for eDP

On 8/10/2015 5:07 PM, Jani Nikula wrote: On Mon, 10 Aug 2015, Sivakumar Thulasimani sivakumar.thulasim...@intel.com wrote: Reviewed-by: Sivakumar Thulasimani sivakumar.thulasim...@intel.com On 8/10/2015 10:35 AM, Sonika Jindal wrote: With HPD support added for all ports including PORT_A

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Dont enable hpd for eDP

On 8/10/2015 5:44 PM, Jani Nikula wrote: On Mon, 10 Aug 2015, Sivakumar Thulasimani sivakumar.thulasim...@intel.com wrote: On 8/10/2015 5:07 PM, Jani Nikula wrote: On Mon, 10 Aug 2015, Sivakumar Thulasimani sivakumar.thulasim...@intel.com wrote: Reviewed-by: Sivakumar Thulasimani

Re: [Intel-gfx] [PATCH 3/3] drm/i915/bxt: WA for swapped HPD pins in A stepping

Reviewed-by: Sivakumar Thulasimani sivakumar.thulasim...@intel.com On 8/10/2015 10:35 AM, Sonika Jindal wrote: WA for BXT A0/A1, where DDIB's HPD pin is swapped to DDIA, so enabling DDIA HPD pin in place of DDIB. v2: For DP, irq_port is used to determine the encoder instead of hpd_pin

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Dont enable hpd for eDP

Reviewed-by: Sivakumar Thulasimani sivakumar.thulasim...@intel.com On 8/10/2015 10:35 AM, Sonika Jindal wrote: With HPD support added for all ports including PORT_A, setting hpd_pin will result in enabling of hpd to edp as well. There is no need to enable HPD on PORT_A hence this patch removes

Re: [Intel-gfx] [PATCH 2/3] drm/i915/bxt: Add HPD support for DDIA

Reviewed-by: Sivakumar Thulasimani sivakumar.thulasim...@intel.com On 8/10/2015 10:35 AM, Sonika Jindal wrote: Also remove redundant comments. Signed-off-by: Sonika Jindal sonika.jin...@intel.com --- drivers/gpu/drm/i915/i915_irq.c | 10 +++--- 1 file changed, 3 insertions(+), 7

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Check live status before reading edid

On 7/14/2015 5:21 PM, Sonika Jindal wrote: Adding this for SKL onwards. v2: Adding checks for VLV/CHV as well. Reusing old ibx and g4x functions to check digital port status. Adding a separate function to get bxt live status (Daniel) Signed-off-by: Sonika Jindal sonika.jin...@intel.com ---

[Intel-gfx] [PATCH] drm/i915: fix checksum write for automated test reply

by Daniel Signed-off-by: Sivakumar Thulasimani sivakumar.thulasim...@intel.com --- drivers/gpu/drm/i915/intel_dp.c |9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index f1b9f93..fa6e202 100644 --- a/drivers

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Support DDI lane reversal for DP

On 8/6/2015 1:04 AM, Benjamin Tissoires wrote: On Jul 30 2015 or thereabouts, Sivakumar Thulasimani wrote: On 7/29/2015 8:52 PM, Benjamin Tissoires wrote: On Jul 29 2015 or thereabouts, Sivakumar Thulasimani wrote: why not detect reverse in intel_dp_detect/intel_hpd_pulse ? that way you

Re: [Intel-gfx] [PATCH v3.1 2/3] drm/i915: Update atomic state when removing mst connector, v3.

thanks for the change :) Reviewed-by: Sivakumar Thulasimani sivakumar.thulasim...@intel.com On 8/6/2015 5:17 PM, Maarten Lankhorst wrote: Fully remove the MST connector from the atomic state, and remove the early returns in check_*_state for MST connectors. With atomic the state can be made

Re: [Intel-gfx] [PATCH v2 02/12] drm/i915: Update atomic state when removing mst connector.

On 7/27/2015 6:05 PM, Maarten Lankhorst wrote: Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com --- drivers/gpu/drm/i915/intel_display.c | 7 -- drivers/gpu/drm/i915/intel_dp_mst.c | 45 +++- 2 files changed, 44 insertions(+), 8

Re: [Intel-gfx] [PATCH] drm/i915/bxt: WA for swapped HPD pins in A stepping

On 8/5/2015 3:23 PM, Imre Deak wrote: On Mon, 2015-07-27 at 11:02 +0530, Sonika Jindal wrote: WA for BXT A0/A1, where DDIB's HPD pin is swapped to DDIA, so enabling DDIA HPD pin in place of DDIB. v2: For DP, irq_port is used to determine the encoder instead of hpd_pin and removing the edp

Re: [Intel-gfx] [PATCH] drm/i915: remove intermediate link rate entries for CHV

On 7/30/2015 10:48 PM, Hindman, Gavin wrote: This applies to all CHV derivatives, including BSW? Gavin Hindman yes, this will apply to all CHV derivatives. -Original Message- From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of Sivakumar Thulasimani Sent

[Intel-gfx] [PATCH 1/2] Revert drm/i915: Add eDP intermediate frequencies for CHV

it in the first place Signed-off-by: Sivakumar Thulasimani sivakumar.thulasim...@intel.com --- drivers/gpu/drm/i915/intel_dp.c |6 -- 1 file changed, 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 44f8a32..d9fb7a8 100644 --- a/drivers/gpu

[Intel-gfx] [PATCH 2/2] drm/i915: remove HBR2 from chv supported list

From: Thulasimani,Sivakumar sivakumar.thulasim...@intel.com This patch removes 5.4Gbps from supported link rate for CHV since it is not supported in it. Signed-off-by: Sivakumar Thulasimani sivakumar.thulasim...@intel.com --- drivers/gpu/drm/i915/intel_dp.c |5 +++-- 1 file changed, 3

[Intel-gfx] [PATCH] drm/i915: read bpp from vbt only for older panels

is zero. v2: use display_info.bpc for deciding when to use vbt_bpp (Jani) Signed-off-by: Sivakumar Thulasimani sivakumar.thulasim...@intel.com --- drivers/gpu/drm/i915/intel_dp.c |5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers

[Intel-gfx] [PATCH] drm/i915: read bpp from vbt only for older panels

From: Thulasimani,Sivakumar sivakumar.thulasim...@intel.com BPP bits defined in VBT should be used only on panels whose edid version is 1.3 or older. EDID version 1.4 introduced offsets where bpp is defined and hence should be preferred over any value programmed in VBT. Signed-off-by: Sivakumar

[Intel-gfx] [PATCH] drm/i915: remove intermediate link rate entries for CHV

From: Thulasimani,Sivakumar sivakumar.thulasim...@intel.com CHV does not support intermediate link rates nor does it support HBR2. This patch removes those entries and returns HBR as the max link rate supported on CHV platform. Signed-off-by: Sivakumar Thulasimani sivakumar.thulasim...@intel.com

Re: [Intel-gfx] [PATCH] drm/i915: read bpp from vbt only for older panels

On 7/30/2015 3:27 PM, Jani Nikula wrote: On Thu, 30 Jul 2015, Sivakumar Thulasimani sivakumar.thulasim...@intel.com wrote: From: Thulasimani,Sivakumar sivakumar.thulasim...@intel.com BPP bits defined in VBT should be used only on panels whose edid version is 1.3 or older. EDID version 1.4

Re: [Intel-gfx] [PATCH] drm/i915: remove intermediate link rate entries for CHV

On 7/30/2015 3:31 PM, Jani Nikula wrote: On Thu, 30 Jul 2015, Sivakumar Thulasimani sivakumar.thulasim...@intel.com wrote: From: Thulasimani,Sivakumar sivakumar.thulasim...@intel.com CHV does not support intermediate link rates nor does it support HBR2. This patch removes those entries

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Support DDI lane reversal for DP

On 7/29/2015 8:52 PM, Benjamin Tissoires wrote: On Jul 29 2015 or thereabouts, Sivakumar Thulasimani wrote: why not detect reverse in intel_dp_detect/intel_hpd_pulse ? that way you can identify both lane count and reversal state without touching anything in the link training code. i am yet

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Support DDI lane reversal for DP

why not detect reverse in intel_dp_detect/intel_hpd_pulse ? that way you can identify both lane count and reversal state without touching anything in the link training code. i am yet to upstream my changes for CHT that i can share if required that does the same in intel_dp_detect without

Re: [Intel-gfx] [PATCH] drm/i915/bxt: WA for swapped HPD pins in A stepping

Reviewed-by: Sivakumar Thulasimani sivakumar.thulasim...@intel.com On 7/27/2015 11:02 AM, Sonika Jindal wrote: WA for BXT A0/A1, where DDIB's HPD pin is swapped to DDIA, so enabling DDIA HPD pin in place of DDIB. v2: For DP, irq_port is used to determine the encoder instead of hpd_pin

Re: [Intel-gfx] [PATCH] drm/i915: fix checksum write for automated test reply

Any comments for this change ? On 7/22/2015 6:31 PM, Sivakumar Thulasimani wrote: From: Thulasimani,Sivakumar sivakumar.thulasim...@intel.com DP spec requires the checksum of the last block read to be written when replying to TEST_EDID_READ. This patch fixes the current code to do the same

Re: [Intel-gfx] [PATCH] drm/i915: Parsing LFP brightness control from VBT

On 7/6/2015 4:35 PM, Vandana Kannan wrote: From: Deepak M m.dee...@intel.com LFP brighness control from the VBT block 43 indicates which controller is used for brightness. LFP1 brightness control method: Bit 7-4 = This field controller number of the brightnes controller. 0 = Controller 0 1 =

Re: [Intel-gfx] [PATCH 1/7] drm: Fix DP_TEST_COUNT_MASK

Reviewed-by: Sivakumar Thulasimani sivakumar.thulasim...@intel.com On 7/24/2015 5:04 AM, Rodrigo Vivi wrote: By Vesa's DP 1.2 Spec this counter has 4 bits [3:0]. This mask is wrong since when the counter was introduced by myself on commit ad9dc91b6e21266bfc6f466db4b95e10211f31ee Author

Re: [Intel-gfx] [PATCH v2 1/3] drm/i915: combine i9xx_get_hpd_pins and pch_get_hpd_pins

, hp_trigger, hp_control, hpd_bxt); + intel_get_hpd_pins(pin_mask, long_mask, hp_trigger, hp_control, + hpd_bxt, pch_port_hotplug_long_detect); intel_hpd_irq_handler(dev, pin_mask, long_mask); } Reviewed-by: Sivakumar Thulasimani sivakumar.thulasim

Re: [Intel-gfx] [PATCH v2 2/3] drm/i915: don't use HPD_PORT_A as an alias for HPD_NONE

. No functional change. v2: - rebase on top of -nightly (Daniel) - make the check for intel_hpd_pin_to_port() return value more readable (Sivakumar) Signed-off-by: Imre Deak imre.d...@intel.com Reviewed-by: Sonika Jindal sonika.jin...@intel.com Reviewed-by: Sivakumar Thulasimani sivakumar.thulasim

Re: [Intel-gfx] [PATCH 1/3] drm/i915: combine i9xx_get_hpd_pins and pch_get_hpd_pins

On 7/21/2015 11:28 PM, Imre Deak wrote: On Tue, 2015-07-21 at 13:50 +0530, Sivakumar Thulasimani wrote: On 7/21/2015 3:13 AM, Imre Deak wrote: These functions are quite similar, so combine them with the use of a new argument for a function that detects long pulses. This will be also needed

Re: [Intel-gfx] [PATCH 3/3] drm/i915/bxt: add support for HPD long/short pulse detection on HPD_PORT_A pin

(1 18) Reviewed-by: Sivakumar Thulasimani sivakumar.thulasim...@intel.com -- regards, Sivakumar ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm/i915/bxt: WA for swapped HPD pins in A stepping

On 7/22/2015 4:39 PM, Jindal, Sonika wrote: On 7/22/2015 4:03 PM, Sivakumar Thulasimani wrote: On 7/22/2015 3:37 PM, Sonika Jindal wrote: As per bspec, on BXT A0/A1, sw needs to activate DDIA HPD logic and interrupts to check the external panel connection and DDIC HPD logic for edp panel

Re: [Intel-gfx] [PATCH] drm/i915/bxt: WA for swapped HPD pins in A stepping

On 7/22/2015 3:37 PM, Sonika Jindal wrote: As per bspec, on BXT A0/A1, sw needs to activate DDIA HPD logic and interrupts to check the external panel connection and DDIC HPD logic for edp panel. v2: For DP, irq_port is used to determine the encoder instead of hpd_pin and removing the edp HPD

[Intel-gfx] [PATCH] drm/i915: fix checksum write for automated test reply

From: Thulasimani,Sivakumar sivakumar.thulasim...@intel.com DP spec requires the checksum of the last block read to be written when replying to TEST_EDID_READ. This patch fixes the current code to do the same. Signed-off-by: Sivakumar Thulasimani sivakumar.thulasim...@intel.com --- drivers/gpu

Re: [Intel-gfx] [PATCH] drm/i915/bxt: WA for swapped HPD pins in A stepping

On 7/22/2015 5:32 PM, Jindal, Sonika wrote: On 7/22/2015 5:01 PM, Sivakumar Thulasimani wrote: On 7/22/2015 4:39 PM, Jindal, Sonika wrote: On 7/22/2015 4:03 PM, Sivakumar Thulasimani wrote: On 7/22/2015 3:37 PM, Sonika Jindal wrote: As per bspec, on BXT A0/A1, sw needs to activate

Re: [Intel-gfx] [PATCH] drm/i915: fix checksum write for automated test reply

On 7/22/2015 5:30 PM, Daniel Vetter wrote: On Wed, Jul 22, 2015 at 03:36:48PM +0530, Sivakumar Thulasimani wrote: From: Thulasimani,Sivakumar sivakumar.thulasim...@intel.com DP spec requires the checksum of the last block read to be written when replying to TEST_EDID_READ. This patch fixes

[Intel-gfx] [PATCH] drm/i915: fix checksum write for automated test reply

From: Thulasimani,Sivakumar sivakumar.thulasim...@intel.com DP spec requires the checksum of the last block read to be written when replying to TEST_EDID_READ. This patch fixes the current code to do the same. Signed-off-by: Sivakumar Thulasimani sivakumar.thulasim...@intel.com --- drivers/gpu

Re: [Intel-gfx] [PATCH 2/3] drm/i915: don't use HPD_PORT_A as an alias for HPD_NONE

this, this change looks good. Reviewed-by: Sivakumar Thulasimani sivakumar.thulasim...@intel.com diff --git a/drivers/gpu/drm/i915/intel_hotplug.c b/drivers/gpu/drm/i915/intel_hotplug.c index 3c53aac..8cda7b9 100644 --- a/drivers/gpu/drm/i915/intel_hotplug.c +++ b/drivers/gpu/drm/i915/intel_hotplug.c

Re: [Intel-gfx] [PATCH 1/3] drm/i915: combine i9xx_get_hpd_pins and pch_get_hpd_pins

On 7/21/2015 3:13 AM, Imre Deak wrote: These functions are quite similar, so combine them with the use of a new argument for a function that detects long pulses. This will be also needed by an upcoming patch adding support for BXT long pulse detection. No functional change. Signed-off-by:

Re: [Intel-gfx] [PATCH 5/9] drm/i915: Clear out DPLL state from pipe config in DSI get config

On 7/13/2015 2:21 PM, Daniel Vetter wrote: On Fri, Jul 10, 2015 at 05:37:07PM +0530, Sivakumar Thulasimani wrote: On 7/1/2015 6:12 PM, Daniel Vetter wrote: On Tue, Jun 30, 2015 at 02:50:33PM +0300, Ville Syrjälä wrote: On Tue, Jun 30, 2015 at 12:13:37PM +0200, Daniel Vetter wrote: On Mon

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