Hi Andi,
On 2022-01-11 14:15:51, Andi Shyti wrote:
>
> From: Tvrtko Ursulin
>
> On a multi-tile platform, each tile has its own registers + GGTT
> space, and BAR 0 is extended to cover all of them.
>
> Up to four gts are supported in i915->gt[], with slot zero
> shadowing the existing
[Redundant sending of this email due to some mail issues]
On 2021-10-28 20:28:12, Matt Roper wrote:
> From: Tvrtko Ursulin
>
> Add some basic plumbing to support more than one dynamically allocated
> struct intel_gt. Up to four gts are supported in i915->gts[], with slot
> zero shadowing the
On 2020-02-28 10:43:37, Chris Wilson wrote:
> Some of the non-privileged registers are at the same offset on each
> engine. We can improve our coverage for unknown HW layout by using the
> reported engine->mmio_base for relative offsets.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Dale B
On 2020-02-28 10:43:36, Chris Wilson wrote:
> Several tests depend upon the implicit engine->mmio_base but have no
> means of determining the physical layout. Since the kernel has started
> providing this information, start putting it to use.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Dale B
On 2020-02-24 13:33:12, Jani Nikula wrote:
> We no longer need or use it as we subclass struct drm_device in our
> struct drm_i915_private, and can always use to_i915() to get at
> i915. Stop assigning the pointer to catch anyone trying to add new users
> for ->dev_private.
>
> Cc: Chris Wilson
On 2020-02-14 19:40:15, Chris Wilson wrote:
> If the context has no engines, it has no engines -- do not override the
> user's setup.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Dale B Stimson
> ---
> lib/i915/gem_engine_topology.c | 19 +++
> 1 file changed, 7
The functionality provided by this patch is something we would like to have.
What are the prospects for having it merged soon?
-Dale
On 2019-10-21 12:01:38, Chris Wilson wrote:
> Some of the non-privileged registers are at the same offset on each
> engine. We can improve our coverage for unknown
> On Wed, Oct 02, 2019 at 12:26:48PM +0100, Chris Wilson wrote:
> > There's very little variation in non-privileged registers for Tigerlake,
> > so we can mostly inherit the set from gen11. There is no whitelist at
> > present, so we do not need to add any special registers.
> >
> > Bugzilla:
