On Wed, 2022-10-19 at 11:21 -0300, Gustavo Sousa wrote:
> Workaround to be applied to platforms using XE_LP graphics.
>
> BSpec: 52890
> Signed-off-by: Gustavo Sousa
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +++
> 2 files ch
On Thu, 2022-10-20 at 16:10 +0100, Matthew Auld wrote:
> We rely on page_sizes.sg in setup_scratch_page() reporting the
> correct
> value if the underlying sgl is not contiguous, however in
> get_pages_internal() we are only looking at the layout of the created
> pages when calculating the sg_page_
On Thu, 2022-07-21 at 14:23 +0800, Slark Xiao wrote:
> Replace 'the the' with 'the' in the comment.
>
> Signed-off-by: Slark Xiao
Reviewed-by: Stuart Summers
> ---
> drivers/gpu/drm/display/drm_dp_helper.c | 2 +-
> drivers/gpu/drm/i915/i915_irq.c | 2 +-
> drivers/gpu/drm
On Thu, 2022-08-04 at 09:46 +0100, Tvrtko Ursulin wrote:
> On 04/08/2022 00:03, Stuart Summers wrote:
> > There can be a race in the PMU process teardown vs the
> > time when the driver is unbound in which the user attempts
> > to stop the PMU process, but the actual data structure
> > in the kerne
On Thu, 2022-08-04 at 09:42 +0100, Tvrtko Ursulin wrote:
> On 04/08/2022 00:03, Stuart Summers wrote:
> > In the driver teardown, we are unregistering the gt prior
> > to unregistering the PMU. This means there is a small window
> > of time in which the application can request metrics from the
> >
On Thu, 2022-07-21 at 08:43 +0100, Tvrtko Ursulin wrote:
> On 21/07/2022 05:30, Summers, Stuart wrote:
> > On Wed, 2022-07-20 at 13:07 -0700, Umesh Nerlige Ramappa wrote:
> > > On Wed, Jul 20, 2022 at 09:14:38AM +0100, Tvrtko Ursulin wrote:
> > > > On 20/07/2022 01:2
2/07/2022 22:03, Umesh Nerlige Ramappa wrote:
> > > > > On Mon, Jul 04, 2022 at 09:31:55AM +0100, Tvrtko Ursulin
> > > > > wrote:
> > > > > > On 01/07/2022 15:54, Summers, Stuart wrote:
> > > > > > > On Fri, 2022-07-01 at
On Fri, 2022-07-01 at 09:37 +0100, Tvrtko Ursulin wrote:
> On 01/07/2022 01:11, Umesh Nerlige Ramappa wrote:
> > On Thu, Jun 30, 2022 at 09:00:28PM +, Stuart Summers wrote:
> > > In the driver teardown, we are unregistering the gt prior
> > > to unregistering the PMU. This means there is a smal
On Thu, 2022-06-30 at 11:29 +0100, Tvrtko Ursulin wrote:
> On 29/06/2022 19:46, Stuart Summers wrote:
> > In the driver teardown, we are unregistering the gt prior
> > to unregistering the PMU. This means there is a small window
> > of time in which the application can request metrics from the
> >
On Mon, 2022-05-02 at 09:34 -0700, Matt Roper wrote:
> Add PVC's forcewake ranges.
>
> Bspec: 67609
> Cc: Daniele Ceraolo Spurio
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/intel_uncore.c | 150
> +-
> drivers/gpu/drm/i915/selftests/intel_uncore.c | 2 +
On Mon, 2022-05-02 at 09:34 -0700, Matt Roper wrote:
> This patch adds the interrupt handler support for
Imperative: Add the interrupt support for...
Otherwise:
Reviewed-by: Stuart Summers
> new copy engines.
>
> Bspec: 54030
> Original-author: CQ Tang
> Signed-off-by: Matt Roper
> ---
> dri
On Mon, 2022-05-02 at 09:34 -0700, Matt Roper wrote:
> This patch adds the reset support for new copy engines
> in PVC.
>
> Bspec: 52549
> Original-author: CQ Tang
> Signed-off-by: Matt Roper
Reviewed-by: Stuart Summers
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 8 +
> drivers/g
On Fri, 2022-03-04 at 14:14 -0800, fei.y...@intel.com wrote:
> From: Fei Yang
>
> GPU hangs have been observed when multiple engines write to the
> same aux_inv register at the same time. To avoid this each engine
> should only invalidate its own auxiliary table. The function
> gen12_emit_flush_x
On Sat, 2022-03-05 at 09:36 +, Patchwork wrote:
Patch Details
Series: drm/i915: avoid concurrent writes to aux_inv (rev5)
URL:https://patchwork.freedesktop.org/series/100772/
State: failure
Details:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22492/index.html
CI Bug Log - ch
On Wed, 2019-12-04 at 19:21 +, Chris Wilson wrote:
> Quoting Summers, Stuart (2019-12-04 19:13:16)
> > On Wed, 2019-12-04 at 13:20 +, Chris Wilson wrote:
> > > Do not blindly assume 30 spin batches will always fit into the
> > > ring,
> > > but
&g
On Wed, 2019-12-04 at 13:20 +, Chris Wilson wrote:
> Do not blindly assume 30 spin batches will always fit into the ring,
> but
> use our measurement tool instead.
>
> Signed-off-by: Chris Wilson
> Cc: Tvrtko Ursulin
> ---
> tests/perf_pmu.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 de
On Sun, 2019-11-24 at 11:27 +, Chris Wilson wrote:
> The implicit soft-pinning we use to probe the vm layout using
> execbuf,
> depends on the batch remaining active (not retired) between execbufs.
> Naturally, if the background retire worker runs the batch is retired
> and
> the implicit soft-
On Thu, 2019-11-21 at 23:30 +, Chris Wilson wrote:
> Use our more regular igt_flush_test() to bind the wait-for-idle and
> error out instead of waiting around forever on critical failure.
>
> Signed-off-by: Chris Wilson
> Cc: Tvrtko Ursulin
Yeah, seems like a better approach here. Should we
On Wed, 2019-11-20 at 17:14 +, Summers, Stuart wrote:
> On Wed, 2019-11-20 at 17:44 +0100, Janusz Krzysztofik wrote:
> > As we've agreed that using I915_GEM_PREAD/PWRITE IOCTLs on dma-buf
> > objects doesn't make much sense, we are not going to extend their
> > h
On Wed, 2019-11-20 at 17:45 +, Chris Wilson wrote:
> Quoting Stuart Summers (2019-11-20 17:36:42)
> > In the event a platform does not properly implement reset,
> > do not go through reset flows for engine domains to avoid
> > an unlikely situation where writes are accepted but register
> > val
On Wed, 2019-11-20 at 17:45 +, Chris Wilson wrote:
> Quoting Stuart Summers (2019-11-20 17:36:42)
> > In the event a platform does not properly implement reset,
> > do not go through reset flows for engine domains to avoid
> > an unlikely situation where writes are accepted but register
> > val
On Wed, 2019-11-20 at 17:44 +0100, Janusz Krzysztofik wrote:
> As we've agreed that using I915_GEM_PREAD/PWRITE IOCTLs on dma-buf
> objects doesn't make much sense, we are not going to extend their
> handlers in the i915 driver with new processing paths required for
> them
> to work correctly with
On Wed, 2019-11-20 at 12:23 +0200, Ville Syrjälä wrote:
> On Tue, Nov 19, 2019 at 04:45:05PM -0800, Stuart Summers wrote:
> > Platforms without display do not map the MCHBAR MMIO into the GFX
> > device BAR. Skip this sequence when display is not available.
>
> Slightly odd decision to hide this s
On Wed, 2019-11-20 at 12:28 +0200, Ville Syrjälä wrote:
> On Tue, Nov 19, 2019 at 05:10:16PM -0800, Stuart Summers wrote:
> > When display is not available, finding the memory bandwidth
> > available
> > for display is not useful. Skip this sequence here.
> >
> > References: HSDES 1209978255
> >
On Tue, 2019-11-19 at 22:57 +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/gem: Ensure aperture exists before setting domain to
> GTT
> URL : https://patchwork.freedesktop.org/series/69698/
> State : failure
>
> == Summary ==
>
> CALLscripts/checksyscalls.sh
> CALL
On Tue, 2019-11-19 at 22:08 +, Chris Wilson wrote:
> Quoting Stuart Summers (2019-11-19 21:30:32)
> > mmap_gtt is already covered by a check for aperture presence.
> > Also add the case to the gem_set_domain IOCTL to avoid this
> > path for unsupported platforms.
>
> It doesn't harm either, it
On Thu, 2019-11-14 at 17:11 -0800, don.hi...@intel.com wrote:
> From: Don Hiatt
>
> On some platforms (e.g. KBL) that do not support GuC submission, but
> the user enabled the GuC communication (e.g for HuC authentication)
> calling the GuC EXIT_S_STATE action results in lose of ability to
> ente
On Sat, 2019-11-09 at 15:10 +, Chris Wilson wrote:
> igt_aux.h already provides the optimal igt_fls(), so use that in
> preference to open coding the brute force version.
>
> Reported-by: Stuart Summers
> Signed-off-by: Chris Wilson
> Cc: Stuart Summers
Thanks for the look here Chris :)
-
On Thu, 2019-10-24 at 09:29 -0700, don.hi...@intel.com wrote:
> From: Don Hiatt
>
> Check to see if GuC submission is enabled before requesting the
> EXIT_S_STATE action.
>
> On some platforms (e.g. KBL) that do not support GuC submission, but
> the user enabled the GuC communication (e.g for Hu
On Thu, 2019-10-17 at 14:42 -0700, Daniele Ceraolo Spurio wrote:
>
> On 10/17/19 12:37 PM, Stuart Summers wrote:
> > During engine initialization in i915 load, the batch buffers
> > being used to set up the initial context are being prematurely
> > ended. In most scenarios, this does not cause a p
On Fri, 2019-10-11 at 12:36 +0100, Chris Wilson wrote:
> Preliminary stub to add engines underneath /sys/class/drm/cardN/, so
> that we can expose properties on each engine to the sysadmin.
>
> To start with we have basic analogues of the i915_query ioctl so that
> we
> can pretty print engine dis
On Tue, 2019-10-01 at 14:54 +0100, Chris Wilson wrote:
> Allow the user to restrict the available set of engines via a module
> parameter.
>
> Signed-off-by: Chris Wilson
> Cc: Stuart Summers
> Cc: Andi Shyti
> Cc: Mika Kuoppala
> Cc: Tvrtko Ursulin
> Cc: Joonas Lahtinen
> Cc: Martin Peres
On Tue, 2019-10-01 at 14:54 +0100, Chris Wilson wrote:
> CI is still unstable whenever we enable more than one engine, and we
> have not yet found a better hack than restricting it to using just
> rcs0.
>
> However, to allow testing to continue on the other engines by
> developers, we allow the av
On Tue, 2019-10-08 at 15:56 +0100, Chris Wilson wrote:
> Quoting Summers, Stuart (2019-10-08 15:52:15)
> > On Tue, 2019-10-08 at 11:56 +0100, Chris Wilson wrote:
> > > A common bane of ours is arbitrary delays in ksoftirqd processing
> > > our
> > > submission
On Tue, 2019-10-08 at 11:56 +0100, Chris Wilson wrote:
> A common bane of ours is arbitrary delays in ksoftirqd processing our
> submission tasklet. Give the submission tasklet a kick before we wait
> to
> avoid those delays eating into a tight timeout.
>
> Signed-off-by: Chris Wilson
> ---
> dr
On Thu, 2019-09-26 at 15:36 +0300, Ville Syrjälä wrote:
> On Wed, Sep 25, 2019 at 02:07:27PM -0700, Stuart Summers wrote:
>
> No commit message.
I'll add one here, should have caught this before posting, sorry.
>
> > Signed-off-by: Stuart Summers
> > ---
> > drivers/gpu/drm/i915/i915_drv.c
On Wed, 2019-09-25 at 15:21 -0700, Daniele Ceraolo Spurio wrote:
> The HuC FW has silently switched to encoding the version the same way
> as
> the GuC FW does, i.e. major.minor.patch instead of just major.minor.
> All
> the current blobs follow the new scheme, but since minor and patch
> are
> bot
On Wed, 2019-09-25 at 08:35 -0700, James Ausmus wrote:
> On Wed, Sep 25, 2019 at 07:33:38AM -0700, Summers, Stuart wrote:
> > On Tue, 2019-09-24 at 15:28 -0700, James Ausmus wrote:
> > > The memory type values have changed in TGL, so we need to
> > > translate
> >
On Tue, 2019-09-24 at 15:28 -0700, James Ausmus wrote:
> The memory type values have changed in TGL, so we need to translate
> them
> differently than ICL. While we're moving it, fix up the ICL
> translation
> for LPDDR4.
>
> BSpec: 53998
>
> v2: Fix up ICL LPDDR4 entry (Ville); Drop unused value
On Sun, 2019-09-22 at 19:48 +0300, Lionel Landwerlin wrote:
> On 21/09/2019 03:39, Lucas De Marchi wrote:
> > On Fri, Sep 13, 2019 at 12:51 AM Chris Wilson <
> > ch...@chris-wilson.co.uk> wrote:
> > > From: Daniele Ceraolo Spurio
> > >
> > > Gen12 has dual-subslices (DSS), which compared to gen11
On Fri, 2019-09-20 at 22:29 +0100, Chris Wilson wrote:
> Quoting Summers, Stuart (2019-09-20 22:09:46)
> > On Thu, 2019-09-19 at 08:00 +0100, Tvrtko Ursulin wrote:
> > > On 18/09/2019 18:31, Stuart Summers wrote:
> > > > Bugzilla: https://bugs.freedesk
On Wed, 2019-09-18 at 13:39 -0700, Daniele Ceraolo Spurio wrote:
>
> On 9/18/19 10:31 AM, Stuart Summers wrote:
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110559
> >
>
> What's the planned usage here? TGL HW only supports slice-level
> power-gating and with only 1 slice on TGL w
On Thu, 2019-09-19 at 08:00 +0100, Tvrtko Ursulin wrote:
> On 18/09/2019 18:31, Stuart Summers wrote:
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110559
>
> Unless there was some discussion I missed we can't just turn it on
> to
> work around a SKIP in IGT. Feature was deliberately
On Wed, 2019-09-18 at 19:31 +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Allow set context SSEU on platforms after gen 11
> URL : https://patchwork.freedesktop.org/series/66870/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_6917 -> Patchwork_1
On Tue, 2019-09-10 at 09:13 +0100, Tvrtko Ursulin wrote:
> On 10/09/2019 05:53, Summers, Stuart wrote:
> > On Fri, 2019-09-06 at 19:13 +0100, Chris Wilson wrote:
> > > Quoting Tvrtko Ursulin (2019-09-02 14:42:44)
> > > >
> > > > On 24/07/2019 14:05, Tvr
On Sun, 2019-09-15 at 21:37 +0100, Chris Wilson wrote:
> Include the active context register state when dumping the engine.
>
> Suggested-by: Mika Kuoppala
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
Reviewed-by: Stuart Summers
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 5 +++
On Fri, 2019-09-06 at 19:13 +0100, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2019-09-02 14:42:44)
> >
> > On 24/07/2019 14:05, Tvrtko Ursulin wrote:
> > >
> > > On 23/07/2019 16:49, Stuart Summers wrote:
> > > > +u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu,
> > > > u8 slice)
On Wed, 2019-08-28 at 10:34 +0100, Chris Wilson wrote:
> Quoting Stuart Summers (2019-08-28 00:14:35)
> > Add a new module parameter, ring_mask, to allow for disabling
> > engines during i915 load. This mask follows the intel_engine_id
> > enum and can be used to hide specified engines from i915 an
On Thu, 2019-08-22 at 23:43 +0100, Chris Wilson wrote:
> Quoting Stuart Summers (2019-08-22 19:32:09)
> > Add a subslice stride calculation when setting subslices. This
> > aligns more closely with the userspace expectation of the subslice
> > mask structure.
> >
> > v2: Use local variable for sub
On Wed, 2019-08-21 at 23:41 +0100, Chris Wilson wrote:
> Quoting Stuart Summers (2019-08-21 00:05:43)
> > Add a new function to copy subslices for a specified slice
> > between intel_sseu structures for the purpose of determining
> > power-gate status.
>
> And ss_stride happens to be one in all ca
On Wed, 2019-08-21 at 23:56 +0100, Chris Wilson wrote:
> Quoting Stuart Summers (2019-08-21 00:05:42)
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > index a82cea95c2f2..99bee06cdbdb 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_
On Wed, 2019-08-21 at 23:49 +0100, Chris Wilson wrote:
> Quoting Stuart Summers (2019-08-21 00:05:44)
> > Currently, the subslice_mask runtime parameter is stored as an
> > array of subslices per slice. Expand the subslice mask array to
> > better match what is presented to userspace through the
>
On Wed, 2019-08-21 at 23:36 +0100, Chris Wilson wrote:
> Quoting Stuart Summers (2019-08-21 00:05:40)
> > Add a subslice stride calculation when setting subslices. This
> > aligns more closely with the userspace expectation of the subslice
> > mask structure.
> >
> > v2: Use local variable for sub
On Tue, 2019-08-20 at 23:29 +, Summers, Stuart wrote:
> On Sat, 2019-08-17 at 02:38 -0700, Lucas De Marchi wrote:
> > From: Michel Thierry
> >
> > Workaround no longer needed (plus L3_LRA_1_GPGPU doesn't exist).
>
> Took a look at this one today and I can at
On Wed, 2019-08-21 at 23:32 +0100, Chris Wilson wrote:
> Quoting Stuart Summers (2019-08-21 00:05:39)
> > Add a new function to set a set of subslices for a given
> > slice.
> >
> > Signed-off-by: Stuart Summers
> > ---
> > drivers/gpu/drm/i915/gt/intel_sseu.c | 6 ++
> > drivers/gpu/dr
On Sat, 2019-08-17 at 02:38 -0700, Lucas De Marchi wrote:
> From: Michel Thierry
>
> Workaround no longer needed (plus L3_LRA_1_GPGPU doesn't exist).
Took a look at this one today and I can at least say this register is
not present at the previous location. I didn't have any luck finding a
speci
On Tue, 2019-08-20 at 11:53 +0100, Chris Wilson wrote:
> Quoting Stuart Summers (2019-08-19 22:50:00)
> > Add a new function to determine whether a particular slice
> > has a given subslice.
> >
> > Signed-off-by: Stuart Summers
> > ---
> > drivers/gpu/drm/i915/gt/intel_sseu.h | 10 +
On Mon, 2019-08-19 at 21:59 -0700, Daniele Ceraolo Spurio wrote:
>
> On 8/19/2019 9:25 PM, Summers, Stuart wrote:
> > On Mon, 2019-08-19 at 18:23 -0700, Daniele Ceraolo Spurio wrote:
> > > First uc firmware release for EHL.
> > >
> > >
On Mon, 2019-08-19 at 18:23 -0700, Daniele Ceraolo Spurio wrote:
> First uc firmware release for EHL.
>
> Signed-off-by: Daniele Ceraolo Spurio <
> daniele.ceraolospu...@intel.com>
> Cc: Matt Roper
> Cc: Anusha Srivatsa
> Cc: Michal Wajdeczko
> ---
> drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c |
On Sun, 2019-08-18 at 10:49 +0100, Chris Wilson wrote:
> If we try to idle while another thread is submitting, we will be
> forced
> to wait until that other thread is finished -- effectively
> serialising
> the parallel workloads, defeating said purpose.
>
> Signed-off-by: Chris Wilson
Reviewed
On Mon, 2019-08-19 at 14:18 -0700, Stuart Summers wrote:
> Currently, the subslice_mask runtime parameter is stored as an
> array of subslices per slice. Expand the subslice mask array to
> better match what is presented to userspace through the
> I915_QUERY_TOPOLOGY_INFO ioctl. The index into this
On Wed, 2019-07-24 at 21:01 +, Patchwork wrote:
> == Series Details ==
>
> Series: Refactor to expand subslice mask (rev 2)
> URL : https://patchwork.freedesktop.org/series/64188/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_6545_full -> Patchwork_13739_full
> =
On Fri, 2019-07-12 at 18:09 -0700, Lucas De Marchi wrote:
> From: Michel Thierry
>
> Enable Small PL for power benefit.
>
> Signed-off-by: Michel Thierry
> Signed-off-by: Lucas De Marchi
Reviewed-by: Stuart Summers
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
> drivers/gp
On Fri, 2019-07-12 at 18:09 -0700, Lucas De Marchi wrote:
> From: Tvrtko Ursulin
>
> Hide the details of MOCS setup from i915_gem by moving both current
> calls
> into one in intel_mocs_init.
>
> Cc: Stuart Summers
> Signed-off-by: Tvrtko Ursulin
> Signed-off-by: Lucas De Marchi
Reviewed-by:
On Tue, 2019-07-23 at 10:12 +0100, Chris Wilson wrote:
> If the system is already idle, omit the GEM_TRACE saying we are about
> to
> wait for idle. It looks confusing in the logs to see a continual
> stream
> of wait-for-idle, as one immediately assumes it is stuck in a loop.
>
> Signed-off-by: C
On Thu, 2019-07-18 at 06:58 +0100, Tvrtko Ursulin wrote:
> On 17/07/2019 22:25, Summers, Stuart wrote:
> > On Wed, 2019-07-17 at 19:06 +0100, Tvrtko Ursulin wrote:
> > > From: Tvrtko Ursulin
> >
> > Not opposed to this exactly, but do we really need this patch if
On Wed, 2019-07-17 at 19:06 +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
Not opposed to this exactly, but do we really need this patch if we're
just getting rid of this routine later in the series?
Thanks,
Stuart
>
> fls returns bit positions starting from one for the lsb and the MCR
>
On Wed, 2019-07-17 at 19:06 +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> A couple issues were present in this code:
>
> 1.
> fls() usage was incorrect causing off by one in subslice mask lookup,
> which in other words means subslice mask of all zeroes is always used
> (subslice mask o
On Wed, 2019-07-17 at 20:47 +, Summers, Stuart wrote:
> On Wed, 2019-07-17 at 19:06 +0100, Tvrtko Ursulin wrote:
> > From: Tvrtko Ursulin
> >
> > Instead of re-calculating the MCR selector in read_subslice_reg do
> > the
> > rwm on its existing value and re
On Wed, 2019-07-17 at 19:06 +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Instead of re-calculating the MCR selector in read_subslice_reg do
> the
> rwm on its existing value and restore it when done.
>
> This consolidates MCR programming to one place for cnl+, and avoids
> re-calculat
On Thu, 2019-07-11 at 22:57 -0700, Lucas De Marchi wrote:
> Tiger Lake has modular FIA bit indicating if we are using it, so add
> to
> the device info.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Stuart Summers
> ---
> drivers/gpu/drm/i915/i915_pci.c | 1 +
> 1 file changed, 1 insertion(
On Thu, 2019-07-11 at 16:49 -0700, Lucas De Marchi wrote:
> On Thu, Jul 11, 2019 at 04:15:42PM -0700, Summers, Stuart wrote:
> > On Thu, 2019-07-11 at 13:58 -0700, Lucas De Marchi wrote:
> > > From: Anusha Srivatsa
> > >
> > > Some platforms may have Mo
On Thu, 2019-07-11 at 16:59 +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
This is generally much more readable than the previous implementation,
thanks! Some minor comments below...
>
> Two issues in this code:
>
> 1.
> fls() usage is incorrect causing off by one in subslice mask lookup,
On Thu, 2019-07-11 at 13:58 -0700, Lucas De Marchi wrote:
> From: Anusha Srivatsa
>
> Some platforms may have Modular FIA. If Modular FIA is used in the
> SOC,
> then Display Driver will access the additional instances of
> FIA based on pre-assigned offset in GTTMADDR space.
>
> Each Modular FIA
On Mon, 2019-07-08 at 22:16 +0100, Chris Wilson wrote:
> Quoting Summers, Stuart (2019-07-08 22:11:15)
> > On Fri, 2019-07-05 at 13:43 +0100, Chris Wilson wrote:
> > > We now track features correctly instead of probing i915-
> > > >engine[RCS0]
> > > whi
On Fri, 2019-07-05 at 13:43 +0100, Chris Wilson wrote:
> We now track features correctly instead of probing i915->engine[RCS0]
> which is much more flexible and avoids any nasty surprises.
>
> Signed-off-by: Chris Wilson
> Cc: Tvrtko Ursulin
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 6
On Fri, 2019-07-05 at 13:43 +0100, Chris Wilson wrote:
> Treat all render engines to the RCS workarounds, simply to avoid
> using
> engine->id when we are trying to think in terms of classes.
>
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
> 1 file cha
On Wed, 2019-06-19 at 18:30 +0300, Jani Nikula wrote:
> On Tue, 18 Jun 2019, Stuart Summers wrote:
> > This addresses the following build error:
> > mm/huge_memory.c: In function ‘__split_huge_page’:
> > mm/huge_memory.c:2506:41: warning: dereferencing ‘void *’ pointer
> > __xa_store(&swap_add
On Thu, 2019-06-06 at 15:42 -0700, Daniele Ceraolo Spurio wrote:
> The size has been increased to 2MB starting from Gen11. GuC and HuC
> FWs
> fit in 1MB so we were fine even with the legacy define, but let's
> still
> move to the correct one before the blobs grow to avoid being caught
> off
> guar
On Tue, 2019-06-04 at 11:49 +0300, Lionel Landwerlin wrote:
> On 29/05/2019 14:24, Chris Wilson wrote:
> > Appease static analysers by making sure subslice always have a
> > value.
> >
> > drivers/gpu/drm/i915//gt/intel_engine_cs.c:971
> > intel_sseu_fls_subslice() error: uninitialized symbol 'sub
On Thu, 2019-05-30 at 09:29 +0100, Saarinen, Jani wrote:
> Hi,
>
>
> > -Original Message-
> > From: Summers, Stuart
> > Sent: keskiviikko 29. toukokuuta 2019 19.02
> > To: Saarinen, Jani ; Ceraolo Spurio,
> > Daniele
> > ; Navare, Manasi D
On Wed, 2019-05-29 at 07:21 -0700, Daniele Ceraolo Spurio wrote:
>
> On 5/28/19 11:48 PM, Saarinen, Jani wrote:
> > Hi,
> >
> > > -Original Message-
> > > From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org]
> > > On Behalf Of
On Wed, 2019-05-29 at 17:58 +0300, Jani Nikula wrote:
> On Fri, 24 May 2019, Stuart Summers wrote:
> > Currently, the subslice_mask runtime parameter is stored as an
> > array of subslices per slice. Expand the subslice mask array to
> > better match what is presented to userspace through the
> >
On Wed, 2019-05-29 at 17:33 +0300, Jani Nikula wrote:
> On Wed, 29 May 2019, Nathan Chancellor
> wrote:
> > Hi Stuart,
> >
> > On Fri, May 24, 2019 at 08:40:22AM -0700, Stuart Summers wrote:
> > > Currently, the subslice_mask runtime parameter is stored as an
> > > array of subslices per slice. E
On Tue, 2019-05-28 at 23:05 +0100, Chris Wilson wrote:
> Quoting Chris Wilson (2019-05-28 23:03:16)
> > Quoting Summers, Stuart (2019-05-28 21:45:05)
> > > On Tue, 2019-05-28 at 21:06 +0100, Chris Wilson wrote:
> > > > We want the index corresponding to the set bit
On Tue, 2019-05-28 at 21:06 +0100, Chris Wilson wrote:
> We want the index corresponding to the set bit but fls() returns the
> 1-index value.
>
> Otherwise, we trigger the sanitycheck
> intel_sseu_get_subslices:46 GEM_BUG_ON(slice >= sseu-
> >max_slices)
> when we look up the invalid slice.
On Tue, 2019-05-28 at 11:32 -0700, Manasi Navare wrote:
> Pushed to dinq, thanks for the patches and the reviews!
Thanks for the push Manasi and the reviews Daniele and others!
-Stuart
>
> Regards
> Manasi
>
> On Fri, May 24, 2019 at 08:40:17AM -0700, Stuart Summers wrote:
> > This patch serie
On Fri, 2019-05-17 at 09:17 -0700, Rodrigo Vivi wrote:
> On Thu, May 16, 2019 at 03:49:19PM +0000, Summers, Stuart wrote:
> > On Thu, 2019-05-16 at 18:42 +0300, Jani Nikula wrote:
> > > On Thu, 16 May 2019, "Summers, Stuart"
> > > wrote:
> > > &g
On Thu, 2019-05-16 at 15:40 -0700, Daniele Ceraolo Spurio wrote:
>
>
> > --- a/drivers/gpu/drm/i915/gt/intel_sseu.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
> > @@ -9,16 +9,18 @@
> >
> > #include
> > #include
> > +#include
>
> AFAICS this header is not needed anymore. With it rem
On Thu, 2019-05-16 at 18:42 +0300, Jani Nikula wrote:
> On Thu, 16 May 2019, "Summers, Stuart"
> wrote:
> > On Thu, 2019-05-16 at 12:59 +0300, Jani Nikula wrote:
> > > On Tue, 14 May 2019, Rodrigo Vivi wrote:
> > > > One possibility that just came
On Thu, 2019-05-16 at 12:59 +0300, Jani Nikula wrote:
> On Tue, 14 May 2019, Rodrigo Vivi wrote:
> > One possibility that just came to my mind now is, what if we make
> > this only for platforms that are still protected by
> > is_alpha_support=1
> > (soon becoming require_force_probe=1)
>
> Pleas
On Wed, 2019-05-15 at 06:43 +0100, Tvrtko Ursulin wrote:
> On 15/05/2019 01:06, Rodrigo Vivi wrote:
> > On Tue, May 14, 2019 at 06:32:01PM +, Summers, Stuart wrote:
> > > On Tue, 2019-05-14 at 17:53 +0100, Chris Wilson wrote:
> > > > Quoting Stuart Summers (201
On Tue, 2019-05-14 at 17:53 +0100, Chris Wilson wrote:
> Quoting Stuart Summers (2019-05-14 17:46:52)
> > To allow easier debug of platforms which do not fully support
> > power-saving render C-state 6, add back the module parameter
> > to allow RC6 flows to be disabled. Instead of directly affecti
On Tue, 2019-05-14 at 17:54 +0100, Chris Wilson wrote:
> Quoting Stuart Summers (2019-05-14 17:46:53)
> > In the event a platform does not properly implement reset,
>
> Then don't enable reset.
Hey Chris,
I'm not sure I fully understand your comment here. The module parameter
is there to do just
On Tue, 2019-05-07 at 14:16 -0700, Daniele Ceraolo Spurio wrote:
>
>
> > >
> > > > --- a/drivers/gpu/drm/i915/intel_device_info.c
> > > > +++ b/drivers/gpu/drm/i915/intel_device_info.c
> > > > @@ -84,17 +84,46 @@ void intel_device_info_dump_flags(const
> > > > struct
> > > > intel_device_info *i
On Tue, 2019-05-07 at 12:00 -0700, Daniele Ceraolo Spurio wrote:
>
> On 5/3/19 2:30 PM, Stuart Summers wrote:
> > Currently, the subslice_mask runtime parameter is stored as an
> > array of subslices per slice. Expand the subslice mask array to
> > better match what is presented to userspace throu
On Tue, 2019-05-07 at 11:12 -0700, Daniele Ceraolo Spurio wrote:
>
> On 5/3/19 2:30 PM, Stuart Summers wrote:
> > Move functions to intel_sseu.h and remove inline qualifier.
> > Additionally, ensure these are all prefixed with intel_sseu_*
> > to match the convention of other functions in i915.
>
On Fri, 2019-05-03 at 10:05 +0100, Lionel Landwerlin wrote:
> Acked-by: Lionel Landwerlin
Thanks for the Ack!
-Stuart
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On Thu, 2019-05-02 at 17:58 +0300, Jani Nikula wrote:
> On Thu, 02 May 2019, "Summers, Stuart"
> wrote:
> > On Thu, 2019-05-02 at 10:15 +0300, Jani Nikula wrote:
> > > Acked-by: Jani Nikula
> >
> > Jani, based on Daniele's feedback, I'm pl
On Thu, 2019-05-02 at 10:15 +0300, Jani Nikula wrote:
> On Wed, 01 May 2019, "Summers, Stuart"
> wrote:
> > On Wed, 2019-05-01 at 14:19 -0700, Daniele Ceraolo Spurio wrote:
> > >
> > > On 5/1/19 2:04 PM, Summers, Stuart wrote:
> > > > On We
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