gt; > > PSR2,
> > > remove this check for PSR2 as there is a plan to test only PSR1 on
> > > PSR2
> > > panels.
> > >
> > > Also add bspec reference to the comment about idle timeout.
> > >
> > > Cc: Tarun Vyas
on")
v2: Remove unnecessary parantheses, make checkpatch happy.
v3: Move the has_psr check to intel_psr_wait_for_idle and commit
message changes (DK).
v4: Derive dev_priv from intel_crtc_state (DK)
v5: Commit message changes to reflect the HW behavior (DK)
Reviewed-by: Dhinakaran Pa
e checkpatch happy.
v3: Move the has_psr check to intel_psr_wait_for_idle and commit
message changes (DK).
v4: Derive dev_priv from intel_crtc_state (DK)
Signed-off-by: Tarun Vyas
---
drivers/gpu/drm/i915/intel_drv.h| 2 +-
drivers/gpu/drm/i915/intel_psr.c| 7 ++-
drivers/gpu/
e checkpatch happy.
v3: Move the has_psr check to intel_psr_wait_for_idle and commit
message changes (DK).
Signed-off-by: Tarun Vyas
---
drivers/gpu/drm/i915/intel_drv.h| 2 +-
drivers/gpu/drm/i915/intel_psr.c| 5 -
drivers/gpu/drm/i915/intel_sprite.c | 2 +-
3 files changed, 6 in
On Mon, Jul 09, 2018 at 01:31:52PM -0700, Dhinakaran Pandiyan wrote:
> On Mon, 2018-07-09 at 12:52 -0700, Tarun Vyas wrote:
> > On Mon, Jul 09, 2018 at 11:58:52AM -0700, Dhinakaran Pandiyan wrote:
> > >
> > > On Mon, 2018-07-09 at 11:16 -0700, Tarun Vyas wrote:
>
On Mon, Jul 09, 2018 at 11:58:52AM -0700, Dhinakaran Pandiyan wrote:
> On Mon, 2018-07-09 at 11:16 -0700, Tarun Vyas wrote:
> > On Mon, Jul 09, 2018 at 11:30:00AM -0700, Dhinakaran Pandiyan wrote:
> > >
> > > On Sun, 2018-07-08 at 18:46 -0700, Tarun Vyas wrote:
>
On Mon, Jul 09, 2018 at 11:30:00AM -0700, Dhinakaran Pandiyan wrote:
> On Sun, 2018-07-08 at 18:46 -0700, Tarun Vyas wrote:
> > In commit "drm/i915: Wait for PSR exit before checking for vblank
> > evasion", the idea was to limit the PSR IDLE checks when PSR is
>
eckpatch happy.
Reviewed-by: Rodrigo Vivi
Signed-off-by: Tarun Vyas
---
drivers/gpu/drm/i915/intel_sprite.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 4990d6e84ddf..83880e3a5f3d 10064
ids everything but pipe A, for the PSR IDLE check.
With this, the PSR IDLE check should be a *no-op* for all but pipe A
which is what was intended originally.
Fixes: a608987970b9 ("drm/i915: Wait for PSR exit before checking for
vblank evasion")
Signed-off-by: Tarun Vyas
---
drivers/gpu
CAN_PSR() to handle platforms that don't support PSR.
v6: Handle local_irq_disable on early return (Chris)
Signed-off-by: Tarun Vyas
---
drivers/gpu/drm/i915/intel_sprite.c | 20
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/int
err (if any) to the caller (Chris)
v5: Form a series with the next patch
v7: Better explain the need for lockless wait and increase the max
timeout to handle refresh rates < 60 Hz (Daniel Vetter)
v8: Rebase
Signed-off-by: Tarun Vyas
---
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/
err (if any) to the caller (Chris)
v5: Form a series with the next patch
v7: Better explain the need for lockless wait and increase the max
timeout to handle refresh rates < 60 Hz (Daniel Vetter)
Signed-off-by: Tarun Vyas
---
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i
CAN_PSR() to handle platforms that don't support PSR.
v6: Handle local_irq_disable on early return (Chris)
Signed-off-by: Tarun Vyas
---
drivers/gpu/drm/i915/intel_sprite.c | 20
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/int
On Tue, Jun 26, 2018 at 09:42:11AM +0100, Chris Wilson wrote:
> Quoting Daniel Vetter (2018-06-26 09:26:57)
> > On Mon, Jun 25, 2018 at 10:57:23PM -0700, Tarun Vyas wrote:
> > > This is a lockless version of the exisiting psr_wait_for_idle().
> > > We want to wait
On Tue, Jun 26, 2018 at 12:43:42PM -0700, Dhinakaran Pandiyan wrote:
> On Tue, 2018-06-26 at 10:26 +0200, Daniel Vetter wrote:
> > On Mon, Jun 25, 2018 at 10:57:23PM -0700, Tarun Vyas wrote:
> > >
> > > This is a lockless version of the exisiting psr_wait_for_idle().
&g
-off-by: Tarun Vyas
---
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_psr.c | 25 +++--
2 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 578346b8d7e2..9cb2b8afdd3e
CAN_PSR() to handle platforms that don't support PSR.
v6: Handle local_irq_disable on early return (Chris)
Signed-off-by: Tarun Vyas
---
drivers/gpu/drm/i915/intel_sprite.c | 20
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/int
On Mon, Jun 25, 2018 at 01:56:24PM +0100, Chris Wilson wrote:
> Quoting Tarun Vyas (2018-06-25 08:09:18)
> > The PIPEDSL freezes on PSR entry and if PSR hasn't fully exited, then
> > the pipe_update_start call schedules itself out to check back later.
> >
> >
CAN_PSR() to handle platforms that don't support PSR.
Signed-off-by: Tarun Vyas
---
drivers/gpu/drm/i915/intel_sprite.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 344c
-off-by: Tarun Vyas
---
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_psr.c | 25 +++--
2 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 578346b8d7e2..9cb2b8afdd3e
PSR.
Regardless, we should wait for PSR exit (if PSR is disabled, we incur
a ~1-2 usec penalty) before reading the PIPEDSL, b/c if we haven't
fully exited PSR, then checking for vblank evasion isn't actually
applicable.
v4: Comment explaining psr_wait after enabling VBL interrupts (
very short (~1-2 usec) wait for cases where PSR
is disabled.
v2: Add comment to explain the 25msec timeout (DK)
v3: Rename psr_wait_for_idle to __psr_wait_for_idle_locked to avoid
naming conflicts and propagate err (if any) to the caller (Chris)
Signed-off-by: Tarun Vyas
---
drivers/gpu
On Fri, Jun 22, 2018 at 01:51:08AM -0700, Tarun Vyas wrote:
> Before checking for vblank evasion in pipe_update_start, we
> need to wait for PSR idle. intel_psr.c already has psr_wait_for_idle
> but we don't need any psr locks in pipe_update_start anyway b/c
> psr_enable/disable
(borrowed from psr_wait_for_idle).
Signed-off-by: Tarun Vyas
---
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_psr.c | 17 +
2 files changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d7dbca1aabf
On Fri, Jun 22, 2018 at 08:12:00AM +0100, Chris Wilson wrote:
> Quoting Tarun Vyas (2018-06-22 08:05:21)
> > This is a lockless version of the exisiting psr_wait_for_idle().
> > We want to wait for PSR to idle out inside intel_pipe_update_start.
> > At the time of a pipe up
very short (~1-2 usec) wait for cases where PSR
is disabled.
v2: Add comment to explain the 25msec timeout (DK)
Signed-off-by: Tarun Vyas
---
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_psr.c | 24
2 files changed, 25 insertions(+)
diff --git a
PSR.
Regardless, we should wait for PSR exit (if PSR is disabled, we incur
a ~1-2 usec penalty) before reading the PIPEDSL, b/c if we haven't
fully exited PSR, then checking for vblank evasion isn't actually
applicable.
Signed-off-by: Tarun Vyas
---
drivers/gpu/drm/i915/intel_sprite.c
very short (~1-2 usec) wait for cases where PSR
is disabled.
Signed-off-by: Tarun Vyas
---
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_psr.c | 19 +++
2 files changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915
On Tue, Jun 19, 2018 at 02:59:54PM -0700, Tarun Vyas wrote:
> On Tue, Jun 19, 2018 at 02:54:07PM -0700, Dhinakaran Pandiyan wrote:
> > On Tue, 2018-06-19 at 14:27 -0700, Dhinakaran Pandiyan wrote:
> > > On Mon, 2018-05-14 at 13:49 -0700, Tarun Vyas wrote:
> > > >
On Tue, Jun 19, 2018 at 02:54:07PM -0700, Dhinakaran Pandiyan wrote:
> On Tue, 2018-06-19 at 14:27 -0700, Dhinakaran Pandiyan wrote:
> > On Mon, 2018-05-14 at 13:49 -0700, Tarun Vyas wrote:
> > >
> > > The PIPEDSL freezes on PSR entry and if PSR hasn't fu
The dpcd read during psr_dpcd_init may not always return the
requested number of bytes. No known cases yet, but good to
put that check in place.
v2: Fix checkpatch warnings.
Signed-off-by: Tarun Vyas
---
drivers/gpu/drm/i915/intel_psr.c | 8 ++--
1 file changed, 6 insertions(+), 2
The dpcd read during psr_dpcd_init may not always return the
requested number of bytes. No known cases yet, but good to
put that check in place.
Signed-off-by: Tarun Vyas
---
drivers/gpu/drm/i915/intel_psr.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu
troduced by "drm/i915/psr: enable ALPM for psr2" enables PSR2
even if ALPM isn't supported, can we add the "Fixes" tag here ? Rest looks good.
Reviewed-by: Tarun Vyas
> Cc: Jose Roberto de Souza
> Cc: Vathsala Nagaraju
> Signed-off-by: Dhinakaran Pandiyan
>
IRED;
> DRM_DEBUG_KMS("PSR2 %ssupported\n",
> dev_priv->psr.sink_psr2_support ? "" : "not ");
The drm_dp_dpcd_read itself reads the first 2 PSR DPCD bytes which is what is
needed. Also, no other callers
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -1159,6 +1159,7 @@ int drm_dp_psr_setup_time(const u8
> psr_cap[EDP_PSR_RECEIVER_CAP_SIZE])
> static const u16 psr_setup_time_us[] = {
> PSR_SETUP_TIME(330),
> PSR_SETUP_TIME(275),
> + PSR_SETUP_TI
intel_dp_get_y_coord_required(intel_dp);
> - DRM_DEBUG_KMS("PSR2 %s on sink", dev_priv->psr.sink_psr2_support
> - ? "supported" : "not supported");
> + DRM_DEBUG_KMS("PSR2 %ssupported\n",
> +
On Mon, May 14, 2018 at 03:00:15PM -0700, Tarun Vyas wrote:
> On Mon, May 14, 2018 at 10:15:19PM +0100, Chris Wilson wrote:
> > Quoting Tarun Vyas (2018-05-14 21:49:20)
> > > intel_pipe_update_start also needs to wait for PSR to idle
> > > out. Need some minor modificati
On Mon, May 14, 2018 at 10:16:38PM +0100, Chris Wilson wrote:
> Quoting Tarun Vyas (2018-05-14 21:49:22)
> > The PIPEDSL freezes on PSR entry and if PSR hasn't fully exited, then
> > the pipe_update_start call schedules itself out to check back later.
> >
> >
On Mon, May 14, 2018 at 10:15:19PM +0100, Chris Wilson wrote:
> Quoting Tarun Vyas (2018-05-14 21:49:20)
> > intel_pipe_update_start also needs to wait for PSR to idle
> > out. Need some minor modifications in psr_wait_for_idle in
> > order to reuse it.
> >
> > Cc
PSR.
Regardless, we should wait for PSR exit (if PSR is supported and active
on the current pipe) before reading the PIPEDSL, b/c if we haven't
fully exited PSR, then checking for vblank evasion isn't actually
applicable.
This scenario applies to a configuration with an additional pipe,
a
We have new users (follow up patch). So, un-statify it
Cc: Chris Wilson
Signed-off-by: Tarun Vyas
---
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_psr.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu
intel_pipe_update_start also needs to wait for PSR to idle
out. Need some minor modifications in psr_wait_for_idle in
order to reuse it.
Cc: Chris Wilson
Signed-off-by: Tarun Vyas
---
drivers/gpu/drm/i915/intel_psr.c | 29 ++---
1 file changed, 18 insertions(+), 11
On Thu, May 03, 2018 at 09:58:56AM -0700, Rodrigo Vivi wrote:
> On Wed, May 02, 2018 at 03:31:15PM -0700, Tarun Vyas wrote:
> > On Wed, May 02, 2018 at 01:04:06PM -0700, Vivi, Rodrigo wrote:
> > > On Wed, May 02, 2018 at 09:51:43PM +0300, Ville Syrjälä wrote:
> > > >
timeout < 0 ? 0 : timeout;" and returns 0
in such cases. Furthermore, the msec_to_jiffies returns an ungined long
value. So, let's do away with the redundant check for an atomic
pipe update.
v2: Commit message changes (Manasi).
Reviewed-by: Manasi Navare
Signed-off-by: Tarun Vya
On Wed, May 02, 2018 at 01:04:06PM -0700, Vivi, Rodrigo wrote:
> On Wed, May 02, 2018 at 09:51:43PM +0300, Ville Syrjälä wrote:
> > On Wed, May 02, 2018 at 11:19:14AM -0700, Tarun Vyas wrote:
> > > On Mon, Apr 30, 2018 at 10:19:33AM -0700, Rodrigo Vivi wrote:
> > > >
On Mon, Apr 30, 2018 at 10:19:33AM -0700, Rodrigo Vivi wrote:
> On Sun, Apr 29, 2018 at 09:00:18PM -0700, Tarun Vyas wrote:
> > From: Tarun
> >
> > The PIPEDSL freezes on PSR entry and if PSR hasn't fully exited, then
> > the pipe_update_start call schedule
rns 0 in such cases. So,
let's do away with the redundant check for an atomic pipe update.
Signed-off-by: Tarun Vyas
---
drivers/gpu/drm/i915/intel_sprite.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel
From: Tarun
The PIPEDSL freezes on PSR entry and if PSR hasn't fully exited, then
the pipe_update_start call schedules itself out to check back later.
On ChromeOS-4.4 kernel, which is fairly up-to-date w.r.t drm/i915 but
lags w.r.t core kernel code, hot plugging an external display triggers
tons
On Thu, Apr 26, 2018 at 02:39:04PM -0700, Tarun Vyas wrote:
> On Thu, Apr 26, 2018 at 10:47:40AM -0700, Dhinakaran Pandiyan wrote:
> >
> >
> >
> > On Thu, 2018-04-26 at 16:41 +0300, Ville Syrjälä wrote:
> > > On Wed, Apr 25, 2018 at 07:10:09PM -0700, taru
From: Tarun
The Display scanline counter freezes on PSR entry. Inside
intel_pipe_update_start, once Vblank interrupts are enabled, we start
exiting PSR, but by the time the scanline counter is read, we may not
have completely exited PSR which leads us to schedule out and check back
later.
On Chro
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