_engine_mask_t cslices;
+ } ccs;
+
LGTM,
Reviewed-by: Umesh Nerlige Ramappa
/*
* Default address space (either GGTT or ppGTT depending on arch).
*
--
2.43.0
On Wed, Feb 14, 2024 at 08:21:21AM +, Tvrtko Ursulin wrote:
On 13/02/2024 18:03, Umesh Nerlige Ramappa wrote:
Once a user opens an fd for a perf event, if the driver undergoes a
function level reset (FLR), the resources are not cleaned up as
expected. For this discussion FLR is defined
On Tue, Feb 13, 2024 at 08:36:43PM +0200, Jani Nikula wrote:
On Tue, 13 Feb 2024, Umesh Nerlige Ramappa
wrote:
Once a user opens an fd for a perf event, if the driver undergoes a
function level reset (FLR), the resources are not cleaned up as
expected. For this discussion FLR is defined
Resending to include patch 2/2. Please ignore this series.
On Mon, Feb 12, 2024 at 10:46:48PM -0800, Umesh Nerlige Ramappa wrote:
Once a user opens an fd for a perf event, if the driver undergoes a
function level reset (FLR), the resources are not cleaned up as
expected. For this discussion FLR
file. To do so, use the event->owner task and find the file
relevant to the event and close it. This relies on the
file->private_data matching the event object.
Test-with: 20240213062948.32735-1-umesh.nerlige.rama...@intel.com
Signed-off-by: Umesh Nerlige Ramappa
Umesh Nerlige Rama
Move pmu teardown to a helper and place it above the destroy hook so
that teardown can also happen inside destroy when events are closed
after i915 pmu is unregistered.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_pmu.c | 106 +---
1 file
close to complete by
checking if list is empty. This wait does not work since the files
are actually closed when unbind returns to user space.
Testing:
- New IGT tests have been added for this and are run with KASAN and
kmemleak enabled.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/dr
Move pmu teardown to a helper and place it above the destroy hook so
that teardown can also happen inside destroy when events are closed
after i915 pmu is unregistered.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_pmu.c | 106 +---
1 file
file. To do so, use the event->owner task and find the file
relevant to the event and close it. This relies on the
file->private_data matching the event object.
Test-with: 20240213062948.32735-1-umesh.nerlige.rama...@intel.com
Signed-off-by: Umesh Nerlige Ramappa
Umesh Nerlige Rama
On Mon, Dec 18, 2023 at 04:05:43PM -0800, Umesh Nerlige Ramappa wrote:
On XEHP platforms user is not able to find MMIO triggered reports in the
OA buffer since i915 squashes the context ID fields. These context ID
fields hold the MMIO trigger markers.
Update logic to not squash the context ID
On Tue, Dec 19, 2023 at 04:57:10AM +, Patchwork wrote:
Patch Details
Series: drm/i915/perf: Update handling of MMIO triggered reports
URL: [1]https://patchwork.freedesktop.org/series/127946/
State: failure
Details:
On Mon, Dec 18, 2023 at 09:48:39PM -0800, Dixit, Ashutosh wrote:
On Mon, 18 Dec 2023 21:28:33 -0800, Dixit, Ashutosh wrote:
On Mon, 18 Dec 2023 16:05:43 -0800, Umesh Nerlige Ramappa wrote:
>
Hi Umesh,
> On XEHP platforms user is not able to find MMIO triggered reports in the
>
/perf: Determine context valid in OA reports")
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_perf.c | 39
1 file changed, 34 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_pe
On Tue, Oct 24, 2023 at 02:20:33PM +0200, Andi Shyti wrote:
Hi Umesh,
On Fri, Oct 20, 2023 at 08:24:41AM -0700, Umesh Nerlige Ramappa wrote:
When the driver unbinds, pmu is unregistered and i915->uabi_engines is
set to RB_ROOT. Due to this, when i915 PMU tries to stop the engine
eve
t;drm/i915/pmu: Handle PCI unbind")
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_pmu.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 108b675088ba..f861863eb7c1 1
isters. The stop event seems to have been left out.
Check for pmu->closed in pmu_event_stop as well.
Based on discussion here -
https://patchwork.freedesktop.org/patch/492079/?series=105790=2
v2: s/is/if/ in commit title
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_
isters. The stop event seems to have been left out.
Check for pmu->closed in pmu_event_stop as well.
Based on discussion here -
https://patchwork.freedesktop.org/patch/492079/?series=105790=2
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_pmu.c | 9 +
1 file c
isters. The stop event seems to have been left out.
Check for pmu->closed in pmu_event_stop as well.
Based on discussion here -
https://patchwork.freedesktop.org/patch/492079/?series=105790=2
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_pmu.c | 9 +
1 file c
On Fri, Sep 22, 2023 at 03:25:08PM -0700, john.c.harri...@intel.com wrote:
From: John Harrison
The GuC has been extended to support a much more friendly engine
busyness interface. So partition the old interface into a 'busy_v1'
space and add 'busy_v2' support alongside. And if v2 is available,
errno on multi-tile systems too. (Umesh)
Signed-off-by: Tvrtko Ursulin
Cc: Umesh Nerlige Ramappa
---
tools/intel_gpu_top.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
index 87e9681e53b4..10601e66b18e 100644
--- a/tools
On Thu, Sep 28, 2023 at 09:16:23AM +0100, Tvrtko Ursulin wrote:
On 27/09/2023 21:13, Umesh Nerlige Ramappa wrote:
On Fri, Sep 22, 2023 at 02:44:28PM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
We have a nice error message displayed when an user with insufficient
permissions tries
On Mon, Sep 25, 2023 at 09:40:46AM +0100, Tvrtko Ursulin wrote:
On 22/09/2023 23:25, john.c.harri...@intel.com wrote:
From: Umesh Nerlige Ramappa
Current engine busyness interface exposed by GuC has a few issues:
- The busyness of active engine is calculated using 2 values provided by
GuC
Cc: Umesh Nerlige Ramappa
---
tools/intel_gpu_top.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
index 87e9681e53b4..e01355f90458 100644
--- a/tools/intel_gpu_top.c
+++ b/tools/intel_gpu_top.c
@@ -554,9 +554,11 @@ static
ngine busyness stats from GuC to
pmu")
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Daniele Ceraolo Spurio
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 38 +--
1 file changed, 35 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submi
On Fri, Sep 15, 2023 at 05:37:53AM +, Patchwork wrote:
Patch Details
Series: i915/guc: Get runtime pm in busyness worker only if already active
URL: [1]https://patchwork.freedesktop.org/series/123744/
State: failure
Details:
On Fri, Sep 15, 2023 at 09:02:05AM -0700, Umesh Nerlige Ramappa wrote:
On Thu, Sep 14, 2023 at 04:18:34AM +, Patchwork wrote:
Patch Details
Series: i915/pmu: Move execlist stats initialization to execlist specific setup
(rev2)
URL: [1]https://patchwork.freedesktop.org/series
On Thu, Sep 14, 2023 at 04:18:34AM +, Patchwork wrote:
Patch Details
Series: i915/pmu: Move execlist stats initialization to execlist specific setup
(rev2)
URL: [1]https://patchwork.freedesktop.org/series/123616/
State: failure
Details:
ngine busyness stats from GuC to
pmu")
Signed-off-by: Umesh Nerlige Ramappa
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 38 +--
1 file changed, 35 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/
On Fri, Sep 08, 2023 at 06:24:16PM -0700, Dixit, Ashutosh wrote:
On Fri, 08 Sep 2023 18:16:26 -0700, Ashutosh Dixit wrote:
Hi Umesh,
From: Umesh Nerlige Ramappa
Correct values for OAR counters are still dependent on enabling the
GEN12_OAG_OACONTROL_OA_COUNTER_ENABLE in OAG_OACONTROL
* PRM says:
@@ -1817,7 +1790,7 @@ static void gen12_init_oa_buffer(struct i915_perf_stream
*stream)
gtt_offset & GEN12_OAG_OATAILPTR_MASK);
/* Mark that we need updated tail pointers to read from... */
- stream->oa_buffer.tail = gtt_offset;
+ st
On Fri, Sep 08, 2023 at 06:16:24PM -0700, Ashutosh Dixit wrote:
The code in oa_buffer_check_unlocked() is correct only if the OA buffer is
16 MB aligned (which seems to be the case today in i915). However when the
16 MB alignment is dropped, when we "Subtract partial amount off the tail",
the "&
xes: 77cdd054dd2c ("drm/i915/pmu: Connect engine busyness stats from GuC to
pmu")
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 1 -
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2 ++
2 files changed, 2 insertions(+), 1 deletion(-
and code comment
- Use runtime pm in the worker
- Put runtime pm after enabling the worker
- Use Link tag and add Fixes tag
Link: https://gitlab.freedesktop.org/drm/intel/-/issues/7077
Fixes: 77cdd054dd2c ("drm/i915/pmu: Connect engine busyness stats from GuC to
pmu")
Signed-off-by: Umesh Nerli
On Mon, Sep 11, 2023 at 08:44:39AM -0700, Daniele Ceraolo Spurio wrote:
On 9/8/2023 10:16 PM, Umesh Nerlige Ramappa wrote:
The worker is canceled in the __gt_park path, but we still see it
running sometimes during suspend. This is likely because some code is
getting a gt wakeref
the gt is active and
running workloads.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/7077
Signed-off-by: Umesh Nerlige Ramappa
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 27 ---
1 file changed, 23 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915
for a context. Re-enable the context valid bit for gen12 platforms.
BSpec: 52196 (description of report_id)
v2: Include BSpec reference (Ashutosh)
Fixes: 00a7f0d7155c ("drm/i915/tgl: Add perf support on TGL")
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Ashutosh Dixit
---
drivers/gp
ading if
not power of 2 size")
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_perf.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index b5491a382bfd..66ab6e1d5c7b 100644
---
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_perf.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index b5491a382bfd..9a8e329c5b5e 100644
--- a/drivers/gpu/drm/i915/i915_pe
for a context. Re-enable the context valid bit for gen12 platforms.
Fixes: 00a7f0d7155c ("drm/i915/tgl: Add perf support on TGL")
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_perf.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i
On Wed, Jun 07, 2023 at 05:40:28PM +, Patchwork wrote:
Patch Details
Series: Avoid reading OA reports before they land (rev2)
URL: [1]https://patchwork.freedesktop.org/series/118886/
State: failure
Details:
[2]https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118886v2/index.html
On Mon, Jun 05, 2023 at 11:44:21PM +, Patchwork wrote:
Patch Details
Series: Avoid reading OA reports before they land
URL: [1]https://patchwork.freedesktop.org/series/118886/
State: failure
Details:
[2]https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118886v1/index.html
://patchwork.freedesktop.org/series/118054/
v2: Drop aging logic completely
v3: Remove unnecessary renames and squash patches
v4: Indentaion fixes
Signed-off-by: Umesh Nerlige Ramappa
Umesh Nerlige Ramappa (2):
i915/perf: Drop the aging_tail logic in perf OA
i915/perf: Do not add ggtt offset to hw_tail
/-/issues/7484
Link: https://gitlab.freedesktop.org/drm/intel/-/issues/7757
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_perf.c | 95 +++---
drivers/gpu/drm/i915/i915_perf_types.h | 12
2 files changed, 38 insertions
ggtt offset for hw_tail is not required for the calculations, so drop
it.
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_perf.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu
://patchwork.freedesktop.org/series/118054/
Signed-off-by: Umesh Nerlige Ramappa
Umesh Nerlige Ramappa (2):
i915/perf: Drop the aging_tail logic in perf OA
i915/perf: Do not add ggtt offset to hw_tail
drivers/gpu/drm/i915/i915_perf.c | 76 ++
drivers/gpu/drm/i915
reason to drop aging logic (Ashutosh)
- Add bug links (Ashutosh)
- rename aged_tail to read_tail
- Squash patches 3 and 1
Bug: https://gitlab.freedesktop.org/drm/intel/-/issues/7484
Bug: https://gitlab.freedesktop.org/drm/intel/-/issues/7757
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm
ggtt offset for hw_tail is not required for the calculations, so drop
it.
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_perf.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu
On Thu, Jun 01, 2023 at 11:22:18AM -0700, Dixit, Ashutosh wrote:
On Wed, 31 May 2023 14:35:47 -0700, Matt Atwood wrote:
Hi Matt,
Set I915_PMU_MAX_GTS to value in I915_MAX_GT, theres no reason for these
values to be different.
Cc: Tvrtko Ursulin
Cc: Umesh Nerlige Ramappa
Cc: Ashutosh
On Wed, May 31, 2023 at 09:13:02PM -0700, Dixit, Ashutosh wrote:
On Wed, 31 May 2023 16:56:34 -0700, Umesh Nerlige Ramappa wrote:
Hi Umesh,
Instead of aged_tail use an iterator that starts from the hw_tail and
goes backward until the oa_buffer.tail looking for valid reports.
Hmm I don't
reports up until this
oa_buffer.tail value which includes invalid reports. Though found on
DG2, this affects all platforms.
Start by dropping the aging tail logic.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_perf.c | 74 ++
drivers/gpu/drm
Instead of aged_tail use an iterator that starts from the hw_tail and
goes backward until the oa_buffer.tail looking for valid reports.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_perf.c | 17 -
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git
ggtt offset for hw_tail is not required for the calculations, so drop
it.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_perf.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index
://patchwork.freedesktop.org/series/118054/
Signed-off-by: Umesh Nerlige Ramappa
Umesh Nerlige Ramappa (3):
i915/perf: Drop the aging_tail logic in perf OA
i915/perf: Do not add ggtt offset to hw_tail
i915/perf: Drop the aged_tail from rewind logic
drivers/gpu/drm/i915/i915_perf.c | 76
alues")
Cc: Umesh Nerlige Ramappa
Cc: Ashutosh Dixit
---
tools/intel_gpu_top.c | 4
1 file changed, 4 insertions(+)
diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
index 4e49367a70c7..a89f13d46f11 100644
--- a/tools/intel_gpu_top.c
+++ b/tools/intel_gpu_top.c
@@ -710,6 +710,10
On Tue, May 23, 2023 at 11:20:54AM -0700, Dixit, Ashutosh wrote:
On Mon, 22 May 2023 15:08:42 -0700, Umesh Nerlige Ramappa wrote:
Hi Umesh,
On Mon, May 22, 2023 at 01:20:12PM -0700, Dixit, Ashutosh wrote:
> On Fri, 19 May 2023 15:56:42 -0700, Umesh Nerlige Ramappa wrote:
>>
On Mon, May 22, 2023 at 02:50:51PM -0700, Dixit, Ashutosh wrote:
On Mon, 22 May 2023 14:34:18 -0700, Umesh Nerlige Ramappa wrote:
On Mon, May 22, 2023 at 01:17:49PM -0700, Ashutosh Dixit wrote:
> Clearing out report id and timestamp as means to detect unlanded reports
> only works if
On Mon, May 22, 2023 at 01:20:12PM -0700, Dixit, Ashutosh wrote:
On Fri, 19 May 2023 15:56:42 -0700, Umesh Nerlige Ramappa wrote:
Hi Umesh,
On DG2, capturing OA reports while running heavy render workloads
sometimes results in invalid OA reports where 64-byte chunks inside
reports have
at the same place each time in the OA buffer (after rewind). If report
size is not a power of 2, we need to zero out the entire report to be able
to detect unlanded reports reliably.
Cc: Umesh Nerlige Ramappa
Signed-off-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_perf.c | 17 +++--
1
/intel/-/issues/7757
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_perf.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 19d5652300ee..61536e3c4ac9 100644
--- a/drivers/gpu/drm
some reference counting, via a mask of unparked GTs, to solve this.
v2: Drop the check for unparked in i915_sample (Ashutosh)
v3: Revert v2 (Tvrtko)
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Umesh Nerlige Ramappa
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Ashutosh Dixit
---
drivers/gpu
From: Tvrtko Ursulin
Trivial prep work for full multi-tile enablement later.
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Vinay Belgaumkar
Reviewed-by: Umesh Nerlige Ramappa
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 ++--
drivers/gpu/drm/i915
the global device
counters (not only GT) we choose not to add per tile versions for now.
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Aravind Iddamsetty
Reviewed-by: Umesh Nerlige Ramappa
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_pmu.c | 82 ++
:
- Include "drm/i915/pmu: Change bitmask of enabled events to u32"
v6: s/u64/u32 (Ashutosh)
v7: CI rerun with updated IGT
Signed-off-by: Umesh Nerlige Ramappa
Test-with: 20230519154650.3751855-1-umesh.nerlige.rama...@intel.com
Tvrtko Ursulin (7):
drm/i915/pmu: Change bitmask of enabled eve
FIXME.
v3: (Ashutosh, Tvrtko)
- Drop BUG_ON that would never fire
- Make enable u64
- Pull in some code from next patch
v4: Set I915_PMU_MAX_GTS to 2 (Tvrtko)
v5: s/u64/u32 where needed (Ashutosh)
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Ashutosh Dixit
From: Tvrtko Ursulin
Having it as u64 was a confusing (but harmless) mistake.
Also add some asserts to make sure the internal field does not overflow
in the future.
v2: Fix WARN_ON firing for INTERRUPT event (Umesh)
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Umesh Nerlige Ramappa
Reviewed
From: Tvrtko Ursulin
As we have more and more engines do not waste time sampling the ones no-
one is monitoring.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Umesh Nerlige Ramappa
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_pmu.c | 3 +++
1 file changed, 3 insertions
From: Tvrtko Ursulin
Given how the metrics are already exported, we also need to run sampling
over engines from all GTs.
Problem of GT frequencies is left for later.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Umesh Nerlige Ramappa
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm
some reference counting, via a mask of unparked GTs, to solve this.
v2: Drop the check for unparked in i915_sample (Ashutosh)
v3: Revert v2 (Tvrtko)
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Umesh Nerlige Ramappa
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Ashutosh Dixit
---
drivers/gpu
From: Tvrtko Ursulin
Trivial prep work for full multi-tile enablement later.
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Vinay Belgaumkar
Reviewed-by: Umesh Nerlige Ramappa
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 ++--
drivers/gpu/drm/i915
FIXME.
v3: (Ashutosh, Tvrtko)
- Drop BUG_ON that would never fire
- Make enable u64
- Pull in some code from next patch
v4: Set I915_PMU_MAX_GTS to 2 (Tvrtko)
v5: s/u64/u32 where needed (Ashutosh)
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915
From: Tvrtko Ursulin
As we have more and more engines do not waste time sampling the ones no-
one is monitoring.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Umesh Nerlige Ramappa
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_pmu.c | 3 +++
1 file changed, 3 insertions
:
- Include "drm/i915/pmu: Change bitmask of enabled events to u32"
Signed-off-by: Umesh Nerlige Ramappa
Test-with: 20230513022234.2832233-1-umesh.nerlige.rama...@intel.com
Tvrtko Ursulin (7):
drm/i915/pmu: Change bitmask of enabled events to u32
drm/i915/pmu: Support PMU for all engines
dr
From: Tvrtko Ursulin
Having it as u64 was a confusing (but harmless) mistake.
Also add some asserts to make sure the internal field does not overflow
in the future.
v2: Fix WARN_ON firing for INTERRUPT event (Umesh)
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Umesh Nerlige Ramappa
Reviewed
From: Tvrtko Ursulin
Given how the metrics are already exported, we also need to run sampling
over engines from all GTs.
Problem of GT frequencies is left for later.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Umesh Nerlige Ramappa
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm
the global device
counters (not only GT) we choose not to add per tile versions for now.
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Aravind Iddamsetty
Reviewed-by: Umesh Nerlige Ramappa
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_pmu.c | 82 ++
On Wed, May 17, 2023 at 09:25:03AM -0700, Dixit, Ashutosh wrote:
On Wed, 17 May 2023 01:26:15 -0700, Tvrtko Ursulin wrote:
On 17/05/2023 07:55, Umesh Nerlige Ramappa wrote:
> On Tue, May 16, 2023 at 05:25:50PM -0700, Dixit, Ashutosh wrote:
>> On Tue, 16 May 2023 16:35:28 -0700, Umes
On Tue, May 16, 2023 at 05:39:02PM -0700, Dixit, Ashutosh wrote:
On Tue, 16 May 2023 16:35:33 -0700, Umesh Nerlige Ramappa wrote:
Hi Umesh,
+static u64 frequency_enabled_mask(void)
u32
+{
+ unsigned int i;
+ u64 mask = 0;
u32
+
+ for (i = 0; i < I915_PMU_MAX_
On Tue, May 16, 2023 at 05:25:50PM -0700, Dixit, Ashutosh wrote:
On Tue, 16 May 2023 16:35:28 -0700, Umesh Nerlige Ramappa wrote:
Hi Umesh/Tvrtko,
Mostly repeating comments/questions made on the previous patch below.
From: Tvrtko Ursulin
Having it as u64 was a confusing (but harmless
On Tue, May 16, 2023 at 03:13:01PM -0700, Umesh Nerlige Ramappa wrote:
On Tue, May 16, 2023 at 10:24:45AM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Having it as u64 was a confusing (but harmless) mistake.
Also add some asserts to make sure the internal field does not overflow
From: Tvrtko Ursulin
Trivial prep work for full multi-tile enablement later.
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Vinay Belgaumkar
Reviewed-by: Umesh Nerlige Ramappa
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 ++--
drivers/gpu/drm/i915
some reference counting, via a mask of unparked GTs, to solve this.
v2: Drop the check for unparked in i915_sample (Ashutosh)
v3: Revert v2 (Tvrtko)
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Umesh Nerlige Ramappa
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Ashutosh Dixit
---
drivers/gpu
FIXME.
v3: (Ashutosh, Tvrtko)
- Drop BUG_ON that would never fire
- Make enable u64
- Pull in some code from next patch
v4: Set I915_PMU_MAX_GTS to 2 (Tvrtko)
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_pmu.c | 148
From: Tvrtko Ursulin
Given how the metrics are already exported, we also need to run sampling
over engines from all GTs.
Problem of GT frequencies is left for later.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Umesh Nerlige Ramappa
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm
the global device
counters (not only GT) we choose not to add per tile versions for now.
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Aravind Iddamsetty
Reviewed-by: Umesh Nerlige Ramappa
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_pmu.c | 82 ++
From: Tvrtko Ursulin
As we have more and more engines do not waste time sampling the ones no-
one is monitoring.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Umesh Nerlige Ramappa
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_pmu.c | 3 +++
1 file changed, 3 insertions
From: Tvrtko Ursulin
Having it as u64 was a confusing (but harmless) mistake.
Also add some asserts to make sure the internal field does not overflow
in the future.
v2: Fix WARN_ON firing for INTERRUPT event (Umesh)
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Umesh Nerlige Ramappa
Cc
:
- Include "drm/i915/pmu: Change bitmask of enabled events to u32"
Signed-off-by: Umesh Nerlige Ramappa
Test-with: 20230513022234.2832233-1-umesh.nerlige.rama...@intel.com
Tvrtko Ursulin (7):
drm/i915/pmu: Change bitmask of enabled events to u32
drm/i915/pmu: Support PMU for all engines
dr
Nerlige Ramappa
---
I am not entirely sure the __builtin_constant_p->BUILD_BUG_ON branch will
work with all compilers. Lets see...
Compile tested only.
---
drivers/gpu/drm/i915/i915_pmu.c | 32 ++--
1 file changed, 22 insertions(+), 10 deletions(-)
diff --git a/driv
On Mon, May 15, 2023 at 11:12:33AM +0100, Tvrtko Ursulin wrote:
On 15/05/2023 07:44, Umesh Nerlige Ramappa wrote:
From: Tvrtko Ursulin
Reserve some bits in the counter config namespace which will carry the
tile id and prepare the code to handle this.
No per tile counters have been added yet
-by: Umesh Nerlige Ramappa
Test-with: 20230513022234.2832233-1-umesh.nerlige.rama...@intel.com
Tvrtko Ursulin (6):
drm/i915/pmu: Support PMU for all engines
drm/i915/pmu: Skip sampling engines with no enabled counters
drm/i915/pmu: Transform PMU parking code to be GT based
drm/i915/pmu: Add
From: Tvrtko Ursulin
Trivial prep work for full multi-tile enablement later.
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Vinay Belgaumkar
Reviewed-by: Umesh Nerlige Ramappa
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 ++--
drivers/gpu/drm/i915
some reference counting, via a mask of unparked GTs, to solve this.
v2: Drop the check for unparked in i915_sample (Ashutosh)
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Umesh Nerlige Ramappa
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_pmu.c | 9
the global device
counters (not only GT) we choose not to add per tile versions for now.
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Aravind Iddamsetty
Reviewed-by: Umesh Nerlige Ramappa
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_pmu.c | 82 ++
FIXME.
v3: (Ashutosh, Tvrtko)
- Drop BUG_ON that would never fire
- Make enable u64
- Pull in some code from next patch
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_pmu.c | 148
From: Tvrtko Ursulin
As we have more and more engines do not waste time sampling the ones no-
one is monitoring.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Umesh Nerlige Ramappa
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_pmu.c | 3 +++
1 file changed, 3 insertions
From: Tvrtko Ursulin
Given how the metrics are already exported, we also need to run sampling
over engines from all GTs.
Problem of GT frequencies is left for later.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Umesh Nerlige Ramappa
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm
On Fri, May 12, 2023 at 09:41:56PM -0700, Dixit, Ashutosh wrote:
On Fri, 12 May 2023 18:55:44 -0700, Umesh Nerlige Ramappa wrote:
From: Tvrtko Ursulin
Reserve some bits in the counter config namespace which will carry the
tile id and prepare the code to handle this.
No per tile counters
FIXME.
v3: (Ashutosh, Tvrtko)
- Drop BUG_ON that would never fire
- Make enable u64
- Pull in some code from next patch
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_pmu.c | 148 +++-
drivers/gpu/drm/i915/i915_pmu.h
With MTL, frequency and rc6 counters are specific to a gt. Export these
counters via gt-specific events to the user space.
v2: Review comments (Ashutosh, Tvrtko)
Signed-off-by: Umesh Nerlige Ramappa
Tvrtko Ursulin (6):
drm/i915/pmu: Support PMU for all engines
drm/i915/pmu: Skip sampling
From: Tvrtko Ursulin
Trivial prep work for full multi-tile enablement later.
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Vinay Belgaumkar
Reviewed-by: Umesh Nerlige Ramappa
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 ++--
drivers/gpu/drm/i915
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