flip is added
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/skl_watermark.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
b/drivers/gpu/drm/i915/display/skl_watermark.c
index a01b1dc01348
Avoid using struct drm_i915_private reference and use intel_display
instead. This is in preparation for the rest of the patches in this
series where hw support for the minimum and interim ddb allocations
for async flip is added
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display
>From xe3 onwards, there is a provision to define and
use min ddb and interim ddb allocations for async flip
use case. Add the dbuf allocation status as part of
i915_ddb_info as well to show if min or interim ddb
is being used.
Bspec: 72053
Signed-off-by: Vinod Govindapillai
---
.../drm/i
programmed.
Bspec: 69880, 72053
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Vinod Govindapillai
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 9 ++
.../drm/i915/display/intel_display_types.h| 8 ++
.../drm/i915/display/skl_universal_plane.c| 31 +++
.../i915/display
Avoid using struct drm_i915_private reference and use intel_display
instead. This is in preparation for the rest of the patches in this
series where hw support for the minimum and interim ddb allocations
for async flip is added
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display
Use intel_display object instead of struct drm_i915_private in
skl_plane_wm_equals(). This is in preparation for the rest of
the patches in this series where hw support for the minimum and
interim ddb allocations for async flip is added
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm
Convert all intel_de_read() to use intel_display instead of
struct drm_i915_private object. This is in preparation for
the rest of the patches in this series where hw support for
the minimum and interim ddb allocations for async flip is
added.
Signed-off-by: Vinod Govindapillai
---
drivers/gpu
Update intel_enabled_dbuf_slices_mask to use intel_display instead
of drm_i915_private object. This is a prepratory patch for the next
patch in the series, where all intel_de_read calls in skl_watermarks.c
are updated to use intel_display instead of drm_i915_private.
Signed-off-by: Vinod
):
drm/i915/xe3: Use hw support for min/interim ddb allocations for async
flip
Vinod Govindapillai (7):
drm/i915/display: update intel_enabled_dbuf_slices_mask to use
intel_display
drm/i9i5/display: use intel_display in intel_de_read calls of
skl_watermark.c
drm/i915/display
ned-off-by: Stanislav Lisovskiy
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_display_device.c | 5 +
drivers/gpu/drm/i915/display/intel_display_device.h | 2 ++
drivers/gpu/drm/i915/display/intel_display_irq.c| 10 ++
drivers/gpu/drm/i915/i915_re
off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_display_device.c | 5 +
drivers/gpu/drm/i915/display/intel_display_device.h | 2 ++
drivers/gpu/drm/i915/display/intel_display_irq.c| 10 ++
drivers/gpu/drm/i915/i915_reg.h | 2 ++
4 files chan
ror message to kernel log.
v2: Initialize dbuf overlap flag in runtime_defaults (Jani Nikula)
v3: Unmask the overlap detection interrupt (Uma)
v4: use display over i915 (Jani Nikula)
Bspec: 69450
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/disp
ror message to kernel log.
v2: Initialize dbuf overlap flag in runtime_defaults (Jani Nikula)
v3: Unmask the overlap detection interrupt (Uma)
Bspec: 69450
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_display_device.c |
Update the reference overhaed values for audio bw calculations
for MTL onwards
Bspec: 67768
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_dp.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers
Limit the audio bw check with DP2 configurations only
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_dp.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index
After pruning the sad audio frequency list, if there are no
supported audio frequencies left, audio cannot be supported.
So mark has_audio accordingly.
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_audio.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion
In intel_dp_audio_compute_config() pipe_config->has_audio decision
is now based on combination of two condition checks. Split out these
condition as two separate checks to facilitate handling has_audio
decision when we introduce audio bw checks in the follow up patches.
Signed-off-by: Vi
For a pipe configuration, if no supported audio frequencies are
found, then start reducing the audio channels and try assess the
sad audio frequency list again.
Bspec: 67768
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_audio.c | 32 --
1 file
Calculate the audio bw requirements and check the supported sad
audio frequencies are feasible with selected pipe configuration.
If not feasible, prune the audio frequencies from sad list.
Bspec: 67768
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_audio.c | 107
assess if an audio frequency can be supported with a pipe config.
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_dp.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display
We would need to check the validity of connector ELD from multiple
places in the follow up patches. So create a separate function to
check the validity for ELD.
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_audio.c | 18 ++
1 file changed, 14
ls. In the followup patches, we
don't even need the drm_i915_private object in this function.
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_audio.c | 5 ++---
drivers/gpu/drm/i915/display/intel_audio.h | 3 +--
drivers/gpu/drm/i915/display/intel_dp.c| 2 +-
drive
and the assessment is done again. Eventually both supported
audio frequency and channels are updated to SAD in ELD.
TODO: Update the hblank available calculations for Xe3
Vinod Govindapillai (9):
drm/i915/display: get rid of encoder param in
intel_audio_compute_config
drm/i915/display
ror message to kernel log.
v2: Initialize dbuf overlap flag in runtime_defaults (Jani Nikula)
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_display_device.c | 5 +
drivers/gpu/drm/i915/display/intel_display_device.h | 2 ++
driv
ror message to kernel log.
v2: Initialize dbuf overlap flag in runtime_defaults (Jani Nikula)
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_display_device.c | 5 +
drivers/gpu/drm/i915/display/intel_display_device.h | 2 ++
driv
)
Bspec: 21664
Suggested-by: Ville Syrjälä
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_fbc.c | 22 ++
1 file changed, 6 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_fbc.c | 22 ++
1 file changed, 6 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
index e9189a864f69..492dc26ecfa2 100644
--- a/drivers
Move the handling of the disabling FBC when VT-d is active wa
as part of the intel_fbc_check_plane()
Bspec: 21664
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_fbc.c | 22 ++
1 file changed, 6 insertions(+), 16 deletions(-)
diff --git a/drivers
Async flip call is not needed. The updated fb mapping is updated
as part of the fixup_initial_plane_config() call. Otherwise we
end up updating the PLAN_SURF register twice with the same info.
v2: avoid async_flip instead of removing fixup call (Ville)
Signed-off-by: Vinod Govindapillai
In XE, the updated fb mapping is already done and updated as
part of intel_find_initial_plane_obj(). So no need to invoke
fixup_initial_plane_config() again as it would basically write
the same data to "PLAN_SURF" again.
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/
quot;iommu/vt-d: Use rbtree to track iommu probed devices")
Signed-off-by: Lu Baolu
Signed-off-by: Vinod Govindapillai
---
drivers/iommu/intel/iommu.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/i
This has already been sent to try bot
https://patchwork.freedesktop.org/series/132132/
Lu Baolu (1):
iommu/vt-d: Fix WARN_ON in iommu probe path
drivers/iommu/intel/iommu.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
--
2.34.1
.
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_bw.c | 8 ++--
drivers/gpu/drm/i915/display/intel_bw.h | 6 ++
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index
o qgv points as well (Vinod)
v2: - pcode confirms that for qgv points, it sets whatever the
driver sets (Vinod)
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_bw.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gp
4 (Vinod)
v8: - Simplify icl_force_disable_sagv (Vinod)
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_bw.c | 50 ++--
drivers/gpu/drm/i915/display/skl_watermark.c | 2 +-
drivers/gpu/drm/i915/display/skl_watermar
Extract the code to prepare the QGV points mask as per the
format expected by the pcode as this could be utlized from
multiple points.
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_bw.c | 16 +++-
1 file changed, 11 insertions(+), 5 deletions(-)
diff
ing
to get access to target device and adding those traces manually.
v2: - Make the debug more generic and move it to intel_dram_detect
(Gustavo Sousa)
v3: - Use %u for unsigned variable in debug prints (Gustavo)
Reviewed-by: Gustavo Sousa
Signed-off-by: Stanislav Lisovskiy
Signed-off
v_point_mask to return max qgv point
mask (Vinod)
v4: - Minor changes in icl_find_qgv_points (Vinod)
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_bw.c | 80 +++--
1 file changed, 50 insertions(+), 30 deletions
calculate max qgv/psf gv
point
drm/i915/display: Disable SAGV on bw init, to force QGV point
recalculation
drm/i915/display: handle systems with duplicate psf gv points
Vinod Govindapillai (2):
drm/i915/display: extract code to prepare qgv points mask
drm/i915/display: force qgv
.
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_bw.c | 8 ++--
drivers/gpu/drm/i915/display/intel_bw.h | 6 ++
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index
4 (Vinod)
v8: - Simplify icl_force_disable_sagv (Vinod)
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_bw.c | 50 ++--
drivers/gpu/drm/i915/display/skl_watermark.c | 2 +-
drivers/gpu/drm/i915/display/skl_watermar
Lisovskiy
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_bw.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index 5f4f93524bef..f6690d545d95 100644
--- a/drivers/gpu/drm/i915
v_point_mask to return max qgv point
mask (Vinod)
v4: - Minor changes in icl_find_qgv_points (Vinod)
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_bw.c | 80 +++--
1 file changed, 50 insertions(+), 30 deletions
Extract the code to prepare the QGV points mask as per the
format expected by the pcode as this could be utlized from
multiple points.
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_bw.c | 16 +++-
1 file changed, 11 insertions(+), 5 deletions(-)
diff
ing
to get access to target device and adding those traces manually.
v2: - Make the debug more generic and move it to intel_dram_detect
(Gustavo Sousa)
v3: - Use %u for unsigned variable in debug prints (Gustavo)
Reviewed-by: Gustavo Sousa
Signed-off-by: Stanislav Lisovskiy
Signed-off
calculate max qgv/psf gv
point
drm/i915/display: Disable SAGV on bw init, to force QGV point
recalculation
drm/i915/display: handle systems with duplicate qgv/psf gv points
Vinod Govindapillai (2):
drm/i915/display: extract code to prepare qgv points mask
drm/i915/display: force
Lisovskiy
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_bw.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index 844d2d9efeb4..20c67474154e 100644
--- a/drivers/gpu/drm/i915
4 (Vinod)
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_bw.c | 55 ++--
drivers/gpu/drm/i915/display/skl_watermark.c | 2 +-
drivers/gpu/drm/i915/display/skl_watermark.h | 1 +
3 files changed, 54 insertio
v_point_mask to return max qgv point
mask (Vinod)
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_bw.c | 76 -
1 file changed, 49 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/displa
ing
to get access to target device and adding those traces manually.
v2: - Make the debug more generic and move it to intel_dram_detect
(Gustavo Sousa)
v3: - Use %u for unsigned variable in debug prints (Gustavo)
Reviewed-by: Gustavo Sousa
Signed-off-by: Stanislav Lisovskiy
Signed-off
We have couple of customer issues, related to SAGV/QGV point
calculation. Those patches contain fixes plus some additional
debugs for those issues.
Stanislav Lisovskiy (4):
drm/i915: Add meaningful traces for QGV point info error handling
drm/i915: Extract code required to calculate max qgv/ps
From: Balasubramani Vivekanandan
Enable the display support for LUNARLAKE
Signed-off-by: Balasubramani Vivekanandan
Signed-off-by: Lucas De Marchi
Reviewed-by: Matt Roper
---
drivers/gpu/drm/xe/xe_pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers
From: Balasubramani Vivekanandan
Load DMC for XE2LPD. The value 0x8000 is the maximum payload size for
any xe2lpd dmc firmware.
Signed-off-by: Balasubramani Vivekanandan
Signed-off-by: Dnyaneshwar Bhadane
---
drivers/gpu/drm/i915/display/intel_dmc.c | 9 -
1 file changed, 8 insertions
From: Stanislav Lisovskiy
According to BSpec we need to write the MBUS CTL and DBUF CTL both for
increasing CDCLK case (pre plane) and for decreasing CDCLK case (post
plane). Make sure those updates are in place for Xe2-LPD.
Since the mbus update is not only on pre-enable anymore, also rename th
From: Ravi Kumar Vodapalli
Add programming sequence for changes on CDCLK for Lunar Lake
platforms. It's mostly the same as MTL, but with some
additional programming for the squash and crawling steps when
a change in mdclk/cdclk ratio is observed.
v2: Remove wrong changes for bxt_cdclk_cd2x_pipe(
From: Stanislav Lisovskiy
Previously we always updated DBuf MBUS CTL and DBUF CTL regs after
CDCLK has been changed(CDCLK_CTL), however for Xe2-LPD we can't do like
that anymore. According to BSpec, we have to first update DBuf regs and
then write CDCLK regs, when CDCLK is decreased, which we do
since it's compatible
with previous versions (Matt Roper)
- Squash the serialization of global state when mdclk_cdclk_ratio
changes
Bspec: 68864, 69482, 69445
Cc: Mika Kahola
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Lucas De Marchi
Signed-off-by: Vinod Govindap
Rest of the cdclk patches as well as the patches to enable the display in LNL
Balasubramani Vivekanandan (2):
drm/i915/xe2lpd: Load DMC
drm/xe/lnl: Enable the display support
Ravi Kumar Vodapalli (1):
drm/i915/lnl: Add programming for CDCLK change
Stanislav Lisovskiy (3):
drm/i915/lnl: I
drm_gem_private_object_init expect the object size be page size
aligned. The xe_bo create functions do not update the size for
any alignment requirements. So align cfb size to be page size
aligned in xe stolen memory handling.
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/xe/compat
FBC compressed frame buffer size need to be PAGE_SIZE aligned
and the corresponding the drm_gem functions check the object
size alignment using PAGE_SIZE macro. Use the PAGE_SIZE macro
in the cfb alloc as well instead of the magic number.
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm
DRM gem object handling expet the object size to be page size
aligned. Neither the driver or xe stolen memory handlers do that
causing BUG_ON being triggered in some cases.
Vinod Govindapillai (2):
drm/i915/display: use PAGE_SIZE macro for FBC cfb alloc
drm/xe: Modify the cfb size to be page
FIFO underruns are observed when FBC is enabled on plane 2 or
plane 3. Recommended WA is to update the FBC enabling sequence.
The plane binding register bits need to be updated separately
before programming the FBC enable bit.
Bspec: 74151
Reviewed-by: Mika Kahola #v3
Signed-off-by: Vinod
removed reference to PSR from the comments
Added reference to HSD
v4: updated the comments to include wa number
Vinod Govindapillai (1):
drm/i915/xe2lpd: implement WA for underruns while enabling FBC
drivers/gpu/drm/i915/display/intel_fbc.c | 8 +++-
1 file changed, 7 insertions(+), 1
In earlier versions, FBC was restricted if PSR2 is enabled. From
xe2lpd onwards no such restrictions are needed anymore.
HSD: 14014305387
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_fbc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers
FBC restriction when PSR2 is enabled can be removed in xe2lpd
Vinod Govindapillai (1):
drm/i915/xe2lpd: remove the FBC restriction if PSR2 is enabled
drivers/gpu/drm/i915/display/intel_fbc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--
2.34.1
: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_fbc.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
index bde12fe62275..8a3594e4d992 100644
--- a/drivers/gpu/drm/i915
removed reference to PSR from the comments
Added reference to HSD
Vinod Govindapillai (1):
drm/i915/xe2lpd: implement WA for underruns while enabling FBC
drivers/gpu/drm/i915/display/intel_fbc.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
--
2.34.1
Because of HW bug, the FBC enabling sequence need to be updated.
The plane binding registrer need to be updated before programming
the FBC enable bit.
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_fbc.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion
Update the FBC enabling sequence. The plane binding register bits
need to programmed before fbe enable bit.
v2: update the patch subject and description as this underrun is not
tied to PSR. FIFO underruns are observed when FBC is enabled on
plane other than the primary.
Vinod
Implement the alternate WA for the underruns when both PSR2
and FBC is enabled.
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_fbc.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers
Implement the alternate WA for the underruns when both PSR2
and FBC is enabled.
Vinod Govindapillai (1):
drm/i915/xe2lpd: alternate WA for underruns with PSR2 and FBC
drivers/gpu/drm/i915/display/intel_fbc.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
--
2.34.1
In devices with PSR2 + FBC support, choose between PSR2 selective fetch
and FBC based on the better power saving efficiency
Vinod Govindapillai (2):
drm/i915/xe2lpd: check selective fetch is optimal in some cases
drm/i915/xe2lpd: prefer FBC for full frame fetch in PSR2
.../drm/i915/display
If the selective fetch is not optimal, use FBC
Bspec: 68881
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_fbc.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display
If both PSR2 + FBC is supported, in cases where the selective
fetch area is greater than 25% of the screen area, FBC might
be more efficient. So have a possibility to check this and add
provision to enable FBC in such cases.
Bspec: 68881
Signed-off-by: Vinod Govindapillai
---
.../drm/i915
.sha...@intel.com
Vinod Govindapillai (2):
drm/i915/display: debugfs entry to list display capabilities
drm/i915: remove display device info from i915 capabilities
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 12
drivers/gpu/drm/i915/i915_debugfs.c | 1
Create a separate debugfs entry to list the display capabilities
IGT can rely on this debugfs entry for tests that depend on
display device and display runtime info for both xe and i915
drivers.
v2: rename the entry to i915_display_capabilities (Chaitanya)
Signed-off-by: Vinod Govindapillai
Display device and display runtime info is exposed as part of
i915_display_capabilities debugfs entry. Remove this information
from i915_ capabilities as it is now reduntant.
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/i915_debugfs.c | 1 -
1 file changed, 1 deletion(-)
diff
Create a separate debugfs entry to list the display capabilities
IGT can rely on this debugfs entry for tests that depend on
display device and display runtime info for both xe and i915
drivers.
v2: rename the entry to i915_display_capabilities (Chaitanya)
Signed-off-by: Vinod Govindapillai
i915_capabilities from this patch series. Remove this only after
IGT starts using the i915_display_capabilities
Vinod Govindapillai (1):
drm/i915/display: debugfs entry to list display capabilities
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 12
1 file changed, 12
Create a separate debugfs entry to list the display capabilities
IGT can rely on this debugfs entry for tests that depend on
display device and display runtime info for both xe and i915
drivers.
v2: rename the entry to i915_display_capabilities (Chaitanya)
Signed-off-by: Vinod Govindapillai
Display device and display runtime info is exposed as part of
i915_display_capabilities debugfs entry. Remove this information
from i915_ capabilities as it is now reduntant.
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/i915_debugfs.c | 1 -
1 file changed, 1 deletion(-)
diff
Expose the display device info as a separate debugfs entry to list out
display device info and remove the same from i915_capabilities
v2: rename the debugs entry to i915_display_capabilities and patch
description changes
Vinod Govindapillai (2):
drm/i915/display: debugfs entry to list
Display device info is exposed as a separate debugfs entry. So
remove the duplicate entries from i915_capabilities debugfs
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/i915_debugfs.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers
Have a common debugfs entry to get the display device info for
both xe and i915 drivers.
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/display
Expose the display device info as a separate debugfs entry to list out
display device info and remove the same from i915_capabilities
Vinod Govindapillai (2):
drm/i915/display: display device info debugfs entry
drm/i915: remove display device info from i915 capabilities
drivers/gpu/drm/i915
Update the number of scalers per pipe based on the display
capabilities reported.
v1: define the field values instead of the magic number (JaniN)
Bspec: 71161
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_display_device.c | 7 +++
1 file changed, 7 insertions
Get the reported device capabilities and update DSC and scaler
feature support
v1: use defined field values instead of magic numbers (Jani Nikula)
Vinod Govindapillai (3):
drm/i915/xe2lpd: display capability register definitions
drm/i915/xe2lpd: update the dsc feature capability
drm/i915
Update the global dsc flag based on the display capabilities
reported.
v1: define the field values instead of the magic number (JaniN)
Bspec: 71161
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_display_device.c | 8
1 file changed, 8 insertions(+)
diff
Register definitions to track the reported scalable display
feature configurations
Bspec: 71161
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/i915_reg.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
Update the number of scalers per pipe based on the display
capabilities reported.
Bspec: 71161
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_display_device.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
Update the global dsc flag based on the display capabilities
reported.
Bspec: 71161
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_display_device.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
b
Register definitions to track the reported scalable display
feature configurations
Bspec: 71161
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/i915_reg.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index
Get the reported device capabilities and update DSC and scaler
feature support
Vinod Govindapillai (3):
drm/i915/xe2lpd: display capability register definitions
drm/i915/xe2lpd: update the dsc feature capability
drm/i915/xe2lpd: update the scaler feature capability
drivers/gpu/drm/i915
FBC is supported with RGB32 8:8:8:8 with or without alpha
Bspec: 68904, 69560
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_fbc.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm
FBC can be supported in first three planes in lnl
Vinod Govindapillai (2):
drm/i915/lnl: possibility to enable FBC on first three planes
drm/i915/lnl: update the supported plane formats with FBC
drivers/gpu/drm/i915/display/intel_fbc.c | 11 ++-
drivers/gpu/drm/i915
ess macro
Bspec: 69560
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_fbc.c | 3 +++
drivers/gpu/drm/i915/display/skl_universal_plane.c | 9 ++---
drivers/gpu/drm/i915/i915_reg.h| 2 ++
3 files changed, 11 insertions(+), 3 deletions(-)
d
ess macro
Bspec: 69560
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_fbc.c | 3 +++
drivers/gpu/drm/i915/display/skl_universal_plane.c | 9 ++---
drivers/gpu/drm/i915/i915_reg.h| 2 ++
3 files changed, 11 insertions(+), 3 deletions(-)
d
For LNL onwards, FBC can be supported on planes with per
pixel alpha
Bspec: 69560
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_fbc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm
FBC can be supported in first three planes in lnl
Vinod Govindapillai (2):
drm/i915/lnl: possibility to enable FBC on first three planes
drm/i915/lnl: FBC is supported with per pixel alpha
drivers/gpu/drm/i915/display/intel_fbc.c | 6 +-
drivers/gpu/drm/i915/display
For LNL onwards, FBC can be supported on planes with per
pixel alpha
Bspec: 69560
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_fbc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm
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