Re: [Intel-gfx] [PATCH] drm/i915/icl: Enable DC9 as lowest possible state during screen-off

2018-10-23 Thread Yadav, Jyoti R
On 9/20/2018 1:36 AM, Anusha Srivatsa wrote: From: Animesh Manna ICL supports DC5, DC6, and DC9. Enable DC9 during screen-off, and enable DC5/6 when appropriate. v2: (James Ausmus) - Also handle ICL as GEN9_LP in i915_drm_suspend_late and i915_drm_suspend_early - Add DC9 to

Re: [Intel-gfx] [PATCH] [intel-gfx] drm/i915/csr Added DC5 and DC6 counter register for ICL in debugfs entry.

2018-10-02 Thread Yadav, Jyoti R
On 10/3/2018 10:36 AM, Vivi, Rodrigo wrote: On Oct 2, 2018, at 9:20 PM, Yadav, Jyoti R wrote: DC5 and DC6 counter register tells about residency of DC5 and DC6. These registers are same for SKL and ICL. v2 : Remove csr_version check. Added generic check regarding DC counters

Re: [Intel-gfx] [PATCH] drm/i915/psr: Enable AUX-A IO power well on ICL for PSR

2018-09-17 Thread Yadav, Jyoti R
Deak, Imre ; Pandiyan, Dhinakaran ; Atwood, Matthew S ; Yadav, Jyoti R ; Bowman, Casey G Subject: [PATCH] drm/i915/psr: Enable AUX-A IO power well on ICL for PSR PSR requires AUX IO power well to be enabled. This was already in place for CNL, extend this for ICL too. Not enabling the power we

Re: [Intel-gfx] [PATCH] [intel-gfx] drm/i915/intel_csr.c Added ICL Stepping info.

2018-09-03 Thread Yadav, Jyoti R
Yeah, Thanks for the "Acked-by" Rodrigo. I request Imre/Anusha to review/acknowledge the same. Regards Jyoti -Original Message- From: Vivi, Rodrigo Sent: Tuesday, September 4, 2018 11:02 AM To: Yadav, Jyoti R Cc: intel-gfx@lists.freedesktop.org Subject: Re: [Intel-gfx] [PAT

Re: [Intel-gfx] [PATCH] [intel-gfx] drm/i915/intel_csr.c Fix DMC FW Loading issue on ICL.

2018-08-29 Thread Yadav, Jyoti R
Hi Imre, I also checked in Bspec. Good catch:) FW size = (End address - Start Address) + 1 Will update the patch also. Thanks for quickly reviewing the patch. Regards Jyoti _ On 8/29/2018 2:51 PM, Imre Deak wrote: On Tue, Aug 28, 2018 at 03:24:19PM -0400, Jyoti Yadav wrote: From: Jyoti

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for Load DMC v1.07 on Icelake (rev2)

2018-08-28 Thread Yadav, Jyoti R
Hi Jani, I am already debugging this issue. Issue got reproduced when we are locally running the icl_dmc_ver1_07.bin on ICL HW. We could not see this issue with previous FW version icl_dmc_ver1_01.bin file.  Already in discussion with DMC FW folks. There are two FW stepping integrated in

Re: [Intel-gfx] [PATCH] firmware/dmc/icl: load v1.07 on icelake.

2018-08-01 Thread Yadav, Jyoti R
Hi Anusha, I think we should also add "HAS_CSR" capability, which is being exercised inside intel_csr_ucode_init() path. For ICL, inside intel_device_info structure we should add has_csr = 1, otherwise below check will fail and function will return from there itself. if

Re: [Intel-gfx] [PATCH] [RFC i-g-t] Test Design to verify mipi enable/disable sequence.

2017-01-09 Thread Yadav, Jyoti R
Hi Jani, Thanks for finding time to review the patch. Please find my comments inline. Regards Jyoti -Original Message- From: Nikula, Jani Sent: Monday, January 9, 2017 2:30 PM To: Yadav, Jyoti R <jyoti.r.ya...@intel.com>; intel-gfx@lists.freedesktop.org Cc: Kahola, Mika <