From: Brad Volkin
This adds a small module for managing a pool of batch buffers.
The only current use case is for the command parser, as described
in the kerneldoc in the patch. The code is simple, but separating
it out makes it easier to change the underlying algorithms and to
extend to future u
From: Brad Volkin
Previously we couldn't trust the user-supplied batch length because
it came directly from userspace (i.e. untrusted code). It would have
affected what commands software parsed without regard to what hardware
would actually execute, leaving a potential hole.
With the parser now
From: Brad Volkin
Move it to a separate function since the main do_execbuffer function
already has so much going on.
Signed-off-by: Brad Volkin
---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 136 +
1 file changed, 79 insertions(+), 57 deletions(-)
diff --git a/dr
From: Brad Volkin
By adding a new exec_entry flag, we cleanly mark the shadow objects
as purgeable after they are on the active list.
Signed-off-by: Brad Volkin
---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/driver
From: Brad Volkin
This is v4 of the series I sent here:
http://lists.freedesktop.org/archives/intel-gfx/2014-November/054733.html
This version incorporates most of the feedback from v3. The couple of things
that I missed (mostly for timing reasons) are:
* Move 'pending_read_domains |= I915_GEM_D
From: Brad Volkin
This patch sets up all of the tracking and copying necessary to
use batch pools with the command parser and dispatches the copied
(shadow) batch to the hardware.
After this patch, the parser is in 'enabling' mode.
Note that performance takes a hit from the copy in some cases
a
From: Brad Volkin
To better account for the potentially large memory consumption
of the batch pool.
Signed-off-by: Brad Volkin
---
drivers/gpu/drm/i915/i915_debugfs.c | 45 +
1 file changed, 36 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915
From: Brad Volkin
It provides some useful information about the buffers in
the global command parser batch pool.
v2: rebase on global pool instead of per-ring pools
v3: rebase
Signed-off-by: Brad Volkin
---
drivers/gpu/drm/i915/i915_debugfs.c | 41 +
1 fil
From: Brad Volkin
This test has a few checks that batch buffer addresses in the error
state match the expected address for the userspace supplied batch.
But the batch buffer copy piece of the command parser means that
the logged addresses are actually _supposed_ to be different. So
skip just th
From: Brad Volkin
The size of the batch buffer passed to the kernel is significantly
larger than the size of the batch buffer passed to the function. A
proposed optimization as part of the batch copy kernel series is to
use batch_len for the copy and parse operations, which leads to a
false "batc
From: Brad Volkin
The command parser's batch_len optimization causes the parser to
reject this batch as not having an MI_BATCH_BUFFER_END because
the length was not set correctly.
Signed-off-by: Brad Volkin
---
tests/gem_madvise.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/gem_m
From: Brad Volkin
This patch sets up all of the tracking and copying necessary to
use batch pools with the command parser and dispatches the copied
(shadow) batch to the hardware.
After this patch, the parser is in 'enabling' mode.
Note that performance takes a hit from the copy in some cases
a
From: Brad Volkin
This adds a small module for managing a pool of batch buffers.
The only current use case is for the command parser, as described
in the kerneldoc in the patch. The code is simple, but separating
it out makes it easier to change the underlying algorithms and to
extend to future u
From: Brad Volkin
This is v3 of the series I sent here:
http://lists.freedesktop.org/archives/intel-gfx/2014-July/048705.html
Most of the previous commentary still applies. We've fixed the secure
dispatch regression though, so the series now puts the parser into
enabling mode in patch 2.
There
From: Brad Volkin
Previously we couldn't trust the user-supplied batch length because
it came directly from userspace (i.e. untrusted code). It would have
affected what commands software parsed without regard to what hardware
would actually execute, leaving a potential hole.
With the parser now
From: Brad Volkin
It provides some useful information about the buffers in
the global command parser batch pool.
v2: rebase on global pool instead of per-ring pools
v3: rebase
Signed-off-by: Brad Volkin
---
drivers/gpu/drm/i915/i915_debugfs.c | 41 +
1 fil
From: Brad Volkin
To better account for the potentially large memory consumption
of the batch pool.
Signed-off-by: Brad Volkin
---
drivers/gpu/drm/i915/i915_debugfs.c | 45 +
1 file changed, 36 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915
From: Brad Volkin
libva uses chained batch buffers in a way that the command parser
can't generally handle. Fortunately, libva doesn't need to write
registers from batch buffers in the way that mesa does, so this
patch causes the driver to fall back to non-secure dispatch if
the parser detects a
From: Brad Volkin
The size of the batch buffer passed to the kernel is significantly
larger than the size of the batch buffer passed to the function. A
proposed optimization as part of the batch copy kernel series is to
use batch_len for the copy and parse operations, which leads to a
false "batc
From: Brad Volkin
libva makes extensive use of chained batch buffers. The batch
buffer copy portion of the command parser has the potential to
break chained batches, so add a simple test to make sure that
doesn't happen.
Signed-off-by: Brad Volkin
---
lib/intel_reg.h| 1 +
tests/gem_
From: Brad Volkin
Ring init and cleanup are not balanced because we re-init the rings on
resume without having cleaned them up on suspend. This leads to the
driver leaking the parser's hash tables with a kmemleak signature such
as this:
unreferenced object 0x880405960980 (size 32):
comm "s
From: Brad Volkin
In commit
commit 896ab1a5d54269b463a24194c2e4a369103b46d8
Author: Daniel Vetter
Date: Wed Aug 6 15:04:51 2014 +0200
drm/i915: Fix up checks for aliasing ppgtt
it looks like we accidentally inverted the check that the command
parser should only run when the driver enabl
From: Brad Volkin
The other paths in the command parser that reject a batch all
log a message indicating the reason. We simply missed this one.
Signed-off-by: Brad Volkin
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/g
From: Brad Volkin
To better account for the potentially large memory consumption
of the batch pool.
Signed-off-by: Brad Volkin
---
drivers/gpu/drm/i915/i915_debugfs.c | 45 +
1 file changed, 36 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915
From: Brad Volkin
This adds a small module for managing a pool of batch buffers.
The only current use case is for the command parser, as described
in the kerneldoc in the patch. The code is simple, but separating
it out makes it easier to change the underlying algorithms and to
extend to future u
From: Brad Volkin
This patch sets up all of the tracking and copying necessary to
use batch pools with the command parser, but does not actually
dispatch the copied (shadow) batch to the hardware yet. We still
aren't quite ready to set the secure bit during dispatch.
Note that performance takes
From: Brad Volkin
Previously we couldn't trust the user-supplied batch length because
it came directly from userspace (i.e. untrusted code). It would have
affected what commands software parsed without regard to what hardware
would actually execute, leaving a potential hole.
With the parser now
From: Brad Volkin
It provides some useful information about the buffers in
the global command parser batch pool.
v2: rebase on global pool instead of per-ring pools
Signed-off-by: Brad Volkin
---
drivers/gpu/drm/i915/i915_debugfs.c | 41 +
1 file changed, 4
From: Brad Volkin
This adds a small module for managing a pool of batch buffers.
The only current use case is for the command parser, as described
in the kerneldoc in the patch. The code is simple, but separating
it out makes it easier to change the underlying algorithms and to
extend to future u
From: Brad Volkin
This is v2 of the series I sent here:
http://lists.freedesktop.org/archives/intel-gfx/2014-June/047609.html
I believe that I've addressed all of the feedback except
* I didn't move the allocation of the shadow batch buffer into parse_cmds(). It
didn't seem like it added much
From: Brad Volkin
This is useful for testing the batch pool code with aliasing PPGTT.
It doesn't work with full PPGTT though; the GPU hangs and the whole
UI is corrupted. We need fixes for the secure dispatch path to
enable this for real.
v2: rebase on shadow_batch_obj replacing batch_obj
Signe
From: Brad Volkin
This is useful for testing the batch pool code with aliasing PPGTT.
It doesn't work with full PPGTT though; the GPU hangs and the whole
UI is corrupted. We need fixes for the secure dispatch path to
enable this for real.
Signed-off-by: Brad Volkin
---
drivers/gpu/drm/i915/i91
From: Brad Volkin
This patch sets up all of the tracking and copying necessary to
use batch pools with the command parser, but does not actually
dispatch the copied (shadow) batch to the hardware yet. We still
aren't quite ready to set the secure bit during dispatch.
Note that performance takes
From: Brad Volkin
This adds a small module for managing a pool of batch buffers.
The only current use case is for the command parser, as described
in the kerneldoc in the patch. The code is simple, but separating
it out makes it easier to change the underlying algorithms and to
extend to future u
From: Brad Volkin
It provides some useful information about the buffers in
the per-ring command parser batch pools.
Signed-off-by: Brad Volkin
---
drivers/gpu/drm/i915/i915_debugfs.c | 48 +
1 file changed, 48 insertions(+)
diff --git a/drivers/gpu/drm/i915
From: Brad Volkin
This series is what I have so far on the batch copy aspect of the
command parser. The individual patches and kerneldoc have details.
It doesn't work with full ppgtt at the moment, so isn't ready for
merge. But I'd like to get feedback on the direction and particularly
whether I'
From: Brad Volkin
Beignet needs these in order to program the L3 cache config for
OpenCL workloads, particularly when using SLM.
Signed-off-by: Brad Volkin
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 3 +++
drivers/gpu/drm/i915/i915_reg.h| 2 ++
2 files changed, 5 insertions(+)
diff
From: Brad Volkin
This extends use of the command parser to VLV.
Note that the patch checks that the PPGTT bit is set appropriately when
PPGTT is enabled but ignores it when PPGTT is disabled. It would be
awkward to correctly invert the expected value to check that the bit is
set appropriately i
From: Brad Volkin
The command parser in newer kernels will reject it and setting this
bit is not required for the actual test case.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76670
Signed-off-by: Brad Volkin
---
This is a resend of
http://lists.freedesktop.org/archives/intel-gfx/20
From: Brad Volkin
For clients that submit large batch buffers the command parser has
a substantial impact on performance. On my HSW ULT system performance
drops as much as ~20% on some tests. Most of the time is spent in the
command lookup code. Converting that from the current naive search to
a
From: Brad Volkin
For clients that submit large batch buffers the command parser has
a substantial impact on performance. On my HSW ULT system performance
drops as much as ~20% on some tests. Most of the time is spent in the
command lookup code. Converting that from the current naive search to
a
From: Brad Volkin
Originally left out because it wasn't used. But it may be needed
and doesn't pose any risk, so add to the whitelist.
Signed-off-by: Brad Volkin
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 1 +
drivers/gpu/drm/i915/i915_reg.h| 1 +
2 files changed, 2 insertions(+)
di
From: Brad Volkin
These are additional registers needed for performance monitoring and
ARB_draw_indirect extensions in mesa.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76719
Cc: Kenneth Graunke
Signed-off-by: Brad Volkin
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 9 +
dr
From: Brad Volkin
The command parser in newer kernels will reject it and setting this
bit is not required for the actual test case.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76670
Signed-off-by: Brad Volkin
---
tests/gen7_forcewake_mt.c | 55 +--
From: Brad Volkin
There is some thought that the data from the performance counters enabled
via OACONTROL should only be available to the process that enabled counting.
To limit snooping, require that any batch buffer which sets OACONTROL to a
non-zero value also sets it back to 0 before the end
From: Brad Volkin
Signed-off-by: Brad Volkin
---
tests/gem_exec_parse.c | 48
1 file changed, 48 insertions(+)
diff --git a/tests/gem_exec_parse.c b/tests/gem_exec_parse.c
index 34d097d..853eb57 100644
--- a/tests/gem_exec_parse.c
+++ b/tests/ge
From: Brad Volkin
As suggested during review, this makes it much more obvious
when the tables are not sorted.
Cc: Jani Nikula
Signed-off-by: Brad Volkin
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 31 +--
1 file changed, 21 insertions(+), 10 deletions(-)
diff --g
From: Brad Volkin
Patches 1 and 2 do some cleanups suggested as part of the review process.
Patch 3 continues the OACONTROL handling fixes from the other day.
I think patches 1 and 2 are valuable on their own. I think the need/benefit
for the tracking provided by patch 3 is somewhat unclear. Per
From: Brad Volkin
There is some thought that the data from the performance counters enabled
via OACONTROL should only be available to the process that enabled counting.
To limit snooping, require that any batch buffer which sets OACONTROL to a
non-zero value also sets it back to 0 before the end
From: Brad Volkin
This brings the code a little more in line with kernel coding style.
Signed-off-by: Brad Volkin
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 136 +
1 file changed, 71 insertions(+), 65 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_cmd_pa
From: Brad Volkin
Signed-off-by: Brad Volkin
---
tests/gem_exec_parse.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/tests/gem_exec_parse.c b/tests/gem_exec_parse.c
index 9e90408..004c3bf 100644
--- a/tests/gem_exec_parse.c
+++ b/tests/gem_exec_parse.c
@@ -257,6 +257,15 @@ igt_m
From: Brad Volkin
The spec defines most of these commands as privileged. A few others,
like the semaphore mbox command and some display commands, are also
reserved for the driver's use. Subsequent patches relax some of
these restrictions.
v2: Rebased
Signed-off-by: Brad Volkin
---
drivers/gpu
From: Brad Volkin
PIPE_CONTROL and MI_FLUSH_DW have bits that would write to the
hardware status page. The driver stores request tracking info
there, so don't let userspace overwrite it.
v2: trailing comma fix, rebased
Signed-off-by: Brad Volkin
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 24
From: Brad Volkin
So userspace can query the kernel for command parser support.
v2: Add i915_cmd_parser_get_version(), history log, and kerneldoc
OTC-Tracker: AXIA-4631
Change-Id: I58af650db9f6753c2dcac9c54ab432fd31db302f
Signed-off-by: Brad Volkin
---
drivers/gpu/drm/i915/i915_cmd_parser.c |
From: Brad Volkin
MI_STORE_REGISTER_MEM, MI_LOAD_REGISTER_MEM, and MI_LOAD_REGISTER_IMM
commands allow userspace access to registers. Only certain registers
should be allowed for such access, so enable checking for those commands.
Each ring gets its own register whitelist.
MI_LOAD_REGISTER_REG o
From: Brad Volkin
The command parser is going to need the same synchronization and
setup logic, so factor it out for reuse.
v2: Add a check that the object is backed by shmem
Signed-off-by: Brad Volkin
---
drivers/gpu/drm/i915/i915_drv.h | 3 +++
drivers/gpu/drm/i915/i915_gem.c | 51
From: Brad Volkin
Signed-off-by: Brad Volkin
---
include/drm/i915_drm.h | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index 2f4eb8c..ba863c4 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -27,7 +27,7
From: Brad Volkin
Various commands that access memory have a bit to determine whether
the graphics address specified in the command should use the GGTT or
PPGTT for translation. These checks ensure that the bit indicates
PPGTT translation.
Most of these checks use the existing bit-checking infra
From: Brad Volkin
This is a speculative test in that it's not particularly relevant
today, but is important if we switch the parser implementation to
use kmap_atomic instead of vmap.
Signed-off-by: Brad Volkin
---
tests/gem_exec_parse.c | 68 ++
From: Brad Volkin
Signed-off-by: Brad Volkin
---
tests/gem_exec_parse.c | 81 ++
1 file changed, 81 insertions(+)
diff --git a/tests/gem_exec_parse.c b/tests/gem_exec_parse.c
index c71e478..ebf7116 100644
--- a/tests/gem_exec_parse.c
+++ b/tests/
From: Brad Volkin
The command parser scans batch buffers submitted via execbuffer ioctls before
the driver submits them to hardware. At a high level, it looks for several
things:
1) Commands which are explicitly defined as privileged or which should only be
used by the kernel driver. The pars
From: Brad Volkin
Start with a simple testcase that should pass.
v2: Switch to I915_PARAM_CMD_PARSER_VERSION
Signed-off-by: Brad Volkin
---
tests/.gitignore | 1 +
tests/Makefile.sources | 1 +
tests/gem_exec_parse.c | 140 +
3 files c
From: Brad Volkin
Signed-off-by: Brad Volkin
---
tests/gem_exec_parse.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/tests/gem_exec_parse.c b/tests/gem_exec_parse.c
index 48fde25..9e90408 100644
--- a/tests/gem_exec_parse.c
+++ b/tests/gem_exec_parse.c
@@ -145,6 +145,
From: Brad Volkin
Add command tables defining irregular length commands for each ring.
This requires a few new command opcode definitions.
v2: Whitespace adjustment in command definitions, sparse fix for !F
OTC-Tracker: AXIA-4631
Change-Id: I064bceb457e15f46928058352afe76d918c58ef5
Signed-off-b
From: Brad Volkin
Signed-off-by: Brad Volkin
---
tests/gem_exec_parse.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/tests/gem_exec_parse.c b/tests/gem_exec_parse.c
index ebf7116..48fde25 100644
--- a/tests/gem_exec_parse.c
+++ b/tests/gem_exec_parse.c
@@ -141
From: Brad Volkin
The Intel DDX uses these to implement scanline waits in the X server.
Signed-off-by: Brad Volkin
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c
b/drivers/gpu/drm/i915
From: Brad Volkin
Certain OpenGL features (e.g. transform feedback, performance monitoring)
require userspace code to submit batches containing commands such as
MI_LOAD_REGISTER_IMM to access various registers. Unfortunately, some
generations of the hardware will noop these commands in "unsecure"
From: Brad Volkin
v2: rebased
OTC-Tracker: AXIA-4631
Change-Id: I6747457e1fe7494bd42787af51198fcba398ad78
Signed-off-by: Brad Volkin
---
drivers/gpu/drm/i915/i915_params.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/
From: Brad Volkin
The driver leaves most interrupts masked during normal operation,
so there would have to be additional work to enable userspace to
safely request/receive an interrupt.
v2: trailing commas, rebased
Signed-off-by: Brad Volkin
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 22 +++
From: Brad Volkin
These registers are currently used by mesa for blitting,
transform feedback extensions, and performance monitoring
extensions.
v2: REG64 macro
Signed-off-by: Brad Volkin
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 45 ++
drivers/gpu/drm/i915/
From: Brad Volkin
These are used to implement scanline waits in the X server.
v2: Use #defines instead of magic numbers
Signed-off-by: Brad Volkin
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 29 +
drivers/gpu/drm/i915/i915_reg.h| 6 ++
2 files changed
From: Brad Volkin
This is a speculative test in that it's not particularly relevant
today, but is important if we switch the parser implementation to
use kmap_atomic instead of vmap.
Signed-off-by: Brad Volkin
---
tests/gem_exec_parse.c | 68 ++
From: Brad Volkin
Signed-off-by: Brad Volkin
---
tests/gem_exec_parse.c | 81 ++
1 file changed, 81 insertions(+)
diff --git a/tests/gem_exec_parse.c b/tests/gem_exec_parse.c
index c71e478..ebf7116 100644
--- a/tests/gem_exec_parse.c
+++ b/tests/
From: Brad Volkin
MI_STORE_REGISTER_MEM, MI_LOAD_REGISTER_MEM, and MI_LOAD_REGISTER_IMM
commands allow userspace access to registers. Only certain registers
should be allowed for such access, so enable checking for those commands.
Each ring gets its own register whitelist.
MI_LOAD_REGISTER_REG o
From: Brad Volkin
Signed-off-by: Brad Volkin
---
tests/gem_exec_parse.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/tests/gem_exec_parse.c b/tests/gem_exec_parse.c
index ebf7116..48fde25 100644
--- a/tests/gem_exec_parse.c
+++ b/tests/gem_exec_parse.c
@@ -141
From: Brad Volkin
Signed-off-by: Brad Volkin
---
include/drm/i915_drm.h | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index 2f4eb8c..ba863c4 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -27,7 +27,7
From: Brad Volkin
Signed-off-by: Brad Volkin
---
tests/gem_exec_parse.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/tests/gem_exec_parse.c b/tests/gem_exec_parse.c
index 9e90408..004c3bf 100644
--- a/tests/gem_exec_parse.c
+++ b/tests/gem_exec_parse.c
@@ -257,6 +257,15 @@ igt_m
From: Brad Volkin
Signed-off-by: Brad Volkin
---
tests/gem_exec_parse.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/tests/gem_exec_parse.c b/tests/gem_exec_parse.c
index 48fde25..9e90408 100644
--- a/tests/gem_exec_parse.c
+++ b/tests/gem_exec_parse.c
@@ -145,6 +145,
From: Brad Volkin
Start with a simple testcase that should pass.
v2: Switch to I915_PARAM_CMD_PARSER_VERSION
Signed-off-by: Brad Volkin
---
tests/.gitignore | 1 +
tests/Makefile.sources | 1 +
tests/gem_exec_parse.c | 140 +
3 files c
From: Brad Volkin
PIPE_CONTROL and MI_FLUSH_DW have bits that would write to the
hardware status page. The driver stores request tracking info
there, so don't let userspace overwrite it.
Signed-off-by: Brad Volkin
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 30 ++
From: Brad Volkin
Various commands that access memory have a bit to determine whether
the graphics address specified in the command should use the GGTT or
PPGTT for translation. These checks ensure that the bit indicates
PPGTT translation.
Most of these checks use the existing bit-checking infra
From: Brad Volkin
The Intel DDX uses these to implement scanline waits in the X server.
Signed-off-by: Brad Volkin
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c
b/drivers/gpu/drm/i915
From: Brad Volkin
Add command tables defining irregular length commands for each ring.
This requires a few new command opcode definitions.
OTC-Tracker: AXIA-4631
Change-Id: I064bceb457e15f46928058352afe76d918c58ef5
Signed-off-by: Brad Volkin
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 157 +++
From: Brad Volkin
The command parser scans batch buffers submitted via execbuffer ioctls before
the driver submits them to hardware. At a high level, it looks for several
things:
1) Commands which are explicitly defined as privileged or which should only be
used by the kernel driver. The pars
From: Brad Volkin
So userspace can query the kernel for command parser support.
OTC-Tracker: AXIA-4631
Change-Id: I58af650db9f6753c2dcac9c54ab432fd31db302f
Signed-off-by: Brad Volkin
---
drivers/gpu/drm/i915/i915_dma.c | 4
include/uapi/drm/i915_drm.h | 1 +
2 files changed, 5 inserti
From: Brad Volkin
The command parser is going to need the same synchronization and
setup logic, so factor it out for reuse.
Signed-off-by: Brad Volkin
---
drivers/gpu/drm/i915/i915_drv.h | 3 +++
drivers/gpu/drm/i915/i915_gem.c | 48 +
2 files changed,
From: Brad Volkin
OTC-Tracker: AXIA-4631
Change-Id: I6747457e1fe7494bd42787af51198fcba398ad78
Signed-off-by: Brad Volkin
---
drivers/gpu/drm/i915/i915_params.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915
From: Brad Volkin
The driver leaves most interrupts masked during normal operation,
so there would have to be additional work to enable userspace to
safely request/receive an interrupt.
Signed-off-by: Brad Volkin
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 25 +++--
driver
From: Brad Volkin
The spec defines most of these commands as privileged. A few others,
like the semaphore mbox command and some display commands, are also
reserved for the driver's use. Subsequent patches relax some of
these restrictions.
Signed-off-by: Brad Volkin
---
drivers/gpu/drm/i915/i91
From: Brad Volkin
Certain OpenGL features (e.g. transform feedback, performance monitoring)
require userspace code to submit batches containing commands such as
MI_LOAD_REGISTER_IMM to access various registers. Unfortunately, some
generations of the hardware will noop these commands in "unsecure"
From: Brad Volkin
These are used to implement scanline waits in the X server.
Signed-off-by: Brad Volkin
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c
b/drivers/gpu/drm/i915
From: Brad Volkin
These registers are currently used by mesa for blitting,
transform feedback extensions, and performance monitoring
extensions.
Signed-off-by: Brad Volkin
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 55 ++
drivers/gpu/drm/i915/i915_reg.h
From: Brad Volkin
Signed-off-by: Brad Volkin
---
tests/gem_exec_parse.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/tests/gem_exec_parse.c b/tests/gem_exec_parse.c
index b34fe1b..d4136db 100644
--- a/tests/gem_exec_parse.c
+++ b/tests/gem_exec_parse.c
@@ -141
From: Brad Volkin
Signed-off-by: Brad Volkin
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c
b/drivers/gpu/drm/i915/i915_cmd_parser.c
index 5593740..adc7d94 100644
--- a/drivers/gpu/drm/i
From: Brad Volkin
Signed-off-by: Brad Volkin
---
tests/gem_exec_parse.c | 81 ++
1 file changed, 81 insertions(+)
diff --git a/tests/gem_exec_parse.c b/tests/gem_exec_parse.c
index a17929f..b34fe1b 100644
--- a/tests/gem_exec_parse.c
+++ b/tests/
From: Brad Volkin
Signed-off-by: Brad Volkin
---
include/drm/i915_drm.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index c1914d6..525dc27 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -306,6 +306,7 @@ typedef struct
From: Brad Volkin
Start with a simple testcase that should pass.
Signed-off-by: Brad Volkin
---
tests/.gitignore | 1 +
tests/Makefile.sources | 1 +
tests/gem_exec_parse.c | 140 +
3 files changed, 142 insertions(+)
create mode 100644
From: Brad Volkin
Signed-off-by: Brad Volkin
---
tests/gem_exec_parse.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/tests/gem_exec_parse.c b/tests/gem_exec_parse.c
index d4136db..0eb328c 100644
--- a/tests/gem_exec_parse.c
+++ b/tests/gem_exec_parse.c
@@ -145,6 +145,
From: Brad Volkin
OTC-Tracker: AXIA-4631
Change-Id: Id178f67338d00c23ca4e8fc9499313dba93d2c5c
Signed-off-by: Brad Volkin
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 34 +
drivers/gpu/drm/i915/i915_drv.h | 3 +++
drivers/gpu/drm/i915/intel_ringbuffer.c
From: Brad Volkin
These checks prevent userspace from using certain commands to
access registers or generate interrupts.
OTC-Tracker: AXIA-4631
Change-Id: Ic6367ae98272495ba874c22abd4824fbced0abca
Signed-off-by: Brad Volkin
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 41 ++
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