On Tue, Oct 29, 2019 at 02:00:27AM -0600, Jonathan Corbet wrote:
> On Tue, 29 Oct 2019 08:31:22 +0800
> Changbin Du wrote:
>
> > Here python is different from C. Both empty string and None are False in
> > python.
> > Note such condition is common in python.
>
&g
On Mon, Oct 28, 2019 at 11:24:22AM +0200, Jani Nikula wrote:
> On Fri, 25 Oct 2019, Changbin Du wrote:
> > On Fri, Oct 25, 2019 at 09:57:48AM +0300, Jani Nikula wrote:
> >> On Thu, 24 Oct 2019, Jonathan Corbet wrote:
> >> > On Sun, 20 Oct 2019 21:17:17 +
On Fri, Oct 25, 2019 at 09:57:48AM +0300, Jani Nikula wrote:
> On Thu, 24 Oct 2019, Jonathan Corbet wrote:
> > On Sun, 20 Oct 2019 21:17:17 +0800
> > Changbin Du wrote:
> >
> >> The 'functions' directive is not only for functions, but also works for
> >> st
are updated.
Signed-off-by: Changbin Du
---
v2:
o use 'identifiers' as the new directive name.
---
Documentation/doc-guide/kernel-doc.rst | 29 ++
Documentation/sphinx/kerneldoc.py | 19 ++---
2 files changed, 28 insertions(+), 20 deletions(-)
diff --git
those things separately, but it does cover
> all the things we do allow to be individually documented.
--
Cheers,
Changbin Du
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On Tue, Oct 15, 2019 at 12:27:26PM -0600, Jonathan Corbet wrote:
> On Sun, 13 Oct 2019 13:53:59 +0800
> Changbin Du wrote:
>
> > The 'functions' directive is not only for functions, but also works for
> > structs/unions. So the name is misleading. This patch renames it to
&
message.
Signed-off-by: Changbin Du
---
Documentation/PCI/pci.rst | 4 +-
Documentation/core-api/boot-time-mm.rst | 2 +-
Documentation/core-api/debug-objects.rst | 14 +-
Documentation/core-api/genalloc.rst | 34 +--
Documentation/core-api/generic
From: Changbin Du <changbin...@intel.com>
This adds a new vGPU cap info bit VGT_CAPS_HUGE_GTT, which is to detect
whether the host supports shadowing of huge gtt pages. If host does
support it, remove the page sizes restriction for vGPU.
Signed-off-by: Changbin Du <changbin...@
From: Changbin Du <changbin...@intel.com>
Don't forget to free allocated spt if shadowing failed.
Signed-off-by: Changbin Du <changbin...@intel.com>
---
drivers/gpu/drm/i915/gvt/gtt.c | 33 +
1 file changed, 21 insertions(+), 12 deletions(-)
diff --g
From: Changbin Du <changbin...@intel.com>
This add 2M huge gtt support for GVTg. Unlike 64K gtt entry, we can
shadow 2M guest entry with real huge gtt. But before that, we have to
check memory physical continuous, alignment and if it is supported on
the host. We can get all supported page
From: Changbin Du <changbin...@intel.com>
We need a interface to allocate a pure shadow page which doesn't have
a guest page associated with. Such shadow page is used to shadow 2M
huge gtt entry.
Signed-off-by: Changbin Du <changbin...@intel.com>
---
drivers/gpu/drm/i915/gv
From: Changbin Du <changbin...@intel.com>
If the guest update the 64K gtt entry before changing IPS bit of PDE, we
need to re-shadow the whole page table. Because we have ignored all
updates to unused entries.
Signed-off-by: Changbin Du <changbin...@intel.com>
---
drivers/gpu/drm/i9
From: Changbin Du <changbin...@intel.com>
Add clear_pse operation in case we need to split huge gtt into small pages.
v2: correct description.
Signed-off-by: Changbin Du <changbin...@intel.com>
---
drivers/gpu/drm/i915/gvt/gtt.c | 19 +++
drivers/gpu/drm/i915/gv
From: Changbin Du <changbin...@intel.com>
This add a software PTE flag on the Ignored bit of PTE. It will be used
to identify splited 64K shadow entries.
v2: fix mask definition.
Signed-off-by: Changbin Du <changbin...@intel.com>
---
drivers/gpu/drm/i915/gv
From: Changbin Du <changbin...@intel.com>
The register RENDER_HWS_PGA_GEN7 is renamed to GEN8_GAMW_ECO_DEV_RW_IA
from GEN8 which can control IPS enabling.
v2: IPS of all engines must be enabled together for gen9.
Signed-off-by: Changbin Du <changbin...@intel.com>
---
drivers/gpu/
From: Changbin Du <changbin...@intel.com>
Add huge gtt shadowing for GVT. This will alow huge gtt feature turned on for
vGPU.
v6:
o Split changes of last patch in i915 side into a separated patch.
v5:
o IPS of all engines must be enabled together for gen9.
o Coding style improvme
From: Changbin Du <changbin...@intel.com>
Add a new entry type GTT_TYPE_PPGTT_PTE_64K_ENTRY. 64K entry is very
different from 2M/1G entry. 64K entry is controlled by IPS bit in upper
PDE. To leverage the current logic, I take IPS bit as 'PSE' for PTE
level. Which means, 64K entries ca
From: Changbin Du <changbin...@intel.com>
Now GVTg supports shadowing both 2M/64K huge gtt pages. So let's turn on
the cap info bit VGT_CAPS_HUGE_GTT.
v2: Split changes in i915 side into a separated patch.
Signed-off-by: Changbin Du <changbin...@intel.com>
---
drivers/gpu/drm/i91
From: Changbin Du <changbin...@intel.com>
Add three IPS operation functions to test/set/clear IPS in PDE.
Signed-off-by: Changbin Du <changbin...@intel.com>
---
drivers/gpu/drm/i915/gvt/gtt.c | 18 ++
drivers/gpu/drm/i915/gvt/gtt.h | 2 ++
2 files changed, 2
From: Changbin Du <changbin...@intel.com>
64K PTE is special, only PTE#0, PTE#16, PTE#32, ... PTE#496 are used in
the page table.
Signed-off-by: Changbin Du <changbin...@intel.com>
---
drivers/gpu/drm/i915/gvt/gtt.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
From: Changbin Du <changbin...@intel.com>
Finally, this add the first huge gtt support for GVTg - 64K pages. Since
64K page and 4K page cannot be mixed on the same page table, so we always
split a 64K entry into small 4K page. And when unshadow guest 64K entry,
we need ensure all the sh
From: Changbin Du <changbin...@intel.com>
To support huge gtt, we need to support huge pages in kvmgt first.
This patch adds a 'size' param to the intel_gvt_mpt::dma_map_guest_page
API and implements it in kvmgt.
v2: rebase.
Signed-off-by: Changbin Du <changbin...@intel.com>
---
From: Changbin Du <changbin...@intel.com>
This change help us detect the real entry type per PSE and IPS setting.
For 64K entry, we also need to check reg GEN8_GAMW_ECO_DEV_RW_IA.
Signed-off-by: Changbin Du <changbin...@intel.com>
---
drivers/gpu/drm/i915/gv
From: Changbin Du <changbin...@intel.com>
If the guest update the 64K gtt entry before changing IPS bit of PDE, we
need to re-shadow the whole page table. Because we have ignored all
updates to unused entries.
Signed-off-by: Changbin Du <changbin...@intel.com>
---
drivers/gpu/drm/i9
From: Changbin Du <changbin...@intel.com>
Don't forget to free allocated spt if shadowing failed.
Signed-off-by: Changbin Du <changbin...@intel.com>
---
drivers/gpu/drm/i915/gvt/gtt.c | 33 +
1 file changed, 21 insertions(+), 12 deletions(-)
diff --g
From: Changbin Du <changbin...@intel.com>
This add 2M huge gtt support for GVTg. Unlike 64K gtt entry, we can
shadow 2M guest entry with real huge gtt. But before that, we have to
check memory physical continuous, alignment and if it is supported on
the host. We can get all supported page
From: Changbin Du <changbin...@intel.com>
This add a software PTE flag on the Ignored bit of PTE. It will be used
to identify splited 64K shadow entries.
v2: fix mask definition.
Signed-off-by: Changbin Du <changbin...@intel.com>
---
drivers/gpu/drm/i915/gv
From: Changbin Du <changbin...@intel.com>
Now GVTg supports shadowing both 2M/64K huge gtt pages. So this is to
remove the restriction on guest side.
To be compatible with old host kernel, we defined a new cap info bit
VGT_CAPS_HUGE_GTT.
Cc: Zhenyu Wang <zhen...@linux.intel.com>
From: Changbin Du <changbin...@intel.com>
64K PTE is special, only PTE#0, PTE#16, PTE#32, ... PTE#496 are used in
the page table.
Signed-off-by: Changbin Du <changbin...@intel.com>
---
drivers/gpu/drm/i915/gvt/gtt.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
From: Changbin Du <changbin...@intel.com>
To support huge gtt, we need to support huge pages in kvmgt first.
This patch adds a 'size' param to the intel_gvt_mpt::dma_map_guest_page
API and implements it in kvmgt.
v2: rebase.
Signed-off-by: Changbin Du <changbin...@intel.com>
---
From: Changbin Du <changbin...@intel.com>
We need a interface to allocate a pure shadow page which doesn't have
a guest page associated with. Such shadow page is used to shadow 2M
huge gtt entry.
Signed-off-by: Changbin Du <changbin...@intel.com>
---
drivers/gpu/drm/i915/gv
From: Changbin Du <changbin...@intel.com>
Add clear_pse operation in case we need to split huge gtt into small pages.
v2: correct description.
Signed-off-by: Changbin Du <changbin...@intel.com>
---
drivers/gpu/drm/i915/gvt/gtt.c | 19 +++
drivers/gpu/drm/i915/gv
From: Changbin Du <changbin...@intel.com>
Add a new entry type GTT_TYPE_PPGTT_PTE_64K_ENTRY. 64K entry is very
different from 2M/1G entry. 64K entry is controlled by IPS bit in upper
PDE. To leverage the current logic, I take IPS bit as 'PSE' for PTE
level. Which means, 64K entries ca
From: Changbin Du <changbin...@intel.com>
This change help us detect the real entry type per PSE and IPS setting.
For 64K entry, we also need to check reg GEN8_GAMW_ECO_DEV_RW_IA.
Signed-off-by: Changbin Du <changbin...@intel.com>
---
drivers/gpu/drm/i915/gv
From: Changbin Du <changbin...@intel.com>
The register RENDER_HWS_PGA_GEN7 is renamed to GEN8_GAMW_ECO_DEV_RW_IA
from GEN8 which can control IPS enabling.
v2: IPS of all engines must be enabled together for gen9.
Signed-off-by: Changbin Du <changbin...@intel.com>
---
drivers/gpu/
From: Changbin Du <changbin...@intel.com>
Add three IPS operation functions to test/set/clear IPS in PDE.
Signed-off-by: Changbin Du <changbin...@intel.com>
---
drivers/gpu/drm/i915/gvt/gtt.c | 18 ++
drivers/gpu/drm/i915/gvt/gtt.h | 2 ++
2 files changed, 2
From: Changbin Du <changbin...@intel.com>
Add huge gtt shadowing for GVT. This will alow huge gtt feature turned on for
vGPU.
v5:
o IPS of all engines must be enabled together for gen9.
o Coding style improvment.
v4:
o Make first patch bisectable.
v3:
o rebase.
v2:
o fix comment
From: Changbin Du <changbin...@intel.com>
Finally, this add the first huge gtt support for GVTg - 64K pages. Since
64K page and 4K page cannot be mixed on the same page table, so we always
split a 64K entry into small 4K page. And when unshadow guest 64K entry,
we need ensure all the sh
From: Changbin Du <changbin...@intel.com>
Our QA reported a problem caused by movntdqa instructions. Currently,
the KVM hypervisor doesn't support VEX-prefix instructions emulation.
If users passthrough a GPU to guest with vfio option 'x-no-mmap=on',
then all access to the BARs will be t
From: Changbin Du <changbin...@intel.com>
Our QA reported a problem caused by movntdqa instructions. Currently,
the KVM hypervisor doesn't support VEX-prefix instructions emulation.
If users passthrough a GPU to guest with vfio option 'x-no-mmap=on',
then all access to the BARs will be t
From: Changbin Du <changbin...@intel.com>
It mistakenly set debugfs root path to "/debug/dri", so correct it.
Signed-off-by: Changbin Du <changbin...@intel.com>
---
overlay/debugfs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/overlay/debugfs.c b/o
From: Changbin Du <changbin...@intel.com>
Just found this is a useful introduction about User command
execution, so add it to doc-tree.
Signed-off-by: Changbin Du <changbin...@intel.com>
---
Documentation/gpu/i915.rst | 6 ++
1 file changed, 6 insertions(+)
diff --git a/Docum
From: Changbin Du <changbin...@intel.com>
In the past, vGPU alloc fence registers by walking through mm.fence_list
to find fence which pin_count = 0 and vma is empty. vGPU may not find
enough fence registers this way. Because a fence can be bind to vma even
though it is not in using. W
From: Changbin Du <changbin...@intel.com>
In the past, vGPU alloc fence registers by walking through mm.fence_list
to find fence which pin_count = 0 and vma is empty. vGPU may not find
enough fence registers this way. Because a fence can be bind to vma even
though it is not in using. W
From: Changbin Du <changbin...@intel.com>
In the past, vGPU alloc fence registers by walking through mm.fence_list
to find fence which pin_count = 0 and vma is empty. vGPU may not find
enough fence registers this way. Because a fence can be bind to vma even
though it is not in using. W
From: Changbin Du <changbin...@intel.com>
At least we need one MPT module (currently only have one) selected
to get GVTg functional. When GVTg is enabled while no MPT selected,
the build just includes useless GVTg code. This doesn't make sense.
With this patch, a submenut is created unde
From: Changbin Du <changbin...@intel.com>
GVTg has introduced the context status notifier to schedule the GVTg
workload. At that time, the notifier is bound to GVTg context only,
so GVTg is not aware of host workloads.
Now we are going to improve GVTg's guest workload scheduler policy,
a
From: Changbin Du <changbin...@intel.com>
GVTg has introduced the context status notifier to schedule the GVTg
workload. At that time, the notifier is bound to GVTg context only,
so GVTg is not aware of host workloads.
Now we are going to improve GVTg's guest workload scheduler policy,
a
From: Changbin Du <changbin...@intel.com>
hi, Daniel, Chris and All,
As you know, GVTg introduced the context status notifier to schedule
the GVTg workload. At that time, the notifier is bound to GVTg context
only, so GVTg is not aware of host workloads.
Now we are going to improve GVTg's
0x30
Signed-off-by: Changbin Du <changbin...@intel.com>
---
drivers/gpu/drm/i915/intel_lrc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 0a09024..81a9b0b 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
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