On 20/08/16 10:39 AM, Sagar Arun Kamble wrote:
Host to GuC actions should not be invoked when GuC isn't loaded hence
add early return in i915_guc_action if GuC load status is not SUCCESS.
Also, SLPC status has to be linked with GuC load status to make sure
SLPC actions get invoked when GuC is l
On 12/08/16 1:04 PM, Jani Nikula wrote:
On Fri, 12 Aug 2016, deepa...@linux.intel.com wrote:
From: Deepak S
With latest Punit FW, vgg input voltag drop falling to minimum is fixed.
So reverting the WA patch & moving to turbo freq opreation range to [RPn -> RP0]
IOW, this patch will
From: Deepak S
With latest Punit FW, vgg input voltag drop falling to minimum is fixed.
So reverting the WA patch & moving to turbo freq opreation range to [RPn -> RP0]
This is not a 1:1 revert of the commit 5b7c91b78b1ce6663e0f1f037f6cb4d7c9537d44.
You can refer to commit 5b5929cbe3f
to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/deepak-s-linux-intel-com/Revert-drm-i915-chv-Set-min-freq-to-efficient-frequency-on-chv/20160812-135320
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-x012-201632 (attached as
From: Deepak S
With latest Punit FW, vgg input voltag drop falling to minimum is fixed.
So reverting the WA patch & moving to turbo freq opreation range to [RPn -> RP0]
This reverts commit 5b7c91b78b1ce6663e0f1f037f6cb4d7c9537d44.
commit 5b7c91b78b1ce6663e0f1f037f6cb4d7c9537d44
Author:
From: Deepak S
With latest Punit FW, vgg input voltag drop falling to minimum is fixed.
So reverting the WA patch & moving to turbo freq opreation range to [RPn -> RP0]
This reverts commit 5b7c91b78b1ce6663e0f1f037f6cb4d7c9537d44.
commit 5b7c91b78b1ce6663e0f1f037f6cb4d7c9537d44
Author:
On Monday 11 May 2015 05:13 PM, Ville Syrjälä wrote:
On Sat, May 09, 2015 at 11:05:27AM +0530, Deepak S wrote:
On Friday 08 May 2015 09:35 PM, Ville Syrjälä wrote:
On Fri, May 08, 2015 at 08:19:12PM +0530, Deepak S wrote:
On Friday 10 April 2015 08:51 PM, ville.syrj...@linux.intel.com
From: Deepak S
After feedback from the hardware team, now we set the GPU min/idel freq to RPe.
Punit is expecting us to operate GPU between Rpe & Rp0. If we drop the
frequency to RPn, punit is failing to change the vgg input voltage to
minimum :(
Since Punit validates the rps range [RPe,
From: Deepak S
It is observed on BSW that requesting a new frequency from Punit
does nothing when the GPU is in rc6, and if we let GPU enter rc6
with a high frequency, Vnn remains slightly higher than at minimum
frequency. Extending vlv_set_rps_idle() workaround on CHV/BSW.
v2: Update commit
From: Deepak S
When GPU is idle on VLV, Request freq to punit should be good enough to
get the voltage back to VNN. Also, make sure gfx clock force applies
before requesting the freq fot vlv.
v2: Do forcewake before setting idle frequency (ville)
Update function comments to match the code
On Friday 08 May 2015 09:35 PM, Ville Syrjälä wrote:
On Fri, May 08, 2015 at 08:19:12PM +0530, Deepak S wrote:
On Friday 10 April 2015 08:51 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
Powergate the PHY lanes when they're not needed. For HDMI all four lanes
are n
On Friday 08 May 2015 10:09 PM, Ville Syrjälä wrote:
On Fri, May 08, 2015 at 08:43:12PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S
After feedback from the hardware team, now we set the GPU min/idel freq to RPe.
Punit is expecting us to operate GPU between Rpe & Rp0. If we
On Friday 08 May 2015 10:04 PM, Ville Syrjälä wrote:
On Fri, May 08, 2015 at 08:43:10PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S
When GPU is idle on VLV, Request freq to punit should be good enough to
get the voltage back to VNN. Also, make sure gfx clock force applies
before
From: Deepak S
After feedback from the hardware team, now we set the GPU min/idel freq to RPe.
Punit is expecting us to operate GPU between Rpe & Rp0. If we drop the
frequency to RPn, punit is failing to change the input voltage to
minimum :(
Since Punit validates the rps range [RPe, RP0].
From: Deepak S
It is obsered on BSW that requesting a new frequency from Punit
does nothing when the GPU is in rc6, and if we let it enter rc6 with a
high frequency Vnn also remains high. Extending vlv_set_rps_idle()
workaround on CHV/BSW.
suggested-by: Ville Syrjälä
Signed-off-by: Deepak S
From: Deepak S
When GPU is idle on VLV, Request freq to punit should be good enough to
get the voltage back to VNN. Also, make sure gfx clock force applies
before requesting the freq fot vlv.
v2: Do forcewake before setting idle frequency (ville)
Update function comments to match the code
On Wednesday 06 May 2015 02:32 PM, Daniel Vetter wrote:
On Tue, May 05, 2015 at 01:12:41PM +0530, Deepak S wrote:
On Monday 04 May 2015 08:58 PM, Ville Syrjälä wrote:
On Mon, May 04, 2015 at 10:12:23AM +0200, Daniel Vetter wrote:
On Mon, May 04, 2015 at 10:58:02AM +0530, Deepak S wrote
g pipe A sub system will also enable pipe B &
c"
Because it is confusing, We says pipe B and C wells don't actually exist,
then if we use PIPE B to drive. how is it working without powering up the well?
Other than this. patch looks fine
Reviewed-by: Deepak S
On Friday 10 April 2015 08:51 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
Powergate the PHY lanes when they're not needed. For HDMI all four lanes
are needed always, but for DP we can enable only the needed lanes. And
when the port is not used all lanes can be power gated. Th
r)
@@ -1636,7 +1636,7 @@ static void chv_hdmi_pre_enable(struct intel_encoder
*encoder)
intel_enable_hdmi(encoder);
- vlv_wait_port_ready(dev_priv, dport);
+ vlv_wait_port_ready(dev_priv, dport, 0x0);
}
static void intel_hdmi_destroy(struct drm_c
On Friday 08 May 2015 06:52 PM, Ville Syrjälä wrote:
On Fri, May 08, 2015 at 06:31:23PM +0530, Deepak S wrote:
On Friday 10 April 2015 08:51 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
Not sure which LDO programming sequence delay should be used for the CHV
PHY, but the
On Friday 08 May 2015 06:49 PM, Ville Syrjälä wrote:
On Fri, May 08, 2015 at 06:24:42PM +0530, Deepak S wrote:
On Friday 10 April 2015 08:51 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
Sometimes (exactly when is a bit unclear) DISPLAY_PHY_CONTROL appears to
get corrupted
On Friday 10 April 2015 08:51 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
Not sure which LDO programming sequence delay should be used for the CHV
PHY, but the spec says that 600ns is "Used by default for initial
bringup", and the BIOS seems to use that, so let's do the same.
CHV_DPIO_CMN_D_POWER_DOMAINS,
.data = PUNIT_POWER_WELL_DPIO_CMN_D,
.ops = &chv_dpio_cmn_power_well_ops,
},
Right, Issue is fixed with latest FW.
Reviewed-by: Deepak S
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop
is patch?
other than this, patch does what it says.
Reviewed-by: Deepak S
+#define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6*(phy)+3*(ch)+2))
+#define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy))
#define DISPLAY_PHY_STATUS (VLV_DISPLAY_BASE + 0x60104)
#define
TAGGER_STRAP(stagger) |
+ DPIO_LANESTAGGER_STRAP_OVRD |
+ DPIO_TX1_STAGGER_MASK(0x1f) |
+ DPIO_TX1_STAGGER_MULT(7) |
+ DPIO_TX2_STAGGER_MULT(5));
/* Clear calc init */
val = vlv_dpio_re
On Monday 04 May 2015 08:58 PM, Ville Syrjälä wrote:
On Mon, May 04, 2015 at 10:12:23AM +0200, Daniel Vetter wrote:
On Mon, May 04, 2015 at 10:58:02AM +0530, Deepak S wrote:
On Wednesday 29 April 2015 02:59 PM, Ville Syrjälä wrote:
On Wed, Apr 29, 2015 at 08:36:24AM +0530, deepa
On Wednesday 29 April 2015 02:59 PM, Ville Syrjälä wrote:
On Wed, Apr 29, 2015 at 08:36:24AM +0530, deepa...@linux.intel.com wrote:
From: Deepak S
Based on the spec, Setting up static BIAS for GPU to improve the
rps performace.
v2: rename reg defn to match spec. (Ville)
v3: Updated bias
On Thursday 30 April 2015 07:35 PM, Ville Syrjälä wrote:
On Thu, Apr 30, 2015 at 02:19:07PM +0300, Ville Syrjälä wrote:
On Thu, Apr 30, 2015 at 03:42:42PM +0530, Deepak S wrote:
As you suggested it would be better to extend the VLV WA to
CHV also to make sure we drop the voltage when idle
On Thursday 30 April 2015 01:23 AM, Ville Syrjälä wrote:
On Wed, Apr 29, 2015 at 06:31:56PM +0300, Ville Syrjälä wrote:
On Wed, Apr 29, 2015 at 08:23:21AM +0530, deepa...@linux.intel.com wrote:
From: Deepak S
After feedback from the hardware team, now we set the GPU min/idel freq to RPe
On Wednesday 29 April 2015 03:56 PM, Ville Syrjälä wrote:
On Wed, Apr 29, 2015 at 08:20:20AM +0530, Deepak S wrote:
On Wednesday 29 April 2015 12:02 AM, Ville Syrjälä wrote:
On Tue, Apr 28, 2015 at 11:16:29AM -0700, Jesse Barnes wrote:
On 03/04/2015 08:08 PM, deepa...@linux.intel.com wrote
From: Deepak S
Based on the spec, Setting up static BIAS for GPU to improve the
rps performace.
v2: rename reg defn to match spec. (Ville)
v3: Updated bias setting for chv (Deepak)
Signed-off-by: Deepak S
---
drivers/gpu/drm/i915/i915_reg.h | 6 ++
drivers/gpu/drm/i915/intel_pm.c | 12
From: Deepak S
After feedback from the hardware team, now we set the GPU min/idel freq to RPe.
Punit is expecting us to operate GPU between Rpe & Rp0. If we drop the
frequency to RPn, punit is failing to change the input voltage to
minimum :(
Since Punit validates the rps range [RPe, RP0].
From: Deepak S
Based on the spec, Setting up static BIAS for GPU to improve the
rps performace.
v2: rename reg defn to match spec. (Ville)
Signed-off-by: Deepak S
---
drivers/gpu/drm/i915/i915_reg.h | 5 +
drivers/gpu/drm/i915/intel_pm.c | 12
2 files changed, 17 insertions
On Wednesday 29 April 2015 12:02 AM, Ville Syrjälä wrote:
On Tue, Apr 28, 2015 at 11:16:29AM -0700, Jesse Barnes wrote:
On 03/04/2015 08:08 PM, deepa...@linux.intel.com wrote:
From: Deepak S
When GPU is idle on VLV, Request freq to punit should be good enough to
get the voltage back to VNN
On Tuesday 28 April 2015 11:46 PM, Jesse Barnes wrote:
Yeah I think this is fine (may need a rebase though, you can keep my r-b
if you do that in case Jani doesn't want to deal with the merge conflicts).
Reviewed-by: Jesse Barnes
Sure Jesse, I will rebase the patch.
Thanks
Deepak
___
On Monday 13 April 2015 05:40 PM, Ville Syrjälä wrote:
On Mon, Apr 13, 2015 at 02:55:12PM +0300, Jani Nikula wrote:
On Thu, 05 Mar 2015, deepa...@linux.intel.com wrote:
From: Deepak S
When GPU is idle on VLV, Request freq to punit should be good enough to
get the voltage back to VNN. Also
Yes agreed, we need to make changes in other paths :)
On Tuesday 28 April 2015 02:14 PM, Chris Wilson wrote:
On Tue, Apr 28, 2015 at 08:29:13AM +, S, Deepak wrote:
Thanks Chirs for review, We moved "Init_hw" to initialize WA's before any BB
submission.
Init_hw calls " init_clock_gating"
From: Deepak S
This WA is avoid problem between shadow vs wake FIFO unload
problem during CPD/RC6 transactions on CHV.
v2: Define individual bits GTFIFOCTL (Ville)
v3: move WA to uncore_early_sanitize (ville)
Signed-off-by: Deepak S
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915
On Thursday 16 April 2015 12:09 AM, Ville Syrjälä wrote:
On Wed, Apr 15, 2015 at 07:41:39PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S
This WA is avoid problem between shadow vs wake FIFO unload
problem during CPD/RC6 transactions on CHV.
v2: Define individual bits GTFIFOCTL
From: Deepak S
This WA is avoid problem between shadow vs wake FIFO unload
problem during CPD/RC6 transactions on CHV.
v2: Define individual bits GTFIFOCTL (Ville)
v3: move WA to uncore_early_sanitize (ville)
Signed-off-by: Deepak S
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers
On Wednesday 15 April 2015 04:48 PM, Ville Syrjälä wrote:
On Wed, Apr 15, 2015 at 02:16:18PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S
This WA is avoid problem between shadow vs wake FIFO unload
problem during CPD/RC6 transactions on CHV.
v2: Define individual bits GTFIFOCTL
From: Deepak S
This WA is avoid problem between shadow vs wake FIFO unload
problem during CPD/RC6 transactions on CHV.
v2: Define individual bits GTFIFOCTL (Ville)
Signed-off-by: Deepak S
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_pm.c | 5 +
2 files changed
On Tuesday 14 April 2015 04:29 PM, Ville Syrjälä wrote:
On Tue, Apr 14, 2015 at 03:58:54PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S
This WA disable usage of shadow register during CPD/RC6 transactions on
CHV
I suppose is a workaround for the shadow vs. wake FIFO problem
On Monday 13 April 2015 05:36 PM, Jani Nikula wrote:
On Thu, 19 Mar 2015, Daniel Vetter wrote:
On Thu, Mar 19, 2015 at 03:38:19PM +0200, David Weinehall wrote:
On Thu, Mar 19, 2015 at 06:17:00PM +0530, Deepak S wrote:
On Thursday 19 March 2015 05:14 PM, David Weinehall wrote:
On Thu, Mar
From: Deepak S
This WA disable usage of shadow register during CPD/RC6 transactions on
CHV
Signed-off-by: Deepak S
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 4
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu
On Tuesday 07 April 2015 02:02 PM, Chris Wilson wrote:
On Tue, Apr 07, 2015 at 10:20:15AM +0200, Daniel Vetter wrote:
On Thu, Apr 02, 2015 at 06:49:38PM +0530, Deepak S wrote:
On Monday 30 March 2015 09:13 PM, Daniel Vetter wrote:
On Mon, Mar 30, 2015 at 08:03:58PM +0530, deepa
From: Deepak S
Sometimes, i915 might call _wait_for when irq is disabled.
If the cpu is the main cpu to process jiffies, jiffies
wouldn't be increased as this cpu disables irq. Then,
time_after(jiffies, timeout__) becomes meaningless. If
gunit doesn't work now, kernel wouldn
From: Deepak S
Cleanup idr table if any error happens after __create_hw_context() in
i915_gem_create_context()
v2: add a new err_idr (Daniel)
Signed-off-by: Deepak S
---
drivers/gpu/drm/i915/i915_gem_context.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers
On Monday 30 March 2015 09:13 PM, Daniel Vetter wrote:
On Mon, Mar 30, 2015 at 08:03:58PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S
Cleanup idr table if any error happens after __create_hw_context() in
i915_gem_create_context()
Signed-off-by: Deepak S
---
drivers/gpu/drm
compensate for the RPS boosts.
v2: Rebase
v3: Exclude Cherrytrail as Deepak was concerned that the increased
number of register writes would wake the common powerwell too often.
Signed-off-by: Chris Wilson
Cc: Deepak S
Cc: Ville Syrjälä
Cc: Rodrigo Vivi
Cc: Daniel Vetter
---
drivers/gpu/drm
allowed to boost.
we may have to look at media workload. Last time when we observed that for
a 1080p HD clip GPU freq was staying at Rp0 most of the time.
Hopefully aggressive downclocking should help
Acked-by: Deepak S
Signed-off-by: Chris Wilson
Cc: Deepak S
Cc: Daniel Vetter
---
drivers/gpu
o, I do not see any race condition happening between diff Gfx force clk in
driver. Lets just drop it :)
Reviewed-by: Deepak S
val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
___
Intel-gfx m
and we'll still have "did it move" sanity check in the PM code to
warn us if something is still amiss.
Looks fine to me
Reviewed-by: Deepak S
References: https://bugs.freedesktop.org/show_bug.cgi?id=89611
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_drv.c | 2 ++
d
From: Deepak S
Cleanup idr table if any error happens after __create_hw_context() in
i915_gem_create_context()
Signed-off-by: Deepak S
---
drivers/gpu/drm/i915/i915_gem_context.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm
On Monday 30 March 2015 03:37 PM, Ville Syrjälä wrote:
On Sat, Mar 28, 2015 at 03:23:34PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S
On CHV, PUNIT team confirmed that 'VLV_GFX_CLK_STATUS_BIT' is not a
sticky bit and it will always be set. So ignore Check for previous
From: Deepak S
Based on the spec, Setting up static BIAS for GPU to improve the
rps performace.
Signed-off-by: Deepak S
---
drivers/gpu/drm/i915/i915_reg.h | 5 +
drivers/gpu/drm/i915/intel_pm.c | 12
2 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915
From: Deepak S
On CHV, PUNIT team confirmed that 'VLV_GFX_CLK_STATUS_BIT' is not a
sticky bit and it will always be set. So ignore Check for previous
Gfx force off during suspend and allow the force clk as part S0ix
Sequence
Signed-off-by: Deepak S
---
drivers/gpu/drm/i915/i915
From: Deepak S
After feedback from the hardware team we are changing the RC6
promotional timer to increase the power saving without
changing performance.
Signed-off-by: Deepak S
Reviewed-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_pm.c | 4 ++--
1 file changed, 2 insertions(+), 2
From: Deepak S
Adding few of PM fixes and Improvements for CHV/VLV.
Addressed few comments.
Deepak S (5):
drm/i915/chv: Remove Wait for a previous gfx force-off
drm/i915: Re-adjusting rc6 promotional timer for chv
drm/i915/chv: Set min freq to efficient frequency on chv
drm/i915/chv
From: Deepak S
After feedback from the hardware team, now we set the GPU min/idel freq to RPe.
Punit is expecting us to operate GPU between Rpe & Rp0. If we drop the
frequency to RPn, punit is failing to change the input voltage to
minimum :(
v2: Change commit message
v3: set min_freq be
From: Deepak S
On CHV, since Punit validates the rps range [RPe, RP0]. This patch
removes unused cherryview_rps_min_freq function.
Signed-off-by: Deepak S
---
drivers/gpu/drm/i915/intel_pm.c | 18 --
1 file changed, 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c
On Friday 27 March 2015 02:32 AM, Paulo Zanoni wrote:
2015-03-19 11:14 GMT-03:00 :
From: Deepak S
After feedback from the hardware team we are changing the RC6
promotional timer to increase the power saving without
changing performance.
I was told that my review comments were sent to the
On Friday 27 March 2015 03:13 AM, Chris Wilson wrote:
On Thu, Mar 26, 2015 at 06:32:15PM -0300, Paulo Zanoni wrote:
2015-03-19 11:14 GMT-03:00 :
From: Deepak S
After feedback from the hardware team, now we set the GPU min/idel freq to RPe.
Punit is expecting us to operate GPU between Rpe
On Tuesday 24 March 2015 01:13 AM, Paulo Zanoni wrote:
2015-02-26 12:16 GMT-03:00 :
From: Deepak S
After feedback from the hardware team we are changing the RC6
promotional timer to increase the power saving without
changing performance.
I can't really say whether this is really wh
From: Deepak S
On CHV, PUNIT team confirmed that 'VLV_GFX_CLK_STATUS_BIT' is not a
sticky bit and it will always be set. So ignore Check for previous
Gfx force off during suspend and allow the force clk as part S0ix
Sequence
Signed-off-by: Deepak S
---
drivers/gpu/drm/i915/i915
From: Deepak S
Based on the spec, Setting up static BIAS for GPU to improve the
rps performace.
Signed-off-by: Deepak S
---
drivers/gpu/drm/i915/i915_reg.h | 5 +
drivers/gpu/drm/i915/intel_pm.c | 12
2 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915
From: Deepak S
After feedback from the hardware team we are changing the RC6
promotional timer to increase the power saving without
changing performance.
Signed-off-by: Deepak S
---
drivers/gpu/drm/i915/intel_pm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers
From: Deepak S
Adding few of PM fixes and Improvements for CHV/VLV.
Addressed few comments.
Deepak S (4):
drm/i915/chv: Remove Wait for a previous gfx force-off
drm/i915: Re-adjusting rc6 promotional timer for chv
drm/i915/chv: Set min freq to efficient frequency on chv
drm/i915: Setup
From: Deepak S
After feedback from the hardware team, now we set the GPU min/idel freq to RPe.
Punit is expecting us to operate GPU between Rpe & Rp0. If we drop the
frequency to RPn, punit is failing to change the input voltage to
minimum :(
v2: Change commit message
Signed-off-by: Deep
On Thursday 19 March 2015 06:40 PM, Chris Wilson wrote:
On Thu, Mar 19, 2015 at 06:31:04PM +0530, Deepak S wrote:
should we skip put_fence in overlay_do_put_image ?
Ah interesting point you raise there. That is buggy code fullstop.
We should not be call put_fence if pin_to_display_plane pins
not mappable.
Signed-off-by: Chris Wilson
Cc: Satyanantha, Rama Gopal M
Cc: Deepak S
Cc: Damien Lespiau
Cc: Daniel Vetter
---
drivers/gpu/drm/i915/i915_gem.c | 7 ++-
drivers/gpu/drm/i915/intel_display.c | 23 +--
2 files changed, 19 insertions(+), 11
On Thursday 19 March 2015 05:14 PM, David Weinehall wrote:
On Thu, Mar 19, 2015 at 04:09:44PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S
Unfortunately WaGsvRC0ResidencyMethod causing system freeze on some
of the baytrail systems :(. Switching back to legacy mode rps.
Is there
On Thursday 19 March 2015 04:48 PM, Ville Syrjälä wrote:
On Thu, Mar 19, 2015 at 04:09:44PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S
Unfortunately WaGsvRC0ResidencyMethod causing system freeze on some
of the baytrail systems :(. Switching back to legacy mode rps.
Do we want to
Cc: Satyanantha, Rama Gopal M
Cc: Deepak S
Cc: Damien Lespiau
Cc: Daniel Vetter
---
drivers/gpu/drm/i915/i915_gem.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 9e498e0bbf22..9a1de848e450
From: Deepak S
Unfortunately WaGsvRC0ResidencyMethod causing system freeze on some
of the baytrail systems :(. Switching back to legacy mode rps.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88012
Signed-off-by: Deepak S
---
drivers/gpu/drm/i915/i915_irq.c | 6 +-
1 file changed
On Wednesday 18 March 2015 04:53 PM, Chris Wilson wrote:
On Wed, Mar 18, 2015 at 04:45:08PM +0530, Deepak S wrote:
+ if (val != dev_priv->rps.cur_freq) {
vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
+ gen6_set_rps_thresholds(dev_priv, val);
.
v3: Rename missed_vblank
v4: Rebase
v5: Cancel the outstanding work in runtime suspend
v6: Rebase
v7: Rebase required fixing
Signed-off-by: Chris Wilson
Cc: Daniel Vetter
Cc: Ville Syrjälä
Cc: Deepak S
---
drivers/gpu/drm/i915/intel_display.c | 11 ---
drivers/gpu/drm/i915/intel_
compensate for the RPS boosts.
v2: Rebase
Signed-off-by: Chris Wilson
Cc: Deepak S
Cc: Ville Syrjälä
Cc: Rodrigo Vivi
Cc: Daniel Vetter
---
drivers/gpu/drm/i915/i915_drv.h | 3 +++
drivers/gpu/drm/i915/i915_irq.c | 4 ++--
drivers/gpu/drm/i915/i915_reg.h | 2 --
drivers/gpu/drm/i915
idle_freq for vlv and add a bunch of WARNs
Signed-off-by: Chris Wilson
Cc: Deepak S
---
drivers/gpu/drm/i915/i915_debugfs.c | 6 +
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 44 +++--
3 files changed, 35 insertions
On Wednesday 18 March 2015 02:50 PM, Chris Wilson wrote:
On Wed, Mar 18, 2015 at 12:26:49PM +0530, Deepak S wrote:
On Friday 06 March 2015 08:36 PM, Chris Wilson wrote:
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_irq.c | 27 ---
1 file changed, 12
On Wednesday 18 March 2015 03:18 PM, Daniel Vetter wrote:
On Wed, Mar 18, 2015 at 01:42:58PM +0530, Deepak S wrote:
I guess your empty reply wasn't intentional?
-Daniel
Sorry, that was not intentional :)
On Friday 06 March 2015 08:36 PM, Chris Wilson wrote:
Reuse the same reclo
static void __intel_rps_boost_work(struct work_struct
*work)
struct request_boost *boost = container_of(work, struct request_boost,
work);
if (!i915_gem_request_completed(boost->rq, true))
- gen6_rps_boost(to_i915(boost->rq->ring->de
On Wednesday 18 March 2015 01:48 PM, Deepak S wrote:
On Friday 06 March 2015 08:36 PM, Chris Wilson wrote:
If we hit a vblank and see that have a pageflip queue but not yet
processed, ensure that the GPU is running at maximum in order to clear
the backlog. Pageflips are only queued for the
On Friday 06 March 2015 08:36 PM, Chris Wilson wrote:
If we hit a vblank and see that have a pageflip queue but not yet
processed, ensure that the GPU is running at maximum in order to clear
the backlog. Pageflips are only queued for the following vblank, if we
miss it, there will be a visible
compensate for the RPS boosts.
Signed-off-by: Chris Wilson
Cc: Deepak S
Cc: Ville Syrjälä
Cc: Rodrigo Vivi
Cc: Daniel Vetter
Conflicts:
drivers/gpu/drm/i915/intel_pm.c
---
drivers/gpu/drm/i915/i915_drv.h | 3 +++
drivers/gpu/drm/i915/i915_irq.c | 4 ++--
drivers/gpu/drm/i915
mask |= GEN6_PM_RP_UP_THRESHOLD;
+ mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
- mask |= dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED);
mask &= dev_priv->pm_rps_events;
return gen6_sanitize_rps_pm_mask(dev_priv, ~mas
On Friday 06 March 2015 08:36 PM, Chris Wilson wrote:
Rewrite commit 31685c258e0b0ad6aa486c5ec001382cf8a64212
Author: Deepak S
Date: Thu Jul 3 17:33:01 2014 -0400
drm/i915/vlv: WA for Turbo and RC6 to work together.
Other than code clarity, the major improvement is to disable the
Other than this. Patch looks fine
Reviewed-by: Deepak S
} else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
if (adj < 0)
adj *= 2;
- else {
- /* CHV needs even encode values */
On Friday 06 March 2015 08:36 PM, Chris Wilson wrote:
When we idle, we set the GPU frequency to the hardware minimum (not user
minimum). We introduce a new variable to distinguish between the
different roles, and to allow easy tuning of the idle frequency without
impacting over aspects of RPS.
On Friday 06 March 2015 08:36 PM, Chris Wilson wrote:
When we idle, we set the GPU frequency to the hardware minimum (not user
minimum). We introduce a new variable to distinguish between the
different roles, and to allow easy tuning of the idle frequency without
impacting over aspects of RPS.
On Friday 06 March 2015 10:10 PM, Daniel Vetter wrote:
On Thu, Mar 05, 2015 at 09:27:59PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S
In normal cases, RC6 promotion timer is 1700us/500us. This will
result in more time spent in C1 state. For more residency in
C6 in case of media
On Thursday 26 February 2015 09:12 PM, Deepak S wrote:
On Thursday 26 February 2015 09:13 PM, Ville Syrjälä wrote:
On Thu, Feb 26, 2015 at 08:46:54PM +0530, deepa...@linux.intel.com
wrote:
From: Deepak S
On CHV, PUNIT team confirmed that 'VLV_GFX_CLK_STATUS_BIT' is not a
sticky
On Wednesday 11 March 2015 07:36 PM, Chris Wilson wrote:
On Wed, Mar 11, 2015 at 07:23:48PM +0530, Deepak S wrote:
On Thursday 26 February 2015 09:42 PM, Chris Wilson wrote:
On Thu, Feb 26, 2015 at 08:46:56PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S
After feedback from the
On Wednesday 11 March 2015 07:26 PM, Chris Wilson wrote:
On Wed, Mar 11, 2015 at 07:07:12PM +0530, Deepak S wrote:
On Friday 06 March 2015 10:10 PM, Daniel Vetter wrote:
On Thu, Mar 05, 2015 at 09:27:59PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S
In normal cases, RC6
On Thursday 26 February 2015 09:42 PM, Chris Wilson wrote:
On Thu, Feb 26, 2015 at 08:46:56PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S
After feedback from the hardware team, now we set the GPU min freq to RPe.
If we drop the freq to RPn, we found that the punit was not setting
From: Deepak S
In normal cases, RC6 promotion timer is 1700us/500us. This will
result in more time spent in C1 state. For more residency in
C6 in case of media workloads, this is changed to 250us.
Not doing this for 3D workloads as too many C6-C0
transition delays can result in performance
From: Deepak S
We update the GT PM interrupts mask at the end of set rps. We observed even
though we are requesting a RPn or RP0, there is a chance to get a DOWN or UP
interrupts before interrupts mask. These extra interrupts are simply wasting
cpu cycles. In this patch we mask the interrupts
From: Deepak S
When GPU is idle on VLV, Request freq to punit should be good enough to
get the voltage back to VNN. Also, make sure gfx clock force applies
before requesting the freq fot vlv.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75244
suggested-by: Jesse Barnes
Signed-off-by
On Thursday 26 February 2015 09:38 PM, Chris Wilson wrote:
On Thu, Feb 26, 2015 at 08:46:57PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S
In normal cases, RC6 promotion timer is 1700us/500us. This will
result in more time spent in C1 state. For more residency in C6
in case of media
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