On 20/08/16 10:39 AM, Sagar Arun Kamble wrote:
Host to GuC actions should not be invoked when GuC isn't loaded hence
add early return in i915_guc_action if GuC load status is not SUCCESS.
Also, SLPC status has to be linked with GuC load status to make sure
SLPC actions get invoked when GuC is
On 12/08/16 1:04 PM, Jani Nikula wrote:
On Fri, 12 Aug 2016, deepa...@linux.intel.com wrote:
From: Deepak S <deepa...@linux.intel.com>
With latest Punit FW, vgg input voltag drop falling to minimum is fixed.
So reverting the WA patch & moving to turbo freq opreation range to [
From: Deepak S <deepa...@linux.intel.com>
With latest Punit FW, vgg input voltag drop falling to minimum is fixed.
So reverting the WA patch & moving to turbo freq opreation range to [RPn -> RP0]
This is not a 1:1 revert of the commit 5b7c91b78b1ce6663e0f1f037f6cb4d7c9537d44.
to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/deepak-s-linux-intel-com/Revert-drm-i915-chv-Set-min-freq-to-efficient-frequency-on-chv/20160812-135320
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-x012-201632 (attached
From: Deepak S <deepa...@linux.intel.com>
With latest Punit FW, vgg input voltag drop falling to minimum is fixed.
So reverting the WA patch & moving to turbo freq opreation range to [RPn -> RP0]
This reverts commit 5b7c91b78b1ce6663e0f1f037f6cb4d7c953
From: Deepak S <deepa...@linux.intel.com>
With latest Punit FW, vgg input voltag drop falling to minimum is fixed.
So reverting the WA patch & moving to turbo freq opreation range to [RPn -> RP0]
This reverts commit 5b7c91b78b1ce6663e0f1f037f6cb4d7c953
On Monday 11 May 2015 05:13 PM, Ville Syrjälä wrote:
On Sat, May 09, 2015 at 11:05:27AM +0530, Deepak S wrote:
On Friday 08 May 2015 09:35 PM, Ville Syrjälä wrote:
On Fri, May 08, 2015 at 08:19:12PM +0530, Deepak S wrote:
On Friday 10 April 2015 08:51 PM, ville.syrj...@linux.intel.com
From: Deepak S deepa...@linux.intel.com
When GPU is idle on VLV, Request freq to punit should be good enough to
get the voltage back to VNN. Also, make sure gfx clock force applies
before requesting the freq fot vlv.
v2: Do forcewake before setting idle frequency (ville)
Update function
From: Deepak S deepa...@linux.intel.com
It is observed on BSW that requesting a new frequency from Punit
does nothing when the GPU is in rc6, and if we let GPU enter rc6
with a high frequency, Vnn remains slightly higher than at minimum
frequency. Extending vlv_set_rps_idle() workaround on CHV
From: Deepak S deepa...@linux.intel.com
After feedback from the hardware team, now we set the GPU min/idel freq to RPe.
Punit is expecting us to operate GPU between Rpe Rp0. If we drop the
frequency to RPn, punit is failing to change the vgg input voltage to
minimum :(
Since Punit validates
From: Deepak S deepa...@linux.intel.com
After feedback from the hardware team, now we set the GPU min/idel freq to RPe.
Punit is expecting us to operate GPU between Rpe Rp0. If we drop the
frequency to RPn, punit is failing to change the input voltage to
minimum :(
Since Punit validates the rps
From: Deepak S deepa...@linux.intel.com
It is obsered on BSW that requesting a new frequency from Punit
does nothing when the GPU is in rc6, and if we let it enter rc6 with a
high frequency Vnn also remains high. Extending vlv_set_rps_idle()
workaround on CHV/BSW.
suggested-by: Ville Syrjälä
On Friday 08 May 2015 06:52 PM, Ville Syrjälä wrote:
On Fri, May 08, 2015 at 06:31:23PM +0530, Deepak S wrote:
On Friday 10 April 2015 08:51 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Not sure which LDO programming sequence delay should
From: Deepak S deepa...@linux.intel.com
When GPU is idle on VLV, Request freq to punit should be good enough to
get the voltage back to VNN. Also, make sure gfx clock force applies
before requesting the freq fot vlv.
v2: Do forcewake before setting idle frequency (ville)
Update function
On Friday 10 April 2015 08:51 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Powergate the PHY lanes when they're not needed. For HDMI all four lanes
are needed always, but for DP we can enable only the needed lanes. And
when the port is not used
On Wednesday 06 May 2015 02:32 PM, Daniel Vetter wrote:
On Tue, May 05, 2015 at 01:12:41PM +0530, Deepak S wrote:
On Monday 04 May 2015 08:58 PM, Ville Syrjälä wrote:
On Mon, May 04, 2015 at 10:12:23AM +0200, Daniel Vetter wrote:
On Mon, May 04, 2015 at 10:58:02AM +0530, Deepak S wrote
On Friday 10 April 2015 08:51 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Expecting CHV power wells to be just an extended versions of the VLV
power wells, a bunch of commented out power wells were added in
anticipation when Punit folks would
On Friday 08 May 2015 06:49 PM, Ville Syrjälä wrote:
On Fri, May 08, 2015 at 06:24:42PM +0530, Deepak S wrote:
On Friday 10 April 2015 08:51 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Sometimes (exactly when is a bit unclear
On Friday 10 April 2015 08:51 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Currently vlv_wait_port_ready() waits for all four lanes on the
appropriate channel. This no longer works on CHV when the unused
lanes may be power gated. So pass in a mask
On Friday 10 April 2015 08:51 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Sometimes (exactly when is a bit unclear) DISPLAY_PHY_CONTROL appears to
get corrupted. The values I've managed to read from it seem to have some
pattern but vary quite a
On Friday 10 April 2015 08:51 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
With recent hardware/firmware there don't appear to be any glitches
on the other PHY when we toggle the cmnreset for the other PHY. So
detangle the cmnlane power wells from
On Friday 10 April 2015 08:51 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Not sure which LDO programming sequence delay should be used for the CHV
PHY, but the spec says that 600ns is Used by default for initial
bringup, and the BIOS seems to use
) |
+ DPIO_TX2_STAGGER_MULT(5));
/* Clear calc init */
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
Patch does what spec says :)
Reviewed-by: Deepak S deepa...@linux.intel.com
___
Intel-gfx mailing list
On Friday 08 May 2015 10:04 PM, Ville Syrjälä wrote:
On Fri, May 08, 2015 at 08:43:10PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
When GPU is idle on VLV, Request freq to punit should be good enough to
get the voltage back to VNN. Also, make sure gfx
On Friday 08 May 2015 10:09 PM, Ville Syrjälä wrote:
On Fri, May 08, 2015 at 08:43:12PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
After feedback from the hardware team, now we set the GPU min/idel freq to RPe.
Punit is expecting us to operate GPU between
On Friday 08 May 2015 09:35 PM, Ville Syrjälä wrote:
On Fri, May 08, 2015 at 08:19:12PM +0530, Deepak S wrote:
On Friday 10 April 2015 08:51 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Powergate the PHY lanes when they're not needed. For HDMI
On Monday 04 May 2015 08:58 PM, Ville Syrjälä wrote:
On Mon, May 04, 2015 at 10:12:23AM +0200, Daniel Vetter wrote:
On Mon, May 04, 2015 at 10:58:02AM +0530, Deepak S wrote:
On Wednesday 29 April 2015 02:59 PM, Ville Syrjälä wrote:
On Wed, Apr 29, 2015 at 08:36:24AM +0530, deepa
On Wednesday 29 April 2015 02:59 PM, Ville Syrjälä wrote:
On Wed, Apr 29, 2015 at 08:36:24AM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
Based on the spec, Setting up static BIAS for GPU to improve the
rps performace.
v2: rename reg defn to match spec
On Thursday 30 April 2015 07:35 PM, Ville Syrjälä wrote:
On Thu, Apr 30, 2015 at 02:19:07PM +0300, Ville Syrjälä wrote:
On Thu, Apr 30, 2015 at 03:42:42PM +0530, Deepak S wrote:
As you suggested it would be better to extend the VLV WA to
CHV also to make sure we drop the voltage when idle
On Thursday 30 April 2015 01:23 AM, Ville Syrjälä wrote:
On Wed, Apr 29, 2015 at 06:31:56PM +0300, Ville Syrjälä wrote:
On Wed, Apr 29, 2015 at 08:23:21AM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
After feedback from the hardware team, now we set the GPU
On Wednesday 29 April 2015 03:56 PM, Ville Syrjälä wrote:
On Wed, Apr 29, 2015 at 08:20:20AM +0530, Deepak S wrote:
On Wednesday 29 April 2015 12:02 AM, Ville Syrjälä wrote:
On Tue, Apr 28, 2015 at 11:16:29AM -0700, Jesse Barnes wrote:
On 03/04/2015 08:08 PM, deepa...@linux.intel.com wrote
On Monday 13 April 2015 05:40 PM, Ville Syrjälä wrote:
On Mon, Apr 13, 2015 at 02:55:12PM +0300, Jani Nikula wrote:
On Thu, 05 Mar 2015, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
When GPU is idle on VLV, Request freq to punit should be good enough to
get
On Tuesday 28 April 2015 11:46 PM, Jesse Barnes wrote:
Yeah I think this is fine (may need a rebase though, you can keep my r-b
if you do that in case Jani doesn't want to deal with the merge conflicts).
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
Sure Jesse, I will rebase the
From: Deepak S deepa...@linux.intel.com
Based on the spec, Setting up static BIAS for GPU to improve the
rps performace.
v2: rename reg defn to match spec. (Ville)
v3: Updated bias setting for chv (Deepak)
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h
On Wednesday 29 April 2015 12:02 AM, Ville Syrjälä wrote:
On Tue, Apr 28, 2015 at 11:16:29AM -0700, Jesse Barnes wrote:
On 03/04/2015 08:08 PM, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
When GPU is idle on VLV, Request freq to punit should be good enough to
get
From: Deepak S deepa...@linux.intel.com
After feedback from the hardware team, now we set the GPU min/idel freq to RPe.
Punit is expecting us to operate GPU between Rpe Rp0. If we drop the
frequency to RPn, punit is failing to change the input voltage to
minimum :(
Since Punit validates the rps
From: Deepak S deepa...@linux.intel.com
Based on the spec, Setting up static BIAS for GPU to improve the
rps performace.
v2: rename reg defn to match spec. (Ville)
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 5 +
drivers/gpu/drm/i915/intel_pm.c
Yes agreed, we need to make changes in other paths :)
On Tuesday 28 April 2015 02:14 PM, Chris Wilson wrote:
On Tue, Apr 28, 2015 at 08:29:13AM +, S, Deepak wrote:
Thanks Chirs for review, We moved Init_hw to initialize WA's before any BB
submission.
Init_hw calls init_clock_gating
From: Deepak S deepa...@linux.intel.com
This WA is avoid problem between shadow vs wake FIFO unload
problem during CPD/RC6 transactions on CHV.
v2: Define individual bits GTFIFOCTL (Ville)
v3: move WA to uncore_early_sanitize (ville)
Signed-off-by: Deepak S deepa...@linux.intel.com
On Wednesday 15 April 2015 04:48 PM, Ville Syrjälä wrote:
On Wed, Apr 15, 2015 at 02:16:18PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
This WA is avoid problem between shadow vs wake FIFO unload
problem during CPD/RC6 transactions on CHV.
v2: Define
From: Deepak S deepa...@linux.intel.com
This WA is avoid problem between shadow vs wake FIFO unload
problem during CPD/RC6 transactions on CHV.
v2: Define individual bits GTFIFOCTL (Ville)
v3: move WA to uncore_early_sanitize (ville)
Signed-off-by: Deepak S deepa...@linux.intel.com
Reviewed
On Thursday 16 April 2015 12:09 AM, Ville Syrjälä wrote:
On Wed, Apr 15, 2015 at 07:41:39PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
This WA is avoid problem between shadow vs wake FIFO unload
problem during CPD/RC6 transactions on CHV.
v2: Define
On Monday 13 April 2015 05:36 PM, Jani Nikula wrote:
On Thu, 19 Mar 2015, Daniel Vetter dan...@ffwll.ch wrote:
On Thu, Mar 19, 2015 at 03:38:19PM +0200, David Weinehall wrote:
On Thu, Mar 19, 2015 at 06:17:00PM +0530, Deepak S wrote:
On Thursday 19 March 2015 05:14 PM, David Weinehall
On Tuesday 14 April 2015 04:29 PM, Ville Syrjälä wrote:
On Tue, Apr 14, 2015 at 03:58:54PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
This WA disable usage of shadow register during CPD/RC6 transactions on
CHV
I suppose is a workaround for the shadow vs
From: Deepak S deepa...@linux.intel.com
This WA is avoid problem between shadow vs wake FIFO unload
problem during CPD/RC6 transactions on CHV.
v2: Define individual bits GTFIFOCTL (Ville)
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu
From: Deepak S deepa...@linux.intel.com
This WA disable usage of shadow register during CPD/RC6 transactions on
CHV
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 4
2 files changed, 5 insertions(+)
diff --git
On Tuesday 07 April 2015 02:02 PM, Chris Wilson wrote:
On Tue, Apr 07, 2015 at 10:20:15AM +0200, Daniel Vetter wrote:
On Thu, Apr 02, 2015 at 06:49:38PM +0530, Deepak S wrote:
On Monday 30 March 2015 09:13 PM, Daniel Vetter wrote:
On Mon, Mar 30, 2015 at 08:03:58PM +0530, deepa
not see any race condition happening between diff Gfx force clk in
driver. Lets just drop it :)
Reviewed-by: Deepak S deepa...@linux.intel.com
val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
val = ~VLV_GFX_CLK_FORCE_ON_BIT;
___
Intel-gfx
frequent a process is
allowed to boost.
we may have to look at media workload. Last time when we observed that for
a 1080p HD clip GPU freq was staying at Rp0 most of the time.
Hopefully aggressive downclocking should help
Acked-by: Deepak S deepa...@linux.intel.com
Signed-off-by: Chris Wilson ch
to compensate for the RPS boosts.
v2: Rebase
v3: Exclude Cherrytrail as Deepak was concerned that the increased
number of register writes would wake the common powerwell too often.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Cc: Deepak S deepa...@linux.intel.com
Cc: Ville Syrjälä ville.syrj
On Thursday 02 April 2015 02:52 AM, Jesse Barnes wrote:
Some BIOSes (e.g. the one on the Minnowboard) don't save/restore this
reg. If it's unlocked, we can just restore the previous value, and if
it's locked (in case the BIOS re-programmed it for us) the write will be
ignored and we'll still
On Monday 30 March 2015 09:13 PM, Daniel Vetter wrote:
On Mon, Mar 30, 2015 at 08:03:58PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
Cleanup idr table if any error happens after __create_hw_context() in
i915_gem_create_context()
Signed-off-by: Deepak S
From: Deepak S deepa...@linux.intel.com
Sometimes, i915 might call _wait_for when irq is disabled.
If the cpu is the main cpu to process jiffies, jiffies
wouldn't be increased as this cpu disables irq. Then,
time_after(jiffies, timeout__) becomes meaningless. If
gunit doesn't work now, kernel
From: Deepak S deepa...@linux.intel.com
Cleanup idr table if any error happens after __create_hw_context() in
i915_gem_create_context()
v2: add a new err_idr (Daniel)
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/i915_gem_context.c | 6 --
1 file changed, 4
On Monday 30 March 2015 03:37 PM, Ville Syrjälä wrote:
On Sat, Mar 28, 2015 at 03:23:34PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
On CHV, PUNIT team confirmed that 'VLV_GFX_CLK_STATUS_BIT' is not a
sticky bit and it will always be set. So ignore Check
From: Deepak S deepa...@linux.intel.com
Cleanup idr table if any error happens after __create_hw_context() in
i915_gem_create_context()
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/i915_gem_context.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu
From: Deepak S deepa...@linux.intel.com
Based on the spec, Setting up static BIAS for GPU to improve the
rps performace.
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 5 +
drivers/gpu/drm/i915/intel_pm.c | 12
2 files changed, 17
From: Deepak S deepa...@linux.intel.com
On CHV, since Punit validates the rps range [RPe, RP0]. This patch
removes unused cherryview_rps_min_freq function.
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 18 --
1 file changed, 18 deletions
From: Deepak S deepa...@linux.intel.com
Adding few of PM fixes and Improvements for CHV/VLV.
Addressed few comments.
Deepak S (5):
drm/i915/chv: Remove Wait for a previous gfx force-off
drm/i915: Re-adjusting rc6 promotional timer for chv
drm/i915/chv: Set min freq to efficient frequency
From: Deepak S deepa...@linux.intel.com
On CHV, PUNIT team confirmed that 'VLV_GFX_CLK_STATUS_BIT' is not a
sticky bit and it will always be set. So ignore Check for previous
Gfx force off during suspend and allow the force clk as part S0ix
Sequence
Signed-off-by: Deepak S deepa
From: Deepak S deepa...@linux.intel.com
After feedback from the hardware team, now we set the GPU min/idel freq to RPe.
Punit is expecting us to operate GPU between Rpe Rp0. If we drop the
frequency to RPn, punit is failing to change the input voltage to
minimum :(
v2: Change commit message
v3
From: Deepak S deepa...@linux.intel.com
After feedback from the hardware team we are changing the RC6
promotional timer to increase the power saving without
changing performance.
Signed-off-by: Deepak S deepa...@linux.intel.com
Reviewed-by: Paulo Zanoni paulo.r.zan...@intel.com
---
drivers/gpu
On Friday 27 March 2015 02:32 AM, Paulo Zanoni wrote:
2015-03-19 11:14 GMT-03:00 deepa...@linux.intel.com:
From: Deepak S deepa...@linux.intel.com
After feedback from the hardware team we are changing the RC6
promotional timer to increase the power saving without
changing performance.
I
On Friday 27 March 2015 03:13 AM, Chris Wilson wrote:
On Thu, Mar 26, 2015 at 06:32:15PM -0300, Paulo Zanoni wrote:
2015-03-19 11:14 GMT-03:00 deepa...@linux.intel.com:
From: Deepak S deepa...@linux.intel.com
After feedback from the hardware team, now we set the GPU min/idel freq to RPe
On Tuesday 24 March 2015 01:13 AM, Paulo Zanoni wrote:
2015-02-26 12:16 GMT-03:00 deepa...@linux.intel.com:
From: Deepak S deepa...@linux.intel.com
After feedback from the hardware team we are changing the RC6
promotional timer to increase the power saving without
changing performance.
I
From: Deepak S deepa...@linux.intel.com
Unfortunately WaGsvRC0ResidencyMethod causing system freeze on some
of the baytrail systems :(. Switching back to legacy mode rps.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88012
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers
ch...@chris-wilson.co.uk
Cc: Satyanantha, Rama Gopal M rama.gopal.m.satyanan...@intel.com
Cc: Deepak S deepa...@linux.intel.com
Cc: Damien Lespiau damien.lesp...@intel.com
Cc: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/i915_gem.c | 7 ++-
1 file changed, 6 insertions(+), 1
On Thursday 19 March 2015 05:14 PM, David Weinehall wrote:
On Thu, Mar 19, 2015 at 04:09:44PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
Unfortunately WaGsvRC0ResidencyMethod causing system freeze on some
of the baytrail systems :(. Switching back
On Thursday 19 March 2015 04:48 PM, Ville Syrjälä wrote:
On Thu, Mar 19, 2015 at 04:09:44PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
Unfortunately WaGsvRC0ResidencyMethod causing system freeze on some
of the baytrail systems :(. Switching back to legacy
On Thursday 19 March 2015 06:40 PM, Chris Wilson wrote:
On Thu, Mar 19, 2015 at 06:31:04PM +0530, Deepak S wrote:
should we skip put_fence in overlay_do_put_image ?
Ah interesting point you raise there. That is buggy code fullstop.
We should not be call put_fence if pin_to_display_plane pins
From: Deepak S deepa...@linux.intel.com
After feedback from the hardware team, now we set the GPU min/idel freq to RPe.
Punit is expecting us to operate GPU between Rpe Rp0. If we drop the
frequency to RPn, punit is failing to change the input voltage to
minimum :(
v2: Change commit message
From: Deepak S deepa...@linux.intel.com
After feedback from the hardware team we are changing the RC6
promotional timer to increase the power saving without
changing performance.
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 4 ++--
1 file changed, 2
From: Deepak S deepa...@linux.intel.com
Adding few of PM fixes and Improvements for CHV/VLV.
Addressed few comments.
Deepak S (4):
drm/i915/chv: Remove Wait for a previous gfx force-off
drm/i915: Re-adjusting rc6 promotional timer for chv
drm/i915/chv: Set min freq to efficient frequency
From: Deepak S deepa...@linux.intel.com
Based on the spec, Setting up static BIAS for GPU to improve the
rps performace.
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 5 +
drivers/gpu/drm/i915/intel_pm.c | 12
2 files changed, 17
From: Deepak S deepa...@linux.intel.com
On CHV, PUNIT team confirmed that 'VLV_GFX_CLK_STATUS_BIT' is not a
sticky bit and it will always be set. So ignore Check for previous
Gfx force off during suspend and allow the force clk as part S0ix
Sequence
Signed-off-by: Deepak S deepa
not mappable.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Cc: Satyanantha, Rama Gopal M rama.gopal.m.satyanan...@intel.com
Cc: Deepak S deepa...@linux.intel.com
Cc: Damien Lespiau damien.lesp...@intel.com
Cc: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/i915_gem.c
On Wednesday 18 March 2015 01:48 PM, Deepak S wrote:
On Friday 06 March 2015 08:36 PM, Chris Wilson wrote:
If we hit a vblank and see that have a pageflip queue but not yet
processed, ensure that the GPU is running at maximum in order to clear
the backlog. Pageflips are only queued
On Wednesday 18 March 2015 03:18 PM, Daniel Vetter wrote:
On Wed, Mar 18, 2015 at 01:42:58PM +0530, Deepak S wrote:
I guess your empty reply wasn't intentional?
-Daniel
Sorry, that was not intentional :)
On Friday 06 March 2015 08:36 PM, Chris Wilson wrote:
Reuse the same reclocking
to compensate for the RPS boosts.
v2: Rebase
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Cc: Deepak S deepa...@linux.intel.com
Cc: Ville Syrjälä ville.syrj...@linux.intel.com
Cc: Rodrigo Vivi rodrigo.v...@intel.com
Cc: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915
On Wednesday 18 March 2015 02:50 PM, Chris Wilson wrote:
On Wed, Mar 18, 2015 at 12:26:49PM +0530, Deepak S wrote:
On Friday 06 March 2015 08:36 PM, Chris Wilson wrote:
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_irq.c | 27
On Friday 06 March 2015 08:36 PM, Chris Wilson wrote:
Use both up/down manual ei calcuations for symmetry and greater
flexibility for reclocking, instead of faking the down interrupt based
on a fixed integer number of up interrupts.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
On Friday 06 March 2015 08:36 PM, Chris Wilson wrote:
With boosting for missed pageflips, we have a much stronger indication
of when we need to (temporarily) boost GPU frequency to ensure smooth
delivery of frames. So now only allow each client to perform one RPS boost
in each period of GPU
to compensate for the RPS boosts.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Cc: Deepak S deepa...@linux.intel.com
Cc: Ville Syrjälä ville.syrj...@linux.intel.com
Cc: Rodrigo Vivi rodrigo.v...@intel.com
Cc: Daniel Vetter daniel.vet...@ffwll.ch
Conflicts:
drivers/gpu/drm/i915/intel_pm.c
idle_freq for vlv and add a bunch of WARNs
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Cc: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 6 +
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 44
On Friday 06 March 2015 08:36 PM, Chris Wilson wrote:
Rewrite commit 31685c258e0b0ad6aa486c5ec001382cf8a64212
Author: Deepak S deepa...@linux.intel.com
Date: Thu Jul 3 17:33:01 2014 -0400
drm/i915/vlv: WA for Turbo and RC6 to work together.
Other than code clarity, the major
On Wednesday 18 March 2015 03:18 PM, Chris Wilson wrote:
If we hit a vblank and see that have a pageflip queue but not yet
processed, ensure that the GPU is running at maximum in order to clear
the backlog. Pageflips are only queued for the following vblank, if we
miss it, there will be a
On Wednesday 18 March 2015 04:53 PM, Chris Wilson wrote:
On Wed, Mar 18, 2015 at 04:45:08PM +0530, Deepak S wrote:
+ if (val != dev_priv-rps.cur_freq) {
vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
+ gen6_set_rps_thresholds(dev_priv, val);
I
Reviewed-by: Deepak S deepa...@linux.intel.com
} else if (pm_iir GEN6_PM_RP_DOWN_THRESHOLD) {
if (adj 0)
adj *= 2;
- else {
- /* CHV needs even encode values */
- adj = IS_CHERRYVIEW(dev_priv-dev
On Friday 06 March 2015 08:36 PM, Chris Wilson wrote:
When we idle, we set the GPU frequency to the hardware minimum (not user
minimum). We introduce a new variable to distinguish between the
different roles, and to allow easy tuning of the idle frequency without
impacting over aspects of RPS.
On Friday 06 March 2015 08:36 PM, Chris Wilson wrote:
When we idle, we set the GPU frequency to the hardware minimum (not user
minimum). We introduce a new variable to distinguish between the
different roles, and to allow easy tuning of the idle frequency without
impacting over aspects of RPS.
On Friday 06 March 2015 10:10 PM, Daniel Vetter wrote:
On Thu, Mar 05, 2015 at 09:27:59PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
In normal cases, RC6 promotion timer is 1700us/500us. This will
result in more time spent in C1 state. For more residency
On Wednesday 11 March 2015 07:36 PM, Chris Wilson wrote:
On Wed, Mar 11, 2015 at 07:23:48PM +0530, Deepak S wrote:
On Thursday 26 February 2015 09:42 PM, Chris Wilson wrote:
On Thu, Feb 26, 2015 at 08:46:56PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
On Thursday 26 February 2015 09:12 PM, Deepak S wrote:
On Thursday 26 February 2015 09:13 PM, Ville Syrjälä wrote:
On Thu, Feb 26, 2015 at 08:46:54PM +0530, deepa...@linux.intel.com
wrote:
From: Deepak S deepa...@linux.intel.com
On CHV, PUNIT team confirmed that 'VLV_GFX_CLK_STATUS_BIT
On Wednesday 11 March 2015 07:26 PM, Chris Wilson wrote:
On Wed, Mar 11, 2015 at 07:07:12PM +0530, Deepak S wrote:
On Friday 06 March 2015 10:10 PM, Daniel Vetter wrote:
On Thu, Mar 05, 2015 at 09:27:59PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
On Thursday 26 February 2015 09:42 PM, Chris Wilson wrote:
On Thu, Feb 26, 2015 at 08:46:56PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
After feedback from the hardware team, now we set the GPU min freq to RPe.
If we drop the freq to RPn, we found
From: Deepak S deepa...@linux.intel.com
In normal cases, RC6 promotion timer is 1700us/500us. This will
result in more time spent in C1 state. For more residency in
C6 in case of media workloads, this is changed to 250us.
Not doing this for 3D workloads as too many C6-C0
transition delays can
From: Deepak S deepa...@linux.intel.com
When GPU is idle on VLV, Request freq to punit should be good enough to
get the voltage back to VNN. Also, make sure gfx clock force applies
before requesting the freq fot vlv.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75244
suggested
From: Deepak S deepa...@linux.intel.com
We update the GT PM interrupts mask at the end of set rps. We observed even
though we are requesting a RPn or RP0, there is a chance to get a DOWN or UP
interrupts before interrupts mask. These extra interrupts are simply wasting
cpu cycles. In this patch
From: Deepak S deepa...@linux.intel.com
In normal cases, RC6 promotion timer is 1700us/500us. This will
result in more time spent in C1 state. For more residency in C6
in case of media workloads, this is changed to 250us.
Not doing this for 3D workloads as too many C6-C0 transition
delays can
From: Deepak S deepa...@linux.intel.com
On CHV, PUNIT team confirmed that 'VLV_GFX_CLK_STATUS_BIT' is not a
sticky bit and it will always be set. So ignore Check for previous
Gfx force off during suspend and allow the force clk as part S0ix
Sequence
Signed-off-by: Deepak S deepa
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