491355230d11 Mon Sep 17 00:00:00 2001
From: Rodrigo Vivi
Date: Wed, 11 Apr 2012 15:36:31 -0300
Subject: [PATCH] drm/edid: Adding common CVT inferred modes when monitor
allows range limited ones trough EDID.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/drm_edid.c | 37 +-
491355230d11 Mon Sep 17 00:00:00 2001
From: Rodrigo Vivi
Date: Wed, 11 Apr 2012 15:36:31 -0300
Subject: [PATCH] drm/edid: Adding common CVT inferred modes when monitor
allows range limited ones trough EDID.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/drm_edid.c | 37 +-
491355230d11 Mon Sep 17 00:00:00 2001
From: Rodrigo Vivi
Date: Wed, 11 Apr 2012 15:36:31 -0300
Subject: [PATCH] drm/edid: Adding common CVT inferred modes when monitor
allows range limited ones trough EDID.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/drm_edid.c | 37 +-
Hi Ajax and Takashi,
Thanks for your comments.
> The intent here is great, but I don't like the way this is phrased, or
> the implementation.
To be honest I don't like this implementation as well. I just tried to
follow the way it wasa already there.
> CVT monitors _must_ accept GTF as well, ED
ser issue at all, it's driver
> policy.
>
> - ajax
>
> _______
> dri-devel mailing list
> dri-de...@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
Thanks for the patches ajax
Feel free to use
Reviewed-by: Rodrigo Vivi
On Tue, Apr 17, 2012 at 12:50 PM, Takashi Iwai wrote:
> At Tue, 17 Apr 2012 17:33:17 +0200,
> Takashi Iwai wrote:
>>
>> At Fri, 13 Apr 2012 16:33:28 -0400,
>> Adam Jackson wrote:
>> >
>
n't use it) and
>> should be left in and perhaps be renamed to just 480p since there is now
>> no need to differentiate frequencies.
>>
>> Something like this?
>
> Hm, I have no idea whether we should just revert the entire commit.
> Rodrigo, your commit
>
&
These 2 modes were removed by mistake during a clean up.
So, now it is time to add them back. For further info about
supported mode and standard timing table please check:
VOL_3_display_registers_updated.pdf at intellinuxgraphics.org.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915
These 2 modes were removed by mistake during a clean up.
So, now it is time to add them back. For further info about
supported mode and standard timing table please check:
VOL_3_display_registers_updated.pdf at intellinuxgraphics.org.
Reported-by: Robert Lowery
Signed-off-by: Rodrigo Vivi
>
> Thanks, Clemens
> ___
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
___
Intel-gfx mailing lis
__
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Reviewed-by: Rodrigo Vivi
2012/8/6 Paulo Zanoni :
> From: Paulo Zanoni
>
> Also properly indent the HB IDs.
>
> Signed-off-by: Paulo Zanoni
> ---
> drivers/char/agp/intel-agp.h| 39 +
> drivers/char/a
Reviewed-by: Rodrigo Vivi
On Mon, Aug 6, 2012 at 6:46 PM, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> Signed-off-by: Paulo Zanoni
> ---
> intel/intel_chipset.h | 68
> ---
> 1 file changed, 65 insertions(+), 3 deletion
Reviewed-by: Rodrigo Vivi
On Mon, Aug 6, 2012 at 6:48 PM, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> Signed-off-by: Paulo Zanoni
> ---
> src/intel_driver.h | 37 +++
> src/intel_module.c | 73
>
Reviewed-by: Rodrigo Vivi
On Mon, Aug 6, 2012 at 6:50 PM, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> Signed-off-by: Paulo Zanoni
> ---
> include/pci_ids/i965_pci_ids.h | 33 ++-
> src/mesa/drivers/dri/intel/in
Reviewed-by: Rodrigo Vivi
On Mon, Aug 6, 2012 at 6:49 PM, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> Signed-off-by: Paulo Zanoni
> ---
> lib/intel_chipset.h | 68
> ++---
> 1 file changed, 65 insertions(+), 3 deletion
ng list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
___
Intel-gfx mailing list
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Feel free to use:
Reviewed-by: Rodrigo Vivi
On Mon, Sep 17, 2012 at 9:10 PM, Ben Widawsky wrote:
> I do not currently have a VLV to test this on, but hopefully it only
> removes information from debugfs, sysfs, and prevents enabling an
> unsupported mode.
>
> CC: Jesse Barnes
der
> *encoder,
> I915_WRITE(data_reg + i, *data);
> data++;
> }
> + for (; i < 32; i += 4)
> + I915_WRITE(data_reg + i, 0);
> mmiowb();
>
> val |= hsw_infoframe_enable(frame);
> --
> 1.7
This was easy for me, feel free to use:
Reviewed-by: Rodrigo Vivi
On Mon, Sep 24, 2012 at 10:32 AM, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> This should never happen, but the silent "return" makes me wonder
> every time I try to debug InfoFrame bugs, so promote t
Feel free to use:
Reviewed-by: Rodrigo Vivi
On Fri, Sep 21, 2012 at 9:01 PM, Ben Widawsky wrote:
> From: Ben Widawsky
>
> Signed-off-by: Ben Widawsky
> ---
> drivers/gpu/drm/i915/i915_dma.c | 4 ++--
> drivers/gpu/drm/i915/i915_drv.h | 8
> drivers/gpu/drm
Feel free to use:
Reviewed-by: Rodrigo Vivi
On Thu, Sep 20, 2012 at 6:36 PM, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> As noticed by Daniel Vetter, intel_pipe_choose_bpp_dither should
> already check for invalid bpp values and set a valid value, so remove
> the
Feel free to use:
Reviewed-by: Rodrigo Vivi
On Thu, Sep 20, 2012 at 6:36 PM, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> The set_m_n code was spread all over the mode_set function.
>
> Version 2:
> Don't set the DP M/N registers on ironlake_set_m_n. Daniel Vetter
Feel free to use:
Reviewed-by: Rodrigo Vivi
On Thu, Sep 20, 2012 at 6:36 PM, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> Too many lines just to compute the value of a single variable, so
> move this to its own function.
>
> Signed-off-by: Paulo Zanoni
> ---
&g
Feel free to use
Reviewed-by: Rodrigo Vivi
On Thu, Sep 20, 2012 at 6:36 PM, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> The last patches moved a lot of code from ironlake_crtc_mode_set to
> sub-functions, so these variables became useless. You could get
> warnings by enabling -
((adjusted_mode->crtc_vtotal - 1) << 16));
> - I915_WRITE(VBLANK(pipe),
> - (adjusted_mode->crtc_vblank_start - 1) |
> - ((adjusted_mode->crtc_vblank_end - 1) << 16));
> - I915_WRITE(VSYNC(pipe),
> - (adjusted_mode->crtc_vsync_start - 1) |
> - ((adjusted_mode->crtc_vsync_end - 1) << 16));
> -
> - /* pipesrc controls the size that is scaled from, which should
> -* always be the user's requested size.
> -*/
> - I915_WRITE(PIPESRC(pipe),
> - ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
> + intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
>
> ironlake_set_m_n(crtc, mode, adjusted_mode);
>
> --
> 1.7.10.4
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
___
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Reviewed-by: Rodrigo Vivi
On Tue, Sep 25, 2012 at 10:53 AM, Chris Wilson wrote:
> As using the contexts (with mesa) causes an instant hard hang on my
> i5-2500 SandyBridge GT1 desktop, they are not ready for universal
> enabling.
>
> Signed-off-by: Chris Wilson
> ---
>
Reviewed-by: Rodrigo Vivi
On Tue, Sep 25, 2012 at 1:23 PM, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> ... even if the actual infoframe is smaller than the maximum possible
> size.
>
> If we don't write all the 32 DIP data bytes the InfoFrame ECC may not
> be co
Reviewed-by: Rodrigo Vivi
On Wed, Sep 26, 2012 at 2:17 PM, Damien Lespiau
wrote:
> From: Damien Lespiau
>
> Those infoframes are programmed when using stereo 3D modes.
>
> Signed-off-by: Damien Lespiau
> ---
> tools/inte
= "3hiaf:s:d:p:mrt";
>
> static void __attribute__((noreturn)) usage(char *name)
> {
> @@ -607,6 +819,7 @@ static void __attribute__((noreturn)) usage(char *name)
> fprintf(stderr, "\t-d\t\tbit depth of scanout buffer\n");
> fprintf(stderr, "\t-p\t,, test overlay
&g
Reviewed-by: Rodrigo Vivi
Tested-by: Rodrigo Vivi
On Thu, Sep 27, 2012 at 3:41 PM, Damien Lespiau
wrote:
> From: Damien Lespiau
>
> The "expose 3D modes" property can be attached to connectors to allow
> user space to indicate it can deal with 3D modes and that the drm
Reviewed-by: Rodrigo Vivi
Tested-by: Rodrigo Vivi
On Thu, Sep 27, 2012 at 3:42 PM, Damien Lespiau
wrote:
> From: Damien Lespiau
>
> When dumping the details of a mode, let's add the 3D formats the mode
> supports.
>
> Signed-off-by: Damien Lespiau
>
Reviewed-by: Rodrigo Vivi
Tested-by: Rodrigo Vivi
On Thu, Sep 27, 2012 at 3:41 PM, Damien Lespiau
wrote:
> From: Damien Lespiau
>
> For now, let's just look at the 3D_present flag of the CEA HDMI vendor
> block to detect if the sink supports a small list of then manda
pu/drm/i915/intel_modes.c
> @@ -124,3 +124,15 @@ intel_attach_broadcast_rgb_property(struct drm_connector
> *connector)
>
> drm_connector_attach_property(connector, prop, 0);
> }
> +
> +void
> +intel_attach_expose_3d_modes_property(struct drm_connector *connector)
&g
Reviewed-by: Rodrigo Vivi
On Fri, Sep 28, 2012 at 8:25 AM, Chris Wilson wrote:
> When we process a pageflip completion, we append an event to the vblank
> queue. That queue is processed by drm_handle_vblank() and so by calling
> drm_handle_vblank() prior to processing the pageflips, we
Reviewed-by: Rodrigo Vivi
On Mon, Oct 1, 2012 at 6:10 PM, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> Version 2: call intel_set_pipe_timings from both i9xx_crtc_mode_set
> and ironlake_crtc_mode_set, instead of just ironlake, as requested by
> Daniel Vetter.
>
> The prob
s,
Rodrigo.
Rodrigo Vivi (3):
drm/i915: Fix TV Out refresh rate.
drm/i915: Removing TV Out modes.
drm/i915: Adding 1080p modes to our TV Out mode list.
drivers/gpu/drm/i915/intel_tv.c | 176 ++-
1 files changed, 63 insertions(+), 113 deletions(-)
-
TV Out refresh rate was half of the specification for almost all modes.
Due to this reason pixel clock was so low for some modes causing flickering
screen.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_tv.c | 16
1 files changed, 8 insertions(+), 8 deletions
These modes are no longer needed or are not according to TV timing standards.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_tv.c | 122 ---
1 files changed, 0 insertions(+), 122 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_tv.c b
According to TV Out timing standards, supported 1080p modes were missing.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_tv.c | 72 +++
1 files changed, 72 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu
For other patches in this serie the table can be found at our PRM
http://intellinuxgraphics.org/VOL_3_display_registers_updated.pdf
Section 5.2 TV Out Programming / 5.2.1 Television Standards
On Wed, Dec 14, 2011 at 9:19 PM, Chris Wilson wrote:
> On Wed, 14 Dec 2011 21:10:08 -0200, Rodrigo V
ument will be public and the comment
will be there forever.
Do you have any suggestion?
Thanks
Rodrigo
On Thu, Dec 15, 2011 at 1:00 PM, Rodrigo Vivi wrote:
> For other patches in this serie the table can be found at our PRM
> http://intellinuxgraphics.org/VOL_3_display_registers_updated.
These modes are no longer needed or are not according to TV timing standards.
Intel PRM Vol 3 - Display Registers Updated - Section 5 TV-Out Programming /
5.2.1 Television Standards / 5.2.1.1 Timing tables
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_tv.c | 122
Adding 1080p supported modes according to new PRM version which is
internal for now.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_tv.c | 72 +++
1 files changed, 72 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_tv.c b
I think we should go ahead and integrate the first and second patches
and skip the 1080 (third) for now.
We are internally discussing when and if that document will be released.
On Fri, Jan 6, 2012 at 8:02 PM, Keith Packard wrote:
> On Wed, 14 Dec 2011 21:10:06 -0200, Rodrigo Vivi
>
gt;
> presumably "whatever" is something like "1920x1080x60.0" in your case ...
> ___
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
GPG:
iately.
>
> Please attach the TV, then run "xrandr --verbose" and send us the output.
> Please also send the output of intel_reg_dumper:
> http://intellinuxgraphics.org/intel_reg_dumper.html
>
> --
> Paulo Zanoni
>
> ___
> Intel-gf
l.com] Maybe the best tree to
>>test is this:
>>http://cgit.freedesktop.org/~danvet/drm-intel/log/?h=drm-intel-next-que
>>ued
>
> I will compile it now. Before I used the drm-intel-next branch. I downloaded
> the latest tar.gz file and didn't use git to checkout the
Reviewed-by: Rodrigo Vivi
On Thu, Mar 15, 2012 at 11:42 AM, Takashi Iwai wrote:
> At Thu, 15 Mar 2012 14:30:35 +0100,
> Takashi Iwai wrote:
>>
>> At Thu, 15 Mar 2012 13:25:08 +,
>> Chris Wilson wrote:
>> >
>> > On Thu, 15 Mar 2012 14:15:54 +0100
Altough Keith's idea is very good I tested here with many systems that
are already working nowadays and it didn't break anything. Including
atom at 945gme, ironlake, sandybridge and ivybridge... including
single and dual channel modes...
Tested-by: Rodrigo Vivi
On Tue, Mar 20, 2012 a
Like in this patch, the defines indentation in some patches in this
series sounds strange, wrong, or at least different from the one
already in use.
So, since I don't know if we should care about indentation now, for
those patches I'll just mark like this:
* indentation
Reviewed-by: Ro
*indentation
and it is missing
#define PIPE_DDI_MODE_SELECT_DP_MST (3<<24)
Otherwise:
Reviewed-by: Rodrigo Vivi
On Wed, Mar 21, 2012 at 10:09 PM, Eugeni Dodonov
wrote:
> There is one set of such registers for each pipe (A/B/C/EDP).
>
> Signed-off-by: Eugeni Dodonov
> ---
* indentation
Reviewed-by: Rodrigo Vivi
On Wed, Mar 21, 2012 at 10:09 PM, Eugeni Dodonov
wrote:
> There is one instance of those registers for each DDI port.
>
> Signed-off-by: Eugeni Dodonov
> ---
> drivers/gpu/drm/i915/i915_reg.h | 23 +++
>
* indentation
Reviewed-by: Rodrigo Vivi
On Wed, Mar 21, 2012 at 10:09 PM, Eugeni Dodonov
wrote:
> Pixel clock gating control for Lynx point.
>
> Signed-off-by: Eugeni Dodonov
> ---
> drivers/gpu/drm/i915/i915_reg.h | 6 ++
> 1 file changed, 6 insertions(+)
>
>
Reviewed-by: Rodrigo Vivi
On Wed, Mar 21, 2012 at 10:09 PM, Eugeni Dodonov
wrote:
> Multiple clocks can drive different outputs.
>
> Signed-off-by: Eugeni Dodonov
> ---
> drivers/gpu/drm/i915/i915_reg.h | 23 +++
> 1 file changed, 23 insertions(+
* indentation
Reviewed-by: Rodrigo Vivi
On Wed, Mar 21, 2012 at 10:09 PM, Eugeni Dodonov
wrote:
> Those are responsible for the Sideband Interface programming.
>
> Signed-off-by: Eugeni Dodonov
> ---
> drivers/gpu/drm/i915/i915_reg.h | 10 ++
> 1 file chan
* indentation
Reviewed-by: Rodrigo Vivi
On Wed, Mar 21, 2012 at 10:09 PM, Eugeni Dodonov
wrote:
> Different registers are identified by their target id and offset. To
> simplify their programming, they are called as .
> For example, SSCCTL register accessed through SBI at target
* indentation
Reviewed-by: Rodrigo Vivi
On Wed, Mar 21, 2012 at 10:09 PM, Eugeni Dodonov
wrote:
> Watermark line time registers for display low power watermark.
>
> Signed-off-by: Eugeni Dodonov
> ---
> drivers/gpu/drm/i915/i915_reg.h | 10 ++
> 1 file chan
* indentation
Reviewed-by: Rodrigo Vivi
On Wed, Mar 21, 2012 at 10:09 PM, Eugeni Dodonov
wrote:
> This PLL control can drive DDI ports at desired frequencies for
> DisplayPort and FDI connections.
>
> Signed-off-by: Eugeni Dodonov
> ---
> drivers/gpu/drm/i915/i915_reg.h |
LCPLL_PLL_ENABLE should be (0<<31)\
Otherwise
Reviewed-by: Rodrigo Vivi
On Wed, Mar 21, 2012 at 10:09 PM, Eugeni Dodonov
wrote:
> Those are used to control the display core clock.
>
> Signed-off-by: Eugeni Dodonov
> ---
> drivers/gpu/drm/i915/i915_reg.h | 7 +++
* indentation
Reviewed-by: Rodrigo Vivi
On Wed, Mar 21, 2012 at 10:09 PM, Eugeni Dodonov
wrote:
> Add Global Time Clock registers
>
> Signed-off-by: Eugeni Dodonov
> ---
> drivers/gpu/drm/i915/i915_reg.h | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --gi
Reviewed-by: Rodrigo Vivi
On Wed, Mar 21, 2012 at 10:09 PM, Eugeni Dodonov
wrote:
> Those registers are used to train DDI buffer translations for each link
> type.
>
> Signed-off-by: Eugeni Dodonov
> ---
> drivers/gpu/drm/i915/i915_reg.h | 7 +++
> 1 file
Ops, actually I'm in doubt about this one, for me:
SBI_RESPONSE should be (0x0<<1)
SBI_READY should be(0x0<<0)
let's double check this togheter, otherwise:
Reviewed-by: Rodrigo Vivi
On Mon, Mar 26, 2012 at 2:40 PM, Rodrigo Vivi wrote:
> * indentation
&g
Reviewed-by: Rodrigo Vivi
On Wed, Mar 21, 2012 at 10:10 PM, Eugeni Dodonov
wrote:
> Those have different functionality on Haswell architecture, so let's
> trigger a warning message when we are going through a path we should not
> go into on Haswell.
>
> This patch is here fo
Reviewed-by: Rodrigo Vivi
On Wed, Mar 21, 2012 at 10:10 PM, Eugeni Dodonov
wrote:
> This patch attempts at following the modeset sequence closely, retrying
> with different voltages if the DP_TP_STATUS reports a failed training.
>
> For training, we add a table of recommended sett
Reviewed-by: Rodrigo Vivi
On Wed, Mar 21, 2012 at 10:10 PM, Eugeni Dodonov
wrote:
> This should be already configured when FDI auto-negotiation is done.
>
> Signed-off-by: Eugeni Dodonov
> ---
> drivers/gpu/drm/i915/intel_display.c | 3 ++-
> 1 file changed, 2 inserti
Reviewed-by: Rodrigo Vivi
On Wed, Mar 21, 2012 at 10:10 PM, Eugeni Dodonov
wrote:
> Signed-off-by: Eugeni Dodonov
> ---
> drivers/gpu/drm/i915/intel_display.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
&
Reviewed-by: Rodrigo Vivi
On Wed, Mar 21, 2012 at 10:10 PM, Eugeni Dodonov
wrote:
> They work differently, but the count is the same.
>
> Signed-off-by: Eugeni Dodonov
> ---
> drivers/gpu/drm/i915/i915_dma.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
&
Reviewed-by: Rodrigo Vivi
On Wed, Mar 21, 2012 at 10:10 PM, Eugeni Dodonov
wrote:
> Some double-buffered registers need to be written twice.
>
> Note that it is being sent as a separate patch because sometimes these
> registers do work when written only once. But double-writing o
Reviewed-by: Rodrigo Vivi
On Wed, Mar 21, 2012 at 10:10 PM, Eugeni Dodonov
wrote:
> Signed-off-by: Eugeni Dodonov
> ---
> drivers/gpu/drm/i915/intel_display.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
&
Reviewed-by: Rodrigo Vivi
On Wed, Mar 21, 2012 at 10:10 PM, Eugeni Dodonov
wrote:
> This needs proper enablement to avoid machine hangs, so let's just avoid
> it for now.
>
> Signed-off-by: Eugeni Dodonov
> ---
> drivers/gpu/drm/i915/intel_display.c | 4
> 1
that's true!
On Mon, Mar 26, 2012 at 2:46 PM, Daniel Vetter wrote:
> On Mon, Mar 26, 2012 at 02:42:30PM -0300, Rodrigo Vivi wrote:
>> LCPLL_PLL_ENABLE should be (0<<31)\
>
> I that case I think we should name it LCPLL_PLL_DISABLE (and use (1<<31)
> obvi
and here can be
SBI_BUSY 0x1<<0
and SBI_RESPONSE_UNSUCCESSFUL 0x1<<1
On Mon, Mar 26, 2012 at 2:48 PM, Rodrigo Vivi wrote:
> Ops, actually I'm in doubt about this one, for me:
>
> SBI_RESPONSE should be (0x0<<1)
> SBI_READY should be (0x0<<0)
>
&
Reviewed-by: Rodrigo Vivi
On Wed, Mar 21, 2012 at 10:09 PM, Eugeni Dodonov
wrote:
> Signed-off-by: Eugeni Dodonov
> ---
> drivers/gpu/drm/i915/intel_display.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
&
+ temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
>> + temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
>> + temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
>> + temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
>> + temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
>> + temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
>> +
>> + SBI_WRITE(dev_priv,
>> + SBI_SSCDIVINTPHASE6,
>> + temp);
>> +
>> + /* Program SSCAUXDIV */
>> + SBI_WRITE(dev_priv,
>> + SBI_SSCAUXDIV6,
>> + SBI_READ(dev_priv, SBI_SSCAUXDIV6) |
>> + SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv));
>> +
>> +
>> + /* Enable modulator and associated divider */
>> + SBI_WRITE(dev_priv, SBI_SSCCTL6,
>> + SBI_READ(dev_priv, SBI_SSCCTL6) &
>> + ~SBI_SSCCTL_DISABLE);
>> +
>> + /* Wait for initialization time */
>> + udelay(50);
>> +
>> + /* Gate pixel clock */
>> + I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
>> +}
>> +
>>
>> /* Link training for HSW parts */
>> static void hsw_fdi_link_train(struct drm_crtc *crtc)
>> @@ -3182,6 +3488,9 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
>> /* DDIE clock is recommented for FDI connections */
>> I915_WRITE(PIPE_CLK_SEL(pipe),
>> PIPE_CLK_SEL_DDIE);
>> +
>> + /* Program iCLKIP */
>> + lpt_program_iclkip(crtc);
>> }
>>
>> /* set transcoder timing, panel must allow it */
>> --
>> 1.7.9.2
>>
>> ___
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Daniel Vetter
> Mail: dan...@ffwll.ch
> Mobile: +41 (0)79 365 57 48
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
GPG: 0x905BE242 @ wwwkeys.pgp.net
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
ah ok, no problem than... I just imagine that this would be useful
because in other places you mentioned the DP MST mode...
On Mon, Mar 26, 2012 at 2:58 PM, Eugeni Dodonov wrote:
> On Mon, Mar 26, 2012 at 14:35, Rodrigo Vivi wrote:
>>
>> *indentation
>> and it
Reviewed-by: Rodrigo Vivi
On Wed, Mar 21, 2012 at 10:09 PM, Eugeni Dodonov
wrote:
> Signed-off-by: Eugeni Dodonov
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/
I was also waiting for the patch that really does some parse as well,
but I think this patch will be useful for one case that I'm currently
working on...
anyway:
Reviewed-by: Rodrigo Vivi
On Thu, Mar 22, 2012 at 2:00 PM, Jesse Barnes wrote:
> On Thu, 22 Mar 2012 09:11:37 -0700
> B
Reviewed-by: Rodrigo Vivi
On Sat, Mar 24, 2012 at 8:03 PM, Chris Wilson wrote:
> On Sat, 24 Mar 2012 23:51:30 +0100, Daniel Vetter
> wrote:
>> Somehow the BIOS manages to screw things up when copying the VBT
>> around, because the one we scrap from the VBIOS rom actually wo
r fix for it. Meanwhile:
Reviewed-by: Rodrigo Vivi
On Sun, Mar 25, 2012 at 5:56 PM, Daniel Vetter wrote:
> This reverts commmit d4b74bf07873da2e94219a7b67a334fc1c3ce649 which
> reverted the origin fix fb8b5a39b6310379d7b54c0c7113703a8eaf4a57.
>
> We have at least 3 different bug
Reviewed-by: Rodrigo Vivi
On Wed, Mar 21, 2012 at 10:09 PM, Eugeni Dodonov
wrote:
> Signed-off-by: Eugeni Dodonov
> ---
> drivers/gpu/drm/i915/i915_drv.c | 4
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> 2 files changed, 6 insertions(+)
>
> diff --git a
On Mon, Dec 03, 2018 at 04:29:17AM -0800, Peres, Martin wrote:
> On 30/11/2018 19:27, Vivi, Rodrigo wrote:
> > On Fri, Nov 30, 2018 at 03:04:40PM +0200, Martin Peres wrote:
> >>
> >>
> >> On 29/11/2018 19:36, Rodrigo Vivi wrote:
> >>> On Wed, Nov 28
_SU_MASK
> > - Adding EDP_PSR2_FRAME_BEFORE_SU_MAX
> > - Adding EDP_PSR2_IDLE_FRAME()
> > - Adding EDP_PSR2_IDLE_FRAME_MAX
> >
> > In the next patch the new macros will be used.
> >
> > Cc: Dhinakaran Pandiyan
> > Cc: Rodrigo Vivi
> > Signed-off-
On Thu, Dec 06, 2018 at 12:25:48PM +1000, Dave Airlie wrote:
> I merged the i915 tree into drm-next this morning, but got a major
> conflict on the drm-tip rebuild in intel_workarounds.c.
>
> I'm not sure if I did wrong thing, but there were a couple of places
> where the code seemed inconsistent
On Fri, Dec 07, 2018 at 10:28:39AM -0800, Anusha wrote:
> From: Anusha Srivatsa
>
> We have an update for HuC for BXT.
> Load the latest version.
>
> v2: Change the subject.
>
> Cc: Rodrigo Vivi
> Signed-off-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/
On Fri, Dec 07, 2018 at 12:36:59PM +0800, Zhenyu Wang wrote:
>
> Hi,
>
> As I was hoping to possibly merge more new stuff for next kernel e.g
> CFL support, etc, but seems those're still not stable enough so better
> wait for next cycle, so sorry for the late.
If I understood correctly Jani alr
On Tue, Dec 11, 2018 at 04:35:57PM +0200, Jani Nikula wrote:
> On Wed, 05 Dec 2018, Lucas De Marchi wrote:
> > Instead of using IS_GEN() for consecutive gen checks, let's pass the
> > range to IS_GEN_RANGE(). By code inspection these were the ranges deemed
> > necessary for spatch:
> >
> > @@
> >
On Thu, Dec 13, 2018 at 09:48:48PM +0200, Imre Deak wrote:
> It's useful to see at which point a TypeC port gets disconnected, so add
> add a debug print for it.
>
> Cc: Paulo Zanoni
> Cc: Ville Syrjälä
> Cc: José Roberto de Souza
> Cc: Rodrigo Vivi
> Signed-of
DP case.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108070
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108924
> Cc: Paulo Zanoni
> Cc: Ville Syrjälä
> Cc: José Roberto de Souza
> Cc: Rodrigo Vivi
> Signed-off-by: Imre Deak
> ---
> dr
ts either via a VBT option or a HW/FW register.
>
> Suggested-by: Ville Syrjälä
> Cc: Paulo Zanoni
> Cc: Ville Syrjälä
> Cc: José Roberto de Souza
> Cc: Rodrigo Vivi
> Signed-off-by: Imre Deak
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/intel_dp.c | 8
On Fri, Dec 14, 2018 at 11:34:13AM -0800, Clint Taylor wrote:
>Oops, failure caused by ICL_PORT_TX_DW7 not being defined yet. Still
>waiting on r-b for a patch that includes the DW7 definition.
I believe it is easier to re-send both patches together. Specially
because apparently one justif
On Fri, Dec 14, 2018 at 01:25:07AM +0200, Imre Deak wrote:
> On Thu, Dec 13, 2018 at 01:06:51PM -0800, Rodrigo Vivi wrote:
> > On Thu, Dec 13, 2018 at 09:48:49PM +0200, Imre Deak wrote:
> > > Atm HPD disconnect events on TypeC ports will break things, since we'll
>
On Sat, Dec 15, 2018 at 01:25:45AM +0200, Imre Deak wrote:
> On Fri, Dec 14, 2018 at 02:22:09PM -0800, Rodrigo Vivi wrote:
> > On Fri, Dec 14, 2018 at 01:25:07AM +0200, Imre Deak wrote:
> > > On Thu, Dec 13, 2018 at 01:06:51PM -0800, Rodrigo Vivi wrote:
> > > > On T
ady that we
> won't disconnect legacy ports in that function.
> - Add a note about the new intel_ddi_encoder_destroy() hook.
> - Reword the commit message after switching to the VBT based detection.
Reviewed-by: Rodrigo Vivi
(just because you asked about what I feel non-symmetric I wi
On Mon, Dec 17, 2018 at 03:23:14PM +0100, Hans de Goede wrote:
> Hi All,
>
> As discussed a while ago, I would like to see us enable fastboot by
> default, starting with Skylake / GEN9 and newer hardware, so that we can
> avoid an unnecessary modeset at boot and move to a truely flickerfree boot.
On Mon, Dec 17, 2018 at 09:35:05PM +0200, Imre Deak wrote:
> On Mon, Dec 17, 2018 at 10:05:40AM -0800, Rodrigo Vivi wrote:
> > On Fri, Dec 14, 2018 at 08:27:02PM +0200, Imre Deak wrote:
> > > Atm HPD disconnect events on TypeC ports will break things, since we'll
>
Paulo Zanoni
> Cc: Ville Syrjälä
> Cc: José Roberto de Souza
> Cc: Rodrigo Vivi
> Signed-off-by: Imre Deak
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> drivers/gpu/drm/i915/intel_bios.c | 11 +--
> 2 files changed, 11 inser
On Tue, Dec 18, 2018 at 05:07:34PM +0100, Hans de Goede wrote:
> Hi,
>
> On 17-12-18 19:43, Rodrigo Vivi wrote:
> > On Mon, Dec 17, 2018 at 03:23:14PM +0100, Hans de Goede wrote:
> > > Hi All,
> > >
> > > As discussed a while ago, I would like to see us
: Dhinakaran Pandiyan
Cc: José Roberto de Souza
Acked-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 19 +++
> 1 file changed, 19 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index e3
On Fri, Dec 21, 2018 at 07:14:36PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> IS_GLK||IS_BXT == IS_GEN9_LP
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Rodrigo Vivi
(I wont be able to review the entire series, just quickly
glancing the obvious ones before going
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