From: Tvrtko Ursulin
JSON output has the full breakdown but for now the interactive mode only
shows total and resident aggregated for all memory regions.
Signed-off-by: Tvrtko Ursulin
---
tools/intel_gpu_top.c | 114 +-
1 file changed, 112 insertions
From: Tvrtko Ursulin
Igt_drm_fdinfo defines it as an unsigned long so it is best that it
matches here as well.
Signed-off-by: Tvrtko Ursulin
---
lib/igt_drm_clients.c | 2 +-
lib/igt_drm_clients.h | 2 +-
tools/intel_gpu_top.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff
From: Tvrtko Ursulin
I will need some record of which regions were found for intel_gpu_top so
lets just copy over the region name from the map on the first match.
Signed-off-by: Tvrtko Ursulin
---
lib/igt_drm_fdinfo.c | 4
1 file changed, 4 insertions(+)
diff --git a/lib
From: Tvrtko Ursulin
A few basic smoke tests to check per client memory info looks legit.
Signed-off-by: Tvrtko Ursulin
---
tests/intel/drm_fdinfo.c | 217 +++
1 file changed, 217 insertions(+)
diff --git a/tests/intel/drm_fdinfo.c b/tests/intel
From: Tvrtko Ursulin
A short smoke tests to exercise fdinfo reads in parallel to contexts
getting created and destroyed.
Signed-off-by: Tvrtko Ursulin
---
tests/intel/drm_fdinfo.c | 68
1 file changed, 68 insertions(+)
diff --git a/tests/intel
From: Tvrtko Ursulin
On top of checking that parsing works, check that there are some engines
present. This will be needed once the memory stats are added and so return
value from __igt_parse_drm_fdinfo() will then be possible to be greater
than zero even when engine stats are not supported
From: Tvrtko Ursulin
Some new tests to exercise per client fdinfo memory stats.
Same as the previous posting, just rebased on top of latest intel_gpu_top fixes.
i915 kernel side at https://patchwork.freedesktop.org/series/119082/.
Tvrtko Ursulin (9):
tests/i915/drm_fdinfo: Check engine info
On 11/10/2023 13:40, Kamil Konieczny wrote:
Hi Tvrtko,
On 2023-10-11 at 09:38:44 +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Padding the percentage bars and table columns with spaces happens quite a
lot so lets do better than putchar at a time. Have a table of visually
empty strings
From: Tvrtko Ursulin
Instead of asserting just skip trying to print columns when terminal is
too narrow.
At the same time fix some type confusion to fix calculations going huge.
Signed-off-by: Tvrtko Ursulin
Closes: https://gitlab.freedesktop.org/drm/igt-gpu-tools/-/issues/143
Reviewed
From: Tvrtko Ursulin
Padding the percentage bars and table columns with spaces happens quite a
lot so lets do better than putchar at a time. Have a table of visually
empty strings and build the required length out of those chunks.
While at it, also move the percentage bar table into its
From: Tvrtko Ursulin
When I moved the client name to be last, I did not account for the fact
current code skips showing engine utilisation until at least two sampling
periods have passed. Consequence of this is that client name gets printed
as the second field and not under the "NAME&qu
From: Tvrtko Ursulin
Recent refactoring broke the clients header in cases when there are no
clients displayed. To fix it we need to account the width of the "NAME"
label.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Kamil Konieczny
---
tools/intel_gpu_top.c | 7 ---
1 file
On 11/10/2023 09:22, Tvrtko Ursulin wrote:
On 10/10/2023 17:43, Kamil Konieczny wrote:
Hi Tvrtko,
On 2023-10-10 at 12:07:14 +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Instead of asserting just skip trying to print columns when terminal is
too narrow.
At the same time fix some type
From: Tvrtko Ursulin
Padding the percentage bars and table columns with spaces happens quite a
lot so lets do better than putchar at a time. Have a table of visually
empty strings and build the required length out of those chunks.
While at it, also move the percentage bar table into its
for demonstrating the need with an RFC again.
If there are outstanding review comments of course address those, check
BAT and all but otherwise I am happy.
Acked-by: Tvrtko Ursulin
Regards,
Tvrtko
v2:
- Add missing supporting patches.
v3:
- Split suspend/resume changes and multi-gt support
On 10/10/2023 17:43, Kamil Konieczny wrote:
Hi Tvrtko,
On 2023-10-10 at 12:07:14 +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Instead of asserting just skip trying to print columns when terminal is
too narrow.
At the same time fix some type confusion to fix calculations going huge
On 10/10/2023 19:44, Jonathan Cavitt wrote:
For platforms supporting selective tlb invalidations, we don't need to
do a full tlb invalidation. Rather do a range based tlb invalidation for
every unbind of purged vma belongs to an active vm.
Signed-off-by: Prathap Kumar Valsan
Cc: Niranjana
On 10/10/2023 17:17, Andi Shyti wrote:
Hi Matt,
FIXME: CAT errors are cropping up on MTL. This removes them,
but the real root cause must still be diagnosed.
Do you have a link to specific IGT test(s) that illustrate the CAT
errors so that we can ensure that they now appear fixed in CI?
From: Tvrtko Ursulin
Instead of asserting just skip trying to print columns when terminal is
too narrow.
At the same time fix some type confusion to fix calculations going huge.
Signed-off-by: Tvrtko Ursulin
Closes: https://gitlab.freedesktop.org/drm/igt-gpu-tools/-/issues/143
---
tools
From: Tvrtko Ursulin
Recent refactoring broke the clients header in cases when there are no
clients displayed. To fix it we need to account the width of the "NAME"
label.
Signed-off-by: Tvrtko Ursulin
---
tools/intel_gpu_top.c | 7 ---
1 file changed, 4 insertions(+), 3 deletion
From: Tvrtko Ursulin
Padding the percentage bars and table columns with spaces happens quite a
lot so lets do better than putchar at a time. Have a table of visually
empty strings and build the required length out of those chunks.
While at it, also move the percentage bar table into its
From: Tvrtko Ursulin
A collection of small fixes around various edge case scenarios.
Tvrtko Ursulin (4):
tools/intel_gpu_top: Fix clients header width when no clients
tools/intel_gpu_top: Fix client layout on first sample period
tools/intel_gpu_top: Optimise interactive display a bit
From: Tvrtko Ursulin
When I moved the client name to be last, I did not account for the fact
current code skips showing engine utilisation until at least two sampling
periods have passed. Consequence of this is that client name gets printed
as the second field and not under the "NAME&qu
Krzysztofik
Signed-off-by: Jonathan Cavitt
Signed-off-by: Nirmoy Das
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Andi Shyti
Cc: Jani Nikula
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Cc: Tvrtko Ursulin
---
Hello,
This patch eliminates the 'force probe' for the MTL platforms. Over the recent
On 09/10/2023 20:14, John Harrison wrote:
On 10/9/2023 01:56, Tvrtko Ursulin wrote:
On 06/10/2023 19:20, Jonathan Cavitt wrote:
From: Prathap Kumar Valsan
The GuC firmware had defined the interface for Translation Look-Aside
Buffer (TLB) invalidation. We should use this interface when
On 09/10/2023 18:29, Jonathan Cavitt wrote:
For the gt_tlb live selftest, when operating on the GSC engine,
increase the timeout from 10 ms to 200 ms because the GSC
engine is a bit slower than the rest.
And others from 10ms to 20ms. By accident or deliberate?
Regards,
Tvrtko
On 09/10/2023 18:29, Jonathan Cavitt wrote:
From: Prathap Kumar Valsan
The GuC firmware had defined the interface for Translation Look-Aside
Buffer (TLB) invalidation. We should use this interface when
invalidating the engine and GuC TLBs.
Add additional functionality to
On 09/10/2023 13:12, Nirmoy Das wrote:
On 10/6/2023 8:20 PM, Jonathan Cavitt wrote:
From: Prathap Kumar Valsan
The GuC firmware had defined the interface for Translation Look-Aside
Buffer (TLB) invalidation. We should use this interface when
invalidating the engine and GuC TLBs.
Add
On 09/10/2023 12:40, Andi Shyti wrote:
Hi,
...
@@ -131,11 +132,23 @@ void intel_gt_invalidate_tlb_full(struct intel_gt *gt,
u32 seqno)
return;
with_intel_gt_pm_if_awake(gt, wakeref) {
+ struct intel_guc *guc = >uc.guc;
+
On 06/10/2023 19:20, Jonathan Cavitt wrote:
In case of GT is suspended, don't allow submission of new TLB invalidation
request and cancel all pending requests. The TLB entries will be
invalidated either during GuC reload or on system resume.
Signed-off-by: Fei Yang
Signed-off-by: Jonathan
On 06/10/2023 19:20, Jonathan Cavitt wrote:
From: Prathap Kumar Valsan
The GuC firmware had defined the interface for Translation Look-Aside
Buffer (TLB) invalidation. We should use this interface when
invalidating the engine and GuC TLBs.
Add additional functionality to
On 06/10/2023 19:50, John Harrison wrote:
Tvrtko, would you have any thoughts on this one?
I wasn't really involved in that work so without digging deep can only
say that smatch seems to be noticing a genuine inconsistency. Whether or
not it is possible at runtime Matt should know better.
On 06/10/2023 11:11, Tvrtko Ursulin wrote:
Hi,
Andi asked me to summarize what I think is unaddressed review feedback
so far in order to consolidate and enable hopefully things to move
forward. So I will try to re-iterate the comments and questions below.
But also note
On 06/10/2023 11:46, Ville Syrjälä wrote:
On Fri, Oct 06, 2023 at 09:31:01AM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
It is not our policy to keep pre-production hardware support for this long
so I guess this one was just forgotten.
This is about detecting pre-prod hw
On 05/10/2023 20:35, Jonathan Cavitt wrote:
In case of GT is suspended or wedged, don't allow submission of new TLB
invalidation request and cancel all pending requests. The TLB entries
will be invalidated either during GuC reload or on system resume.
Signed-off-by: Fei Yang
Signed-off-by:
Hi,
Andi asked me to summarize what I think is unaddressed review feedback
so far in order to consolidate and enable hopefully things to move
forward. So I will try to re-iterate the comments and questions below.
But also note that there is a bunch of new valid comments from John
against
From: Tvrtko Ursulin
XeHP SDV was a pre-production hardware used to bring up ATS and was not
generally available. Since latter was since explicitly added, there is no
need to keep the code for the former around.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_gsc.c
From: Tvrtko Ursulin
It is not our policy to keep pre-production hardware support for this long
so I guess this one was just forgotten.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_driver.c | 1 -
drivers/gpu/drm/i915/i915_drv.h| 2 --
2 files changed, 3 deletions(-)
diff
From: Tvrtko Ursulin
PVC support will not be coming to i915 so get rid of its partial
enablement and reduce the driver maintenance burden.
Signed-off-by: Tvrtko Ursulin
---
.../gpu/drm/i915/gem/i915_gem_object_types.h | 2 +-
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 3 -
drivers
From: Tvrtko Ursulin
A little bit of house keeping, trimming off some pre-production hardware and
incomplete platform support.
Tvrtko Ursulin (3):
drm/i915: Remove early/pre-production Haswell code
drm/i915: Remove incomplete PVC plumbing
drm/i915: Remove xehpsdv support
.../gpu/drm
On 05/10/2023 13:52, Jani Nikula wrote:
On Thu, 05 Oct 2023, Jouni Högander wrote:
Currently all module parameters are handled by i915_param.c/h. This
is a problem for display parameters when Xe driver is used.
This patch set adds a mechanism to add parameters specific to the
display. This
On 04/10/2023 19:36, Jonathan Cavitt wrote:
From: Prathap Kumar Valsan
The GuC firmware had defined the interface for Translation Look-Aside
Buffer (TLB) invalidation. We should use this interface when
invalidating the engine and GuC TLBs.
Add additional functionality to
On 03/10/2023 22:01, Jonathan Cavitt wrote:
In case of GT is suspended or wedged, don't allow submission of new TLB
invalidation request and cancel all pending requests. The TLB entries
will be invalidated either during GuC reload or on system resume.
Signed-off-by: Fei Yang
Signed-off-by:
On 03/10/2023 22:01, Jonathan Cavitt wrote:
From: Prathap Kumar Valsan
The GuC firmware had defined the interface for Translation Look-Aside
Buffer (TLB) invalidation. We should use this interface when
invalidating the engine and GuC TLBs.
Add additional functionality to
On 04/10/2023 10:43, Andi Shyti wrote:
The MCR steering semaphore is a shared lock entry between i915
and various firmware components.
Getting the lock might sinchronize on some shared resources.
Sometimes though, it might happen that the firmware forgets to
unlock causing unnecessary noise
On 04/10/2023 10:52, Mathias Krause wrote:
On 03.10.23 09:32, Tvrtko Ursulin wrote:
On 29/09/2023 12:00, Tvrtko Ursulin wrote:
[...]
Thanks again!
Reviewed-by: Tvrtko Ursulin
Patches pushed to drm-intel-gt-next.
Thanks, Tvrtko!
I guess this implies no backport of the first patch
On 03/10/2023 22:08, Jonathan Cavitt wrote:
Increase the timeout MCR waits for the steering semaphore
in intel_gt_mcr_lock by a factor of 10.
Ideally you mention why in the commit message, with some appropriate
level of detail depending on the situation.
+Matt for MCR stuff.
Regards,
/25233
v2:
- incorporated feedback from Tvrtko Ursulin:
- updated patch description to clarify the use case that identified
this issue.
- updated query_uc_fw_version() to use copy_query_item() helper.
- updated the implemented GuC version query to return Submission
version.
On 03/10/2023 21:23, John Harrison wrote:
On 10/3/2023 03:28, Tvrtko Ursulin wrote:
On 02/10/2023 18:24, Jonathan Cavitt wrote:
From: Prathap Kumar Valsan
The GuC firmware had defined the interface for Translation Look-Aside
Buffer (TLB) invalidation. We should use this interface when
On 03/10/2023 17:41, Andi Shyti wrote:
Hi,
[...]
+static void guc_ggtt_invalidate(struct i915_ggtt *ggtt)
+{
+ struct drm_i915_private *i915 = ggtt->vm.i915;
+ struct intel_gt *gt;
+
+ if (!IS_GEN9_LP(i915) && GRAPHICS_VER(i915) < 11)
+
Some more comments..
On 02/10/2023 18:24, Jonathan Cavitt wrote:
From: Prathap Kumar Valsan
The GuC firmware had defined the interface for Translation Look-Aside
Buffer (TLB) invalidation. We should use this interface when
invalidating the engine and GuC TLBs.
Add additional functionality
On 02/10/2023 18:24, Jonathan Cavitt wrote:
From: Fei Yang
In case of GT is suspended or wedged, don't allow submission of new TLB
invalidation request and cancel all pending requests. The TLB entries
will be invalidated either during GuC reload or on system resume.
Signed-off-by: Fei Yang
On 02/10/2023 18:24, Jonathan Cavitt wrote:
From: Prathap Kumar Valsan
The GuC firmware had defined the interface for Translation Look-Aside
Buffer (TLB) invalidation. We should use this interface when
invalidating the engine and GuC TLBs.
Add additional functionality to
On 29/09/2023 12:00, Tvrtko Ursulin wrote:
On 28/09/2023 19:20, Mathias Krause wrote:
Chaining user engines happens in multiple passes during driver
initialization, mutating its type along the way. It starts off with a
simple lock-less linked list (struct llist_node/head) populated
On 29/09/2023 21:18, Jonathan Cavitt wrote:
From: Fei Yang
In case of GT is suspended or wedged, don't allow submission of new TLB
invalidation request and cancel all pending requests. The TLB entries
will be invalidated either during GuC reload or on system resume.
Signed-off-by: Fei Yang
On 29/09/2023 16:40, Umesh Nerlige Ramappa wrote:
On Fri, Sep 29, 2023 at 12:09:49PM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
We have a nice error message displayed when an user with insufficient
permissions tries to run the tool, but that got lost while Meteorlake
support
On 02/10/2023 08:53, Jani Nikula wrote:
On Fri, 29 Sep 2023, Jonathan Cavitt wrote:
From: Fei Yang
In case of GT is suspended or wedged, don't allow submission of new TLB
invalidation request and cancel all pending requests. The TLB entries
will be invalidated either during GuC reload or
From: Tvrtko Ursulin
Igt_drm_fdinfo defines it as an unsigned long so it is best that it
matches here as well.
Signed-off-by: Tvrtko Ursulin
---
lib/igt_drm_clients.c | 2 +-
lib/igt_drm_clients.h | 2 +-
tools/intel_gpu_top.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff
From: Tvrtko Ursulin
JSON output has the full breakdown but for now the interactive mode only
shows total and resident aggregated for all memory regions.
Signed-off-by: Tvrtko Ursulin
---
tools/intel_gpu_top.c | 114 +-
1 file changed, 112 insertions
From: Tvrtko Ursulin
Similar as we can toggle between aggregated engines and clients, add the
capability to toggle between aggregated and per memory region stats.
It starts in aggregated mode by default and interactive command 'm' and
command line switch '-m' can be used to toggle that.
Both
From: Tvrtko Ursulin
Same concept as with the engine map, allowing callers to pass in fixed
map of names to indices, simplifying their implementation and avoiding
auto-detection while parsing.
Signed-off-by: Tvrtko Ursulin
---
lib/igt_drm_clients.c | 5 +++--
lib/igt_drm_clients.h | 3
From: Tvrtko Ursulin
Wrap all operations on clients via the Intel specific wrappers in order to
simplify upcoming work.
Signed-off-by: Tvrtko Ursulin
---
tools/intel_gpu_top.c | 42 ++
1 file changed, 22 insertions(+), 20 deletions(-)
diff --git
From: Tvrtko Ursulin
I will need some record of which regions were found for intel_gpu_top so
lets just copy over the region name from the map on the first match.
Signed-off-by: Tvrtko Ursulin
---
lib/igt_drm_fdinfo.c | 4
1 file changed, 4 insertions(+)
diff --git a/lib
From: Tvrtko Ursulin
When I moved the client name to be last, I did not account for the fact
current code skips showing engine utilisation until at least two sampling
periods have passed. Consequence of this is that client name gets printed
as the second field and not under the "NAME&qu
From: Tvrtko Ursulin
Padding the percentage bars and table columns with spaces happens quite a
lot so lets do better than putchar at a time. Have a table of visually
empty strings and build the required length out of those chunks.
While at it, also move the percentage bar table into its
From: Tvrtko Ursulin
Recent refactoring broke the clients header in cases when there are no
clients displayed. To fix it we need to account the width of the "NAME"
label.
Signed-off-by: Tvrtko Ursulin
---
tools/intel_gpu_top.c | 7 ---
1 file changed, 4 insertions(+), 3 deletion
From: Tvrtko Ursulin
A few basic smoke tests to check per client memory info looks legit.
Signed-off-by: Tvrtko Ursulin
---
tests/intel/drm_fdinfo.c | 217 +++
1 file changed, 217 insertions(+)
diff --git a/tests/intel/drm_fdinfo.c b/tests/intel
From: Tvrtko Ursulin
On top of checking that parsing works, check that there are some engines
present. This will be needed once the memory stats are added and so return
value from __igt_parse_drm_fdinfo() will then be possible to be greater
than zero even when engine stats are not supported
From: Tvrtko Ursulin
A short smoke tests to exercise fdinfo reads in parallel to contexts
getting created and destroyed.
Signed-off-by: Tvrtko Ursulin
---
tests/intel/drm_fdinfo.c | 68
1 file changed, 68 insertions(+)
diff --git a/tests/intel
From: Tvrtko Ursulin
Some basic testst for fdinfo memory stats, intel_gpu_top memory stats support
(first draft) and a couple fixlets.
Tvrtko Ursulin (12):
tests/i915/drm_fdinfo: Check engine info is supported
tests/i915/drm_fdinfo: Stress test context close versus fdinfo reads
tests/i915
On 28/09/2023 22:31, Umesh Nerlige Ramappa wrote:
On Thu, Sep 28, 2023 at 09:16:23AM +0100, Tvrtko Ursulin wrote:
On 27/09/2023 21:13, Umesh Nerlige Ramappa wrote:
On Fri, Sep 22, 2023 at 02:44:28PM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
We have a nice error message displayed
From: Tvrtko Ursulin
We have a nice error message displayed when an user with insufficient
permissions tries to run the tool, but that got lost while Meteorlake
support was added. Bring it back in.
v2:
* Propagate unexpected errno on multi-tile systems too. (Umesh)
Signed-off-by: Tvrtko
+ };
unsigned int engine_uabi_class_count[I915_LAST_UABI_ENGINE_CLASS + 1];
/* protects the irq masks */
Thanks again!
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
s to deal with the intermediate
llist state.
Reported-by: sanitiy checks in grsecurity
Typo in sanity - can fix up while merging.
Suggested-by: Tvrtko Ursulin
Fixes: 1ec23ed7126e ("drm/i915: Use uabi engines for the default engine map")
Signed-off-by: Mathias Krause
Cc: Jonathan Cavitt
On 27/09/2023 20:34, Belgaumkar, Vinay wrote:
On 9/21/2023 3:41 AM, Tvrtko Ursulin wrote:
On 20/09/2023 22:56, Vinay Belgaumkar wrote:
Provide a bit to disable waitboost while waiting on a gem object.
Waitboost results in increased power consumption by requesting RP0
while waiting
On 27/09/2023 14:48, Steven Price wrote:
On 27/09/2023 14:38, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
It is better not to lose precision and not revert to 1 MiB size
granularity for every size greater than 1 MiB.
Sizes in KiB should not be so troublesome to read (and in fact machine
On 27/09/2023 17:36, Teres Alexis, Alan Previn wrote:
Thanks for taking the time to review this Tvrtko, replies inline below.
On Wed, 2023-09-27 at 10:02 +0100, Tvrtko Ursulin wrote:
On 26/09/2023 20:05, Alan Previn wrote:
When suspending, add a timeout when calling
checks, make others IP version based
[mtl] (Matt Roper)
- Replace Meteorlake subplatforms with IP version checks (Matt Roper)
- Adding DeviceID for Arrowlake-S under MTL [mtl] (Nemesa Garg)
- Run relevant bits of debugfs drop_caches per GT (Tvrtko Ursulin)
Miscellaneous:
- Remove Wa_15010599737
On 14/09/2023 17:49, Matt Roper wrote:
On Thu, Sep 14, 2023 at 07:17:24PM +0530, Dnyaneshwar Bhadane wrote:
Set the instruction and state cache invalidate bit using INDIRECT_CTX on
every gpu context switch.
The goal of this workaround is to actually perform an explicit
invalidation of that
On 12/09/2023 13:46, Rodrigo Vivi wrote:
On Mon, Aug 28, 2023 at 12:04:50PM +0530, Tejas Upadhyay wrote:
Now this workaround is permanent workaround on MTL and DG2,
since this also impacts DG2, the subject 'drm/i915/mtl'
is wrong. I know, this is water under the bridge now.
Found this
Hi,
On 21/09/2023 07:24, Mathias Krause wrote:
On 05.09.23 13:39, Mathias Krause wrote:
Commit 1ec23ed7126e ("drm/i915: Use uabi engines for the default engine
map") introduced a bug regarding engine iteration in default_engines()
as the rb tree isn't set up yet that early during driver
From: Tvrtko Ursulin
Simplify the implementation of perf/OA queries by re-ogranizing the way
querying of the OA config list is done, how temporary storage is used,
and also replace the multi-step manual retrieving of user data with the
existing copy_query_item helper.
Note that this could
On 27/09/2023 21:13, Umesh Nerlige Ramappa wrote:
On Fri, Sep 22, 2023 at 02:44:28PM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
We have a nice error message displayed when an user with insufficient
permissions tries to run the tool, but that got lost while Meteorlake
support
From: Tvrtko Ursulin
Use the newly added drm_print_memory_stats helper to show memory
utilisation of our objects in drm/driver specific fdinfo output.
To collect the stats we walk the per memory regions object lists
and accumulate object size into the respective drm_memory_stats
categories.
v2
From: Tvrtko Ursulin
At the moment memory region names are a bit too varied and too
inconsistent to be used for ABI purposes, like for upcoming fdinfo
memory stats.
System memory can be either system or system-ttm. Local memory has the
instance number appended, others do not. Not only
From: Tvrtko Ursulin
Account ring buffers and logical context space against the owning client
memory usage stats.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Aravind Iddamsetty
---
drivers/gpu/drm/i915/gt/intel_context.c | 14 ++
drivers/gpu/drm/i915/i915_drm_client.c | 10
From: Tvrtko Ursulin
In order to show per client memory usage lets add some infrastructure
which enables tracking buffer objects owned by clients.
We add a per client list protected by a new per client lock and to support
delayed destruction (post client exit) we make tracked objects hold
From: Tvrtko Ursulin
Account page table backing store against the owning client memory usage
stats.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Aravind Iddamsetty
---
drivers/gpu/drm/i915/gt/intel_gtt.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt
From: Tvrtko Ursulin
To enable accounting of indirect client memory usage (such as page tables)
in the following patch, lets start recording the creator of each PPGTT.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Aravind Iddamsetty
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 11
From: Tvrtko Ursulin
It is better not to lose precision and not revert to 1 MiB size
granularity for every size greater than 1 MiB.
Sizes in KiB should not be so troublesome to read (and in fact machine
parsing is I expect the norm here), they align with other api like
/proc/meminfo
From: Tvrtko Ursulin
A short series to enable fdinfo memory stats for i915.
I added tracking of most classes of objects (user objects, page tables, context
state, ring buffers) which contribute to client's memory footprint and am
accouting their memory use along the similar lines as in Rob's
On 27/09/2023 14:23, Tvrtko Ursulin wrote:
On 27/09/2023 07:54, Andi Shyti wrote:
Hi Tvrtko,
Use the newly added drm_print_memory_stats helper to show memory
utilisation of our objects in drm/driver specific fdinfo output.
To collect the stats we walk the per memory regions object lists
drm_memory_stats
categories.
v2:
* Only account against the active region.
* Use DMA_RESV_USAGE_BOOKKEEP when testing for active. (Tejas)
v3:
* Update commit text. (Aravind)
* Update to use memory regions uabi names.
Signed-off-by: Tvrtko Ursulin
Cc: Aravind Iddamsetty
Cc: Rob Clark
From: Tvrtko Ursulin
A few basic smoke tests to check per client memory info looks legit.
Signed-off-by: Tvrtko Ursulin
---
tests/intel/drm_fdinfo.c | 217 +++
1 file changed, 217 insertions(+)
diff --git a/tests/intel/drm_fdinfo.c b/tests/intel
On 26/09/2023 11:26, Andi Shyti wrote:
Hi Tvrtko,
On Tue, Sep 26, 2023 at 11:08:55AM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Commit ade8a0f59844 ("drm/i915: Make all GPU resets atomic") added a
preempt disable section over the hardware reset callback to prepare
On 27/09/2023 05:14, Balasubrawmanian, Vivaik wrote:
Due to a bug in GuC firmware, Mesa can't enable by default the usage of
compute engines in DG2 and newer.
A new GuC firmware fixed the issue but until now there was no way
for Mesa to know if KMD was running with the fixed GuC version or
On 26/09/2023 20:05, Alan Previn wrote:
When suspending, add a timeout when calling
intel_gt_pm_wait_for_idle else if we have a lost
G2H event that holds a wakeref (which would be
indicative of a bug elsewhere in the driver),
driver will at least complete the suspend-resume
cycle, (albeit not
On 26/09/2023 16:29, Iddamsetty, Aravind wrote:
On 22-09-2023 19:16, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
At the moment memory region names are a bit too varied and too
inconsistent to be used for ABI purposes, like for upcoming fdinfo
memory stats.
System memory can be either system
On 26/09/2023 10:18, Andi Shyti wrote:
Hi Tvrtko,
Commit ade8a0f59844 ("drm/i915: Make all GPU resets atomic") added a
preempt disable section over the hardware reset callback to prepare the
driver for being able to reset from atomic contexts.
In retrospect I can see that the work item at a
From: Tvrtko Ursulin
Commit ade8a0f59844 ("drm/i915: Make all GPU resets atomic") added a
preempt disable section over the hardware reset callback to prepare the
driver for being able to reset from atomic contexts.
In retrospect I can see that the work item at a time was abou
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