From: Ville Syrjälä
Replace the hardcoded final numbers in the AUX SYNC/precharge
setup, and derive those from numbers from the (e)DP specs.
The new functions can serve as the single point of truth for
the number of SYNC pulses we use.
Cc: Jouni Högander
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
Fast wake should use 8 SYNC pulses for the preamble
and 10-16 SYNC pulses for the precharge. Recuce our
fast wake SYNC count to match the maximum value.
We also use the maximum precharge length for normal
AUX transactions.
Cc: Jouni Högander
Signed-off-by: Ville Syrjälä
From: Ville Syrjälä
Include the device and connector information in the SCDC
debugs. Makes it easier to figure out who did what.
Cc: Andrzej Hajda
Cc: Neil Armstrong
Cc: Robert Foss
Cc: Laurent Pinchart
Cc: Jonas Karlman
Cc: Jernej Skrabec
Cc: Thierry Reding
Cc: Emma Anholt
Cc: Maxime
From: Ville Syrjälä
In order to validate LUT programming more thoroughly let's
do a state check for all color management updates as well.
Not sure we really want this outside CI. It is rather heavy
and color management updates could become rather common
with all the HDR/etc. stuff happening.
From: Ville Syrjälä
Include the csc matrices in the state dump. The format being
hardware specific we just dump as hex for now. Might have
to think of some way to get a bit more human readable
output...
Signed-off-by: Ville Syrjälä
---
.../drm/i915/display/intel_crtc_state_dump.c | 43
From: Ville Syrjälä
Read out the csc matrix on chv, and stash the result into the
correct spot in the crtc state.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color.c | 36 ++
1 file changed, 36 insertions(+)
diff --git
From: Ville Syrjälä
Have the state checker validate that the csc matrices
look correct when read back from the hardware.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 21
1 file changed, 21 insertions(+)
diff --git
From: Ville Syrjälä
Make sure the csc enable bit(s) match the way we're about to
fill the csc matrices.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color.c | 22 ++
1 file changed, 22 insertions(+)
diff --git
From: Ville Syrjälä
Read out the pipe/output csc matrices on ilk+ and stash the results
(in the hardware specific format) into the appropriate place
in the crtc state.
Note that on skl/glk/icl the pipe csc unit suffers from an issue
where *reads* of the coefficient/offset registers also disarm
From: Ville Syrjälä
Store the chv cgm csc matrix in the crtc state as well. We
shall store it in the same place where we store the ilk+
pipe csc matrix (as opposed to the output csc matrix).
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color.c | 35
From: Ville Syrjälä
Embed a pair of intel_csc_matrix structs in the crtc state,
and fill them out appropriately during atomic_check().
Since pre-ivb platforms don't have programmable post offsets
we shall leave those zeroed, mainly in preparation for
state readout+check.
Signed-off-by: Ville
From: Ville Syrjälä
Convert chv_cgm_csc_convert_ctm() over to using the nee
intel_csc_matrix structure. No pre/post offsets on this
hardware so only the coefficients get filled out.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color.c | 24 +++---
1 file
From: Ville Syrjälä
Introduce a structure that can hold our CSC matrices. In there
we shall have the preoffsets, postoffsets, and coefficients,
all in platform specific format (at least for now).
We shall start by converting the ilk+ code to make use of
the new structure. chv will come later.
From: Ville Syrjälä
Split chv_cgm_csc_convert_ctm() out from chv_load_cgm_csc() so
that we have functions with clear jobs. This is also how the ilk+
code is already structured.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color.c | 19 +--
1 file
From: Ville Syrjälä
Our current limited range matrix is a bit off. I think it
was originally calculated with rounding, as if we wanted
the normal pixel replication type of behaviour.
That is, since the 8bpc max value is 0xeb we assumed the
16bpc max value should be 0xebeb, but what the HDMI spec
From: Ville Syrjälä
Implement state readout/check for the various CSC units
we utilize.
Ville Syrjälä (12):
drm/i915: Fix limited range csc matrix
drm/i915: Introduce intel_csc_matrix struct
drm/i915: Split chv_load_cgm_csc() into pieces
drm/i915: Start using struct intel_csc_matrix for
From: Ville Syrjälä
Only the PWM output mode of the utility pin is incompatible
with DC6/LCPLL disable. Check for that specifically.
References: https://gitlab.freedesktop.org/drm/intel/-/issues/6609
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display_power.c | 6
From: Ville Syrjälä
If we have to force the hardware to go through a full modeset
due to eg. cdclk reprogramming, we need to preserve
crtc_state->inherited for all crtcs that have not otherwise
gone through the whole compute_config() stuff after connectors
have been detected.
Otherwise eg.
From: Ville Syrjälä
The fact that DC states reset the PSR perofrmance counter
is no reason not to include it in the debug output.
But let's keep the comment there to remind people about
that caveat.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_psr.c | 10 --
1
From: Ville Syrjälä
Reduce the 'intel_dp' stuff a bit by introducing local
cpu_transcoder variables.
Ideally I'd like the whole PSR code to stop using intel_dp
except during a full modeset, but dunno yet if that's
possible. But the less 'intel_dp' we have sprad around
the easier that should be
From: Ville Syrjälä
We need to disable PSR when we are doing AUX by hand, otherwise
it's possible that the PSR hardware could be using the AUX CH
while we try to do our manual stuff. Add a FIXME for now.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dp_aux.c | 5 +
1
From: Ville Syrjälä
Define more of the PSR mask bits, and describe in detail
what some of them do. Even if we don't set them all from
the driver they can be very useful during PSR debugging.
Having to trawl through bspec every time to find them is
not fun, and re-reverse engineering the
From: Ville Syrjälä
Use REG_BIT() & co. to make the PSR register definitions
nicer.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_psr.c | 34 ++--
drivers/gpu/drm/i915/i915_reg.h | 197 ---
2 files changed, 116 insertions(+), 115
From: Ville Syrjälä
Replace some hand rolled RMW stuff with intel_de_rmw().
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_psr.c | 32 ++--
1 file changed, 13 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
From: Ville Syrjälä
Modernize a bunch of display chicken registers by using
REG_BIT() & co.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 106 +---
1 file changed, 55 insertions(+), 51 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h
From: Ville Syrjälä
Fix a binch of whitespace issues in some display register
definitons. Only touching the bits alerayd using REG_BIT() &
co. here. The rest will come later.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 70 -
1 file
From: Ville Syrjälä
Some cleanups around mostly PSR/related registers.
Ville Syrjälä (8):
drm/i915: Fix up whitespace in some display chicken registers
drm/i915: Clean up various display chicken registers
drm/i915/psr: Clean up PSR register defininitions
drm/i915/psr: Use intel_de_rmw()
From: Ville Syrjälä
Similar to FBC let's expose an debugfs file to control
IPS false color. Enabling this provides an immediate visual
feedback on whether IPS is working or not.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/hsw_ips.c| 58 ++-
From: Ville Syrjälä
IPS is a per-pipe feature, so let's move the debugfs stuff
under the crtc directory, and only register it when IPS
is actually available.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/hsw_ips.c| 15 +++
From: Ville Syrjälä
Currently we have no sane way to forcibly disable SAGV, which
makes debugging things a PITA. Manually poking at the pcode
mailbox with it's various SAGV/QGV/PSF formats is no fun,
and likely to be clobbered by the driver anyway.
Let's add a modparam for this.
Signed-off-by:
From: Ville Syrjälä
Advertize more suitable cursor sizes via the new SIZE_HINTS
plane property.
Here are some examples on various platforms:
ivb+:
31 SIZE_HINTS:
flags: immutable blob
blobs:
value:
From: Ville Syrjälä
Add a new immutable plane property by which a plane can advertise
a handful of recommended plane sizes. This would be mostly exposed
by cursor planes as a slightly more capable replacement for
the DRM_CAP_CURSOR_WIDTH/HEIGHT caps, which can only declare
a one size fits all
From: Ville Syrjälä
Tweak the parameters we pass to the cursor size_ok() functions
in preparation for using them to populate the SIZE_HINT property.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cursor.c | 63 +++--
1 file changed, 32 insertions(+), 31
From: Ville Syrjälä
I was pondering how I'd be able to do non-square cursor
sizes without have a massive list of them in the SIZE_HINTS
blob.
So I came up with this idea of having a 2D bitmap in
there to indicate support for (mostly) POT non-square
sizes..
What does everyone think? Is this
From: Ville Syrjälä
Move VRR enabling/disabling into a place where it also works
for fastsets.
With this we always start the transcoder up in non-VRR mode.
Granted we already did that but for a very short period of
time. But now that we might end up doing a bit more with the
transcoder in
From: Ville Syrjälä
Now that VRR enable/disable are called from convenient places
it is trivial to allow it to change state during fastsets.
Make it so.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/7542
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c
From: Ville Syrjälä
Move VRR enabling/disabling into a place where it also works
for fastsets.
With this we always start the transcoder up in non-VRR mode.
Granted we already did that but for a very short period of
time. But now that we might end up doing a bit more with the
transcoder in
From: Ville Syrjälä
In order to move VRR enable/disable to a place where it's also
applicable to fastsets we need to be prepared to configure
the pipe into non-VRR mode initially, and then later switch
to VRR mode. To that end allow the active timings to be configured
in non-VRR mode temporarily
From: Ville Syrjälä
On adl/dg2 a chicken bit needs to be set for TRANS_SET_CONTENXT_LATENCY
to take effect in VRR mode. Can't really think of a reason why we'd
ever disable that chicken bit, so let's just always set it.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_vrr.c
From: Ville Syrjälä
I want to use the same logic that planes_{enabling,disabling}()
are using for other features as well. Generlize the thing
into a pair of macros.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 16
1 file changed, 12
From: Ville Syrjälä
Some of the VRR functions take redundant arguments. Get rid
of them to make life simpler.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_vrr.c
From: Ville Syrjälä
People would prefer to be able to enable/disable VRR without
a full modeset. Make it so.
Ville Syrjälä (6):
drm/i915: Generalize planes_{enabling,disabling}()
drm/i915/vrr: Eliminate redundant function arguments
drm/i915/vrr: Make delayed vblank operational in VRR mode
From: Ville Syrjälä
Keeping DC states enabled is incompatible with the _noarm()/_arm()
split we use for writing pipe/plane registers. When DC5 and PSR
are enabled, all pipe/plane registers effectively become self-arming
on account of DC5 exit arming the update, and PSR exit latching it.
What
From: Ville Syrjälä
Define more of the PSR mask bits. Even if we don't set them
from the driver they can be very useful during PSR debugging.
Having to trawl through bspec every time to find them is
not fun.
The particularly interesting bits are:
-
From: Ville Syrjälä
Keeping DC states enabled is incompatible with the _noarm()/_arm()
split we use for writing pipe/plane registers. When DC5 and PSR
are enabled, all pipe/plane registers effectively become self-arming
on account of DC5 exit arming the update, and PSR exit latching it.
What
From: Ville Syrjälä
Unlike SKL/GLK the ICL CSC unit suffers from a new issue where
CSC_MODE arming is sticky. That is, once armed it remains armed
causing the CSC coeff/offset registers to become effectively
self-arming.
CSC coeff/offset registers writes no longer disarm the CSC,
but
From: Ville Syrjälä
We're going to need stuff after the color management
register lathcing has happened. Add a corresponding hook.
Cc: Manasi Navare
Cc: Drew Davenport
Cc: Imre Deak
Cc: Jouni Högander
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color.c | 13
From: Ville Syrjälä
SKL/GLK CSC unit suffers from a nasty issue where a CSC
coeff/offset register read or write between DC5 exit and
PSR exit will undo the CSC arming performed by DMC, and
then during PSR exit the hardware will latch zeroes into
the active CSC registers. This causes any plane
From: Ville Syrjälä
We're going to want different behavior for skl/glk vs. icl
in .color_commit_noarm(), so split the hook into two. Arguably
we already had slightly different behaviour since
csc_enable/gamma_enable are never set on icl+, so the old
code was perhaps a bit confusing as well.
Cc:
From: Ville Syrjälä
The CSC unit on SKL/GLK/ICL is borked in various ways. This
can cause black screens and/or premature noarm register latching.
And DC5+PSR can in general also cause premature noarm register
latching. Deal with it all.
Cc: Manasi Navare
Cc: Drew Davenport
Cc: Imre Deak
Cc:
From: Ville Syrjälä
All other skl+ universal plane register bit definitons are next
to the pipe A register definition. Move the PLANE_BUF_CFG bit
definitions there as well.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 10 +-
1 file changed, 5 insertions(+), 5
From: Ville Syrjälä
Add i915.enable_dpt modparam to allow disabling the DPT
usage in hardware via the chicken bit. Useful when debugging
potential DPT issues.
Quickly smoke tested on ADL.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 6 ++
From: Ville Syrjälä
Define the PLANE_CHICKEN register offsets.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d22ffd7a32dc..4ad36b637f82
From: Ville Syrjälä
Replace the hand rolled DISPLAY_VER check for a more descriptive
HAS_DPT() macro. Will be used on more than one place later.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fb.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 2 ++
2 files changed, 3
From: Ville Syrjälä
If we want to test with DPT disabled on ADL the POT stride remap
stuff needs to be disabled. Make it depend on actual DPT usage
instead of just assuming it based on the modifier.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fb.c | 2 +-
1 file
From: Ville Syrjälä
Currently i915_gem_object_is_framebuffer() doesn't treat the
BO containing the framebuffer's DPT as a framebuffer itself.
This means eg. that the shrinker can evict the DPT BO while
leaving the actual FB BO bound, when the DPT is allocated
from regular shmem.
That causes an
From: Ville Syrjälä
Avoid the shrinker evicting the DPT during hibernate and
causing an oops. This might also fix DPT induced display faults
during high memory pressure (though still don't have a real
theory how that could actually happen).
Also add a i915.enable_dpt modparam to disable DPT
From: Ville Syrjälä
Looks to me like the theoretical max the sprintf()s need
here is about 34+4+9+sizeof(de->d_name) bytes. Let's just
make that 64+sizeof(de->d_name) for simplicity.
This shuts up the compiler:
../src/intel_device.c: In function ‘__intel_open_device__pci’:
From: Ville Syrjälä
../src/sna/kgem_debug_gen3.c:1289:50: warning: ‘%03d’ directive writing between
3 and 10 bytes into a region of size 8 [-Wformat-overflow=]
1289 | sprintf(instr_prefix, "PS%03d", instr);
| ^~~~
From: Ville Syrjälä
3DSTATE_PIXEL_SHADER_PROGRAM instruction length is
9 bits, not 8 bits.
Signed-off-by: Ville Syrjälä
---
src/sna/kgem_debug_gen3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/sna/kgem_debug_gen3.c b/src/sna/kgem_debug_gen3.c
index
From: Ville Syrjälä
For consistency with most other code use the kms crtc index
instead of the hardware pipe number where either will do.
Signed-off-by: Ville Syrjälä
---
src/sna/sna_video_sprite.c | 44 +++---
1 file changed, 22 insertions(+), 22 deletions(-)
From: Ville Syrjälä
../src/sna/kgem_debug_gen2.c:625:5: warning: ‘static’ is not at beginning of
declaration [-Wold-style-declaration]
625 | const static struct {
| ^
Signed-off-by: Ville Syrjälä
---
src/sna/kgem_debug_gen2.c | 2 +-
1 file changed, 1 insertion(+), 1
From: Ville Syrjälä
Start using the kms crtc index rather than the pipe almost
everywhere. The two numbers could in theory be different
if the hardware has some pipes fused off. Though I think
such non-contiguous fusing won't actually happen on the
hardware generations the driver fully supports.
From: Ville Syrjälä
Let's the limit the use of hardware pipe numbers to absolutely
the only place where it's needed (MI_SCANLINE_WAIT). Everywhere
else just use the crtc index.
Signed-off-by: Ville Syrjälä
---
src/sna/sna_display.c | 220 +++--
From: Ville Syrjälä
Start using the kms crtc index rather than the pipe almost
everywhere. The two numbers could in theory be different
if the hardware has some pipes fused off. Though I think
such non-contiguous fusing won't actually happen on the
hardware generations the driver fully supports.
From: Ville Syrjälä
Move intel_plane_check_src_coordinates() from the pre-skl sprite
plane specific code to a more suitable place for common plane code.
Signed-off-by: Ville Syrjälä
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 60 ++-
From: Ville Syrjälä
Move the sprite colorkey ioctl handler to its own file
so that intel_sprite.c becomes all about the low level
details of pre-skl sprite planes.
And drop a bunch of unnecessary includes while at it.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/Makefile
From: Ville Syrjälä
Convert a few more skl+ plane registers to REG_BIT() & co.
Somehow thse were missed during the earlier cleanup.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git
From: Ville Syrjälä
Might as well complete the SURFLIVE register definitions
for all platforms/plane types. We are only missing the
VLV/CHV sprite planes.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
1 file changed, 3 insertions(+)
diff --git
From: Ville Syrjälä
Add the definitions for the skl+ univerals plane SURFLIVE
registers. Despite not being used for anything real
these came in suprisingly handy during some DSB debugging
recently, so having the defines around can be useful.
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
VLV/CHV have an extra register to configure some stereo3d
signalling details via DP MSA. Make sure we reset that
register to zero (since we don't do any stereo3d stuff).
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 2 ++
From: Ville Syrjälä
Add definitions for various pipe timestamp registers:
- frame timestamp (last start of vblank) (g4x+), already had this defined
- flip timestamp (when SURF was last written) (g4x+)
- flipdone timestamp (when last flipdone was signalled) (tgl+)
Note that on pre-tgl the flip
From: Ville Syrjälä
The PIPE_MISC registers don't exist on pre-bdw hardware,
so there is no point in using pipe_offsets[] for them.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
From: Ville Syrjälä
This PIPEMISC vs. PIPE_MISC inconsitency is ugly. Unify
the naming (PIPE_MISC is also what bspec has always called it).
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/icl_dsi.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 56
From: Ville Syrjälä
Do a bit of cleanup/reorganization around mostly plane
relatd stuff, and also add some more plane/pipe registers
that are useful for development/debugging.
Ville Syrjälä (9):
drm/i915: Stop using pipe_offsets[] for PIPE_MISC*
drm/i915: s/PIPEMISC/PIPE_MISC/
drm/i915:
From: Ville Syrjälä
Add a new immutable plane property by which a plane can advertise
a handful of recommended plane sizes. This would be mostly exposed
by cursor planes as a slightly more capable replacement for
the DRM_CAP_CURSOR_WIDTH/HEIGHT caps, which can only declare
a one size fits all
From: Ville Syrjälä
Remove the unused i915 variable to fix the build with WERROR=y.
Cc: Lucas De Marchi
Fixes: d1b3657fb5b6 ("drm/i915: Remove redundant check for DG1")
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 --
1 file changed, 2 deletions(-)
diff
From: Ville Syrjälä
Pull the scanline_offset calculation into its own function. Might
have further use for this later with DSB scanline waits.
Reviewed-by: Jani Nikula
Reviewed-by: Mitul Golani
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_vblank.c | 89
From: Ville Syrjälä
Move intel_crtc_update_active_timings() into intel_vblank.c
where it more properly belongs.
Also do the s/dev_priv/i915/ modernization rename while at it.
Reviewed-by: Jani Nikula
Reviewed-by: Mitul Golani
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
Add some (probably overkill) locking to protect the vblank
timestamping constants updates during seamless M/N fastsets.
As everything should be naturally aligned I think the individual
pieces should probably end up updating atomically enough. So this
is only really meant to
From: Ville Syrjälä
When we change the M/N values seamlessly during a fastset we should
also update the vblank timestamping stuff to make sure the vblank
timestamp corrections/guesstimations come out exact.
Note that only crtc_clock and framedur_ns can actually end up
changing here during
From: Linus Torvalds
It turns out that commit 596ff4a09b89 ("cpumask: re-introduce
constant-sized cpumask optimizations") exposed a number of cases of
drivers not checking the result of "cpumask_next()" and friends
correctly.
The documented correct check for "no more cpus in the cpumask" is to
From: Ville Syrjälä
AFAICS Bspec has never asked us to switch to TPS1 when *disabling*
DP_TP_CTL. Let's stop doing that in case it confuses something.
We do have to switch before we *enable* DP_TP_CTL, but that
is already being handled correctly.
v2: Do the same for FDI
v3: Rebase
Reviewed-by:
From: Ville Syrjälä
Bspec calls us to select pattern 2 after link training for
DP 2.0. Let's do that... by doing nothing because we will
be transmitting pattern 2 at the end of the link training
already.
Reviewed-by: Imre Deak
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
AFAICS Bspec has never asked us to switch to TPS1 when *disabling*
DP_TP_CTL. Let's stop doing that in case it confuses something.
We do have to switch before we *enable* DP_TP_CTL, but that
is already being handled correctly.
v2: Do the same for FDI
Reviewed-by: Imre Deak
From: Ville Syrjälä
The pipe needs a certain amount of time during vblank to prefill
sufficiently. If the vblank is too short the relevant watermark
level must be disabled.
Start implementing the necessary calculations to check this.
Scaler and DSC prefill are left out for now as handling those
From: Ville Syrjälä
The most modern VBT I've observed in the wild is version 250.
The child dev size hasn't changed since version 216, so bump
the version number in the expected child dev size check.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_bios.c | 2 +-
1 file
From: Ville Syrjälä
Pull the scanline_offset calculation into its own function. Might
have further use for this later with DSB scanline waits.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_vblank.c | 89 +++--
1 file changed, 48 insertions(+), 41
From: Ville Syrjälä
Move intel_crtc_update_active_timings() into intel_vblank.c
where it more properly belongs.
Also do the s/dev_priv/i915/ modernization rename while at it.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 84 --
From: Ville Syrjälä
Add some (probably overkill) locking to protect the vblank
timestamping constants updates during seamless M/N fastsets.
As everything should be naturally aligned I think the individual
pieces should probably end up updating atomically enough. So this
is only really meant to
From: Ville Syrjälä
When we change the M/N values seamlessly during a fastset we should
also update the vblank timestamping stuff to make sure the vblank
timestamp corrections/guesstimations come out exact.
Note that only crtc_clock and framedur_ns can actually end up
changing here during
From: Ville Syrjälä
Pair each _hotplug_enables() function with
a corresponding _hotplug_mask() function so that
we can determine right bits to clear on a per hpd_pin basis.
We'll need this for turning on HPD sense for a specific
encoder rather than just all of them.
v2: Drop the unused 'i915'
From: Ville Syrjälä
Replace the hardcoded masks with just a loop over all hpd
pins using the _hotplug_mask() functions.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_irq.c | 57 +
1 file changed, 22 insertions(+), 35 deletions(-)
diff --git
From: Ville Syrjälä
We need to untangle the mess where some SKL machines (at least)
declare both DDI A and DDI E to be present in their VBT, and
both using AUX A. DDI A is a ghost eDP, wheres DDI E may be a
real DP->VGA converter.
Currently that is handled by checking the VBT child devices
for
From: Ville Syrjälä
Add a mechanism by which we can enable the HPD sense for
individual encoders.
This will be used during eDP probing to figure out if
anything is actually connected. The normal intel_hpd_irq_setup()
thing doesn't work since we only do that after probing the
outputs, and we
From: Ville Syrjälä
Pair each _hotplug_enables() function with
a corresponding _hotplug_mask() function so that
we can determine right bits to clear on a per hpd_pin basis.
We'll need this for turning on HPD sense for a specific
encoder rather than just all of them.
v2: Drop the unused 'i915'
From: Ville Syrjälä
The idea that ctg uses different HPD live state bits is
total nonsense, at least on my machine (Dell Latitude
E5400).
The only reason DP-B even works on my ctg is that DP-D
live state is stuck high, even though there is no physical
DP-D port. So when the detect checks DP-B
From: Ville Syrjälä
We'll need dig_port->connected() to be there for a HPD live
state check during eDP connector probing. Reorder intel_ddi_init()
accordingly. g4x_dp_init() is already fine.
Reviewed-by: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c |
From: Ville Syrjälä
SKL doesn't have any north DE hotplug stuff. Currently we're
trying to read DDI A live state from the BDW north DE bit,
instead of the approproate south DE bit. Fix it.
And for good measure clear the pointer to the north hpd
pin array, so that we'll actually notice if some
From: Ville Syrjälä
Carved out the HPD changes from by big DDI probe series
to get it tested separately.
Also tweaked a few things Jani pointed out during earlier
review, and tossed in one extra refactoring patch on top.
Ville Syrjälä (7):
drm/i915: Populate dig_port->connected() before
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