From: Ville Syrjälä
Stop dumping state while reading it out. We have a proper
place for that stuff.
Signed-off-by: Ville Syrjälä
---
.../gpu/drm/i915/display/intel_crtc_state_dump.c| 2 ++
drivers/gpu/drm/i915/display/intel_ddi.c| 13 +++--
2 files changed, 5
From: Ville Syrjälä
On pre-TGL FEC is a port level feature, not a transcoder
level features, and it's DDI A which doesn't have it, not
trancodere A. Check for the correct thing when determining
whether FEC is supported or not.
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
ICL doesn't support FEC with a x1 DP link. Make sure
we don't try to enable FEC in such cases.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dp.c | 23 ---
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git
From: Ville Syrjälä
The MST DSC code has a myriad of issues:
- Platform checks are wrong (MST+DSC is TGL+ only IIRC)
- Return values of .mode_valid_ctx() are wrong
- .mode_valid_ctx() assumes bigjoiner might be used, but ther rest
of the code doesn't agree
- compressed bpp calculations don't
From: Ville Syrjälä
The MST codepath is missing FEC readout. Add it.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index
From: Ville Syrjälä
The big one here is removal of the defunct i915 MST DSC code.
That one clearly needs a lot more love, and the big issue
there (FEC) probably can't be done in a way that can be
easily backported. So IMO we just need to nuke the whole
MST+DSC thing for now, or else we'll end up
From: Ville Syrjälä
The current code does '(bpp << 4) / 16' in the MST PBN
calculation, but that is just the same as 'bpp' so the
DSC codepath achieves absolutely nothing. Fix it up so that
the fractional part of the bpp value is actually used instead
of truncated away. 64*1006 has enough zero
From: Ville Syrjälä
To avoid annoying spec lookups let's define more PS_CTRL
bits in the header.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
From: Ville Syrjälä
Pimp the skl+ scaler register bits with REG_BIT()/etc.
Reviewed-by: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 98 ++---
1 file changed, 53 insertions(+), 45 deletions(-)
diff --git
From: Ville Syrjälä
Define and use the bitmasks for the x/y components
of the skl+ scaler window pos/size registers.
We stick to the full 16 bits mask here even though the
hardware limits are actually lower. The current (ADL)
hardware maximums are in fact: 14 bits for X size, 13 bits
for X pos,
From: Ville Syrjälä
Fix a typo in the PS_COEF_INDEX_AUTO_INC define.
Reviewed-by: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/skl_scaler.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git
From: Ville Syrjälä
Rename the scaler binding bits to match the spec more closely.
Also call the parameters 'plane_id' to make it a bit more clear
what to pass in.
v2: Don't break gvt
Reviewed-by: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/skl_scaler.c | 12
From: Ville Syrjälä
We have some duplicated scaler register defines that are
never used. Remove them.
Reviewed-by: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 12
1 file changed, 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h
From: Ville Syrjälä
Define and use the bitmasks for the x/y components
of the ilk+ panel filter window pos/size registers.
Note that we stick to the full 16 bit mask even though
the actual hardware limits are lower (and somewhat
platform dependent). BDW is actually limited to
13 bits horizontal
From: Ville Syrjälä
Remainder of the scaler/pfit cleanups.
v2: Go back to using full 16 bit masks for pos/size
Ville Syrjälä (7):
drm/i915: Define bitmasks for ilk pfit window pos/size
drm/i915: Remove dead scaler register defines
drm/i915: Rename skl+ scaler binding bits
drm/i915:
From: Ville Syrjälä
No idea why the DSI code is feeling the need to assert that
has_pch_encoder must not be set. PCH encoders aren't even a
thing on any platform that has DSI.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/icl_dsi.c | 2 --
From: Ville Syrjälä
The encoder hooks already get passed the crtc state so just
grab the crtc from there instead of from the connector state.
This is generally what everyone else does, so no reason for
icl_dsi.c to be different.
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
Follow what Windows does and do the DSI panel reset+power off
after everything else.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/icl_dsi.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git
From: Ville Syrjälä
icl+ DSI isn't respecting the panel power_off_delay. Remedy that.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/icl_dsi.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
b/drivers/gpu/drm/i915/display/icl_dsi.c
From: Ville Syrjälä
Do the scaler disable in the spot where bspec has specfied it
for TLG+ DSC. And also move the DSC disable to match what
intel_ddi.c does.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/icl_dsi.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
From: Ville Syrjälä
encoder->disable() is supposed to happen before the pipe/transcoder
gets disabled. The icl+ DSI code screwed that up and put most things
(including the transcoder disable itself) into encoder->disable().
Follow the common rules and hoist most things into the
From: Ville Syrjälä
The clock gating step is in the wrong spot compared to the
TGL+ bspec sequence. Move it the right place. Windows also
seems to use the TGL+ order here always.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/icl_dsi.c | 5 ++---
1 file changed, 2
From: Ville Syrjälä
Plug in the encoder->shutdown() hook for icl+ DSI so that
we are guaranteed to respect the power cycle delay during
reboots and whatnot.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/icl_dsi.c | 1 +
drivers/gpu/drm/i915/display/intel_dsi.c | 7 +++
From: Ville Syrjälä
Handle the DSI panel power cycle delay on icl+.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/icl_dsi.c | 6 ++
drivers/gpu/drm/i915/display/intel_dsi.c | 13 +
drivers/gpu/drm/i915/display/intel_dsi.h | 1 +
From: Ville Syrjälä
The programming of the DPHY vs. DSI _TIMING registers are
two separate steps in the TGL+ bspec sequence, with some
other stuff in between. Implement the same split.
Windows also seems follow the bspec TGL+ sequence, even
on ICL/JSL.
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
Help out debugging things by printing out how long the VBT
delay sequence is supposed to wait.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Ville Syrjälä
Windows doesn't try any tricks to optimize out the DSI panel power
delays. Let's follow suit since anything else is entirely untested
behaviour. Why would the VBT even specify a power on delay if we're
not supposed to use it?
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
Doing the init OTP and display on DSI sequences back to back
doesn't really make any sense (a single sequence would suffice
then). Move the display on sequence to be done just before
backlight on, which is also what Windows does.
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
Looks like we're trying to talk to the DSI panel even before turning
it on, on icl+. Bspec doesn't actually specify when these should be
done, but certainly we need to turn the panel on at least before
talking to it. So let's move the power on + reset deassert steps to
be the
From: Ville Syrjälä
A bunch of changes to the ICL+ DSI modeset sequences.
The hope is that these might help with
https://gitlab.freedesktop.org/drm/intel/-/issues/7717
Ville Syrjälä (14):
drm/i915/icl: Do panel power on + reset deassert earlier on icl+
drm/i915/dsi: Do display on sequence
From: Ville Syrjälä
All known issues fixed now, so re-enable PSR1 on hsw/bdw.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_pci.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index
From: Ville Syrjälä
Can't see why we'd want the sprite blocking PSR entry.
Mask it out.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 4
drivers/gpu/drm/i915/display/intel_psr.c | 4
2 files changed, 8 insertions(+)
diff --git
From: Ville Syrjälä
WA 0479 says: "Do not skip both TP1 and TP2/TP3". Let's just
stick the minimum 100us TP2/3 time in there to avoid that.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_psr.c | 9 +
1 file changed, 9 insertions(+)
diff --git
From: Ville Syrjälä
hsw/bdw lack the pipe register vs. display register distinction
in their PSR masking capabilities. So to keep our CURSURFLIVE
tricks working we need to just unmask all display register writes
on these platforms. The downside being that any display regitster
(eg. even SWF
From: Ville Syrjälä
Bspec asks us to unmask "vblank to registers" in the DPRS unit.
Note that I was unable to observe any change in hardware
behviour due to this bit on HSW. But let's do this anyway
in case it matters in some cases, and the correspoding bit
on BDW is abolutely critical as
From: Ville Syrjälä
Implement WaPsrDPAMaskVBlankInSRD:hsw, which makes the hardware
generate the extra vblank between link training and first frame
being transmitted. This is the same thing that's controlled by
TRANS_CHICKEN[21] on skl+ (but due to the funky double buffering
it's effectively
From: Ville Syrjälä
Add the PSR interrupt handling code back for HSW. Looks like
the removal was never completed anyway since the irq setup
code was lest untouched.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_irq.c | 14 ++
1 file changed, 14 insertions(+)
diff
From: Ville Syrjälä
Deal with HSW/BDW in transcoder_has_psr2().
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_psr.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
From: Ville Syrjälä
Reintroduce the special PSR AUX CH setup for hsw/bdw. Not all
of it was even removed (BDW AUX data registers were left behind).
Update the code to use REG_BIT() & co. while at it.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dp_aux.c | 2 +-
From: Ville Syrjälä
Add back hsw'w special SRD/PSR1 registers.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_psr.c | 20 +++
drivers/gpu/drm/i915/display/intel_psr_regs.h | 4
2 files changed, 20 insertions(+), 4 deletions(-)
diff --git
From: Ville Syrjälä
In preparation for re-introducing HSW's different PSR1 register
offeets let's just wrap all the registers into functions.
Avoids having to make the register macros more complex.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_psr.c | 99
From: Ville Syrjälä
The multiplication got replaced by an addition in some cleanup.
This means we never write the correct data to some of the BDW
PSR data registers and thus we fail to actually wake up the
panel from PSR.
Fixes: 4ab4fa103217 ("drm/i915/psr: Make PSR registers relative to
From: Ville Syrjälä
PC8+ clobbers a bunch of displays registers which need to
be restored by hand or else we lost a bunch of workarounds.
The important ones for us are at least CHICKEN_PAR2* and
CHICKEN_PIPESL*.
Curiously at least some CHICKEN_PAR1* registers
are preserved by the
From: Ville Syrjälä
Fix all the obvious issues affecting HSW/BDW PSR1 and
restore it back to life.
The PC8+ vs. init_clock_gating() problem also affects
some non-PSR workarounds as well.
Ville Syrjälä (13):
drm/i915: Re-init clock gating on coming out of PC8+
drm/i915/psr: Fix BDW PSR AUX
From: Ville Syrjälä
Rename the scaler binding bits to match the spec more closely.
Also call the parameters 'plane_id' to make it a bit more clear
what to pass in.
v2: Don't break gvt
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/skl_scaler.c | 12 ++--
From: Ville Syrjälä
Move skl_get_pfit_config() next to the other skl+ scaler code
and rename it to skl_scaler_get_config() so that it has a consistnet
namespace.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 49 ++--
From: Ville Syrjälä
Pimp the skl+ scaler register bits with REG_BIT()/etc.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 98 ++---
1 file changed, 53 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h
From: Ville Syrjälä
To avoid annoying spec lookups let's define more PS_CTRL
bits in the header.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
From: Ville Syrjälä
Define and use the bitmasks for the x/y components
of the ilk+ panel filter window pos/size registers.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 12
drivers/gpu/drm/i915/i915_reg.h | 8
2 files
From: Ville Syrjälä
Fix a typo in the PS_COEF_INDEX_AUTO_INC define.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/skl_scaler.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git
From: Ville Syrjälä
Rename the scaler binding bits to match the spec more closely.
Also call the parameters 'plane_id' to make it a bit more clear
what to pass in.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/skl_scaler.c | 12 ++--
drivers/gpu/drm/i915/i915_reg.h
From: Ville Syrjälä
Define and use the bitmasks for the x/y components
of the skl+ scaler window pos/size registers.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/skl_scaler.c | 14 --
drivers/gpu/drm/i915/i915_reg.h | 8
2 files changed, 16
From: Ville Syrjälä
ilk_pfit_enable() is defined before the first use. No need
for a forwared declaration.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
From: Ville Syrjälä
Polish the ilk+ pfit registers with REG_BIT() & co., and
also take the opportunity to unify the ivb/hsw vs. not checks
in ilk_pfit_enable() and ilk_get_pfit_config().
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 9 +++--
From: Ville Syrjälä
We have some duplicated scaler register defines that are
never used. Remove them.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 12
1 file changed, 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h
From: Ville Syrjälä
Move intel_atomic_setup_scalers() next to the other scaler
code in skl_scaler.c.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_atomic.c | 256 ---
drivers/gpu/drm/i915/display/intel_atomic.h | 4 -
From: Ville Syrjälä
Modernize the gmch pfit register definitions using REG_BIT/etc.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 15 +++---
drivers/gpu/drm/i915/display/intel_overlay.c | 16 +++---
drivers/gpu/drm/i915/display/intel_panel.c | 8 +--
From: Ville Syrjälä
Give the PFIT_CONTROL bits a consistent namespace.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_lvds.c| 2 +-
drivers/gpu/drm/i915/display/intel_overlay.c | 2 +-
drivers/gpu/drm/i915/display/intel_panel.c | 25 ++--
From: Ville Syrjälä
The skl+ scalers only sample 12 bits of PIPESRC so we can't
do any plane scaling at all when the pipe source size is >4k.
Make sure the pipe source size is also below the scaler's src
size limits. Might not be 100% accurate, but should at least be
safe. We can refine the
From: Ville Syrjälä
Move the VBLANK_EVASION_TIME_US definition to a slightly
better place.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_crtc.h| 10 ++
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 2 +-
From: Ville Syrjälä
One scaler bugfix, and a bunch of scaler/pfit cleanups/etc.
Ville Syrjälä (15):
drm/i915: Check pipe source size when using skl+ scalers
drm/i915: Relocate VBLANK_EVASION_TIME_US
drm/i915: Relocate intel_atomic_setup_scalers()
drm/i915: Relocate skl_get_pfit_config()
From: Ville Syrjälä
Replace the hardcoded masks with just a loop over all hpd
pins using the _hotplug_mask() functions.
v2: Deal with mtp
Reviewed-by: Vinod Govindapillai a #v1
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_irq.c | 65 -
1 file
From: Ville Syrjälä
We need to untangle the mess where some SKL machines (at least)
declare both DDI A and DDI E to be present in their VBT, and
both using AUX A. DDI A is a ghost eDP, wheres DDI E may be a
real DP->VGA converter.
Currently that is handled by checking the VBT child devices
for
From: Ville Syrjälä
Add a mechanism by which we can enable the HPD sense for
individual encoders.
This will be used during eDP probing to figure out if
anything is actually connected. The normal intel_hpd_irq_setup()
thing doesn't work since we only do that after probing the
outputs, and we
From: Ville Syrjälä
Pair each _hotplug_enables() function with
a corresponding _hotplug_mask() function so that
we can determine right bits to clear on a per hpd_pin basis.
We'll need this for turning on HPD sense for a specific
encoder rather than just all of them.
v2: Drop the unused 'i915'
From: Ville Syrjälä
Remainder of the eDP HPD check series, now rebased on top
of MTL HPD stuff.
Ville Syrjälä (4):
drm/i915: Introduce _hotplug_mask()
drm/i915: Introduce intel_hpd_enable_detection()
drm/i915: Check HPD live state during eDP probe
drm/i915: Reuse _hotplug_mask() in
From: Ville Syrjälä
intel_{mpllb,c10pll}_state_verify() blows up if you call them
for a non-modeset/fastset commit on account of the relevant
connector not being part of the overall atomic state.
Currently the state checker only runs for modeset/fastset
commits, but for testing purposes it is
From: Ville Syrjälä
The point of the WARN was to print something, not oops
straight up. Currently that is precisely what happens
if we can't find the connector for the crtc in the atomic
state. Get the dev pointer from the atomic state instead
of the potentially NULL encoder to avoid that.
From: Ville Syrjälä
intel_mpllb_state_verify() blows up if you call it for a
non-modeset/fastset commit on account of the relevant
connector not being part of the overall atomic state.
Currently the state checker only runs for modeset/fastset
commits, but for testing purposes it is sometimes
From: Ville Syrjälä
In order to validate LUT programming more thoroughly let's
do a state check for all color management updates as well.
Not sure we really want this outside CI. It is rather heavy
and color management updates could become rather common
with all the HDR/etc. stuff happening.
From: Ville Syrjälä
VLV has a so called "wide gamut color correction" unit (WGC).
What it is is a 3x3 matrix similar to the later CHV CGM
CSC, which less precisions/range. In fact CHV also has the WGC
but using it there doesn't reall make sense when you have the
superior CGM CSC around.
Hook up
From: Ville Syrjälä
The CHV CGM CSC coefficients are in s4.12 two's complement
format. Fix the CTM->CGM conversion to handle that correctly
instead of pretending that the hw coefficients are also
in some sign-magnitude format.
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
On CHV toggling the CGM CSC on/off while the pipe is running leads
to underruns. Looks like we'd have to do the toggling strictly inside
the start_of_vblank-frame_start window to avoid this, but that window
is less than a scanline so there's no way we can guarantee hitting
From: Ville Syrjälä
Apparently desktop gen3 parts don't support the
10bit gamma mode at all. Stop claiming otherwise.
As is the case with pipe A on gen3 mobile parts, the
PIPECONF gamma mode bit can be set but it has no
effect on the output.
PNV seems to be the only slight exception, but
From: Ville Syrjälä
Document in which order the CTM matrix elements are stored.
Signed-off-by: Ville Syrjälä
---
include/uapi/drm/drm_mode.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index 46becedf5b2f..43691058d28f
From: Ville Syrjälä
The ilk/snb code is internally fully capable of handling the
CTM property, so expose it.
Note that we still choose not to expose DEGAMMA_LUT though.
The hardware is capable if degamma or gamma, but not both
similtanously due to lack of the split gamma mode. Exposing
both
From: Ville Syrjälä
Mostly some CTM stuff:
- document the uapi better
- fix CHV CSC negative coefficients
- expose CTM on ilk/snb/vlv
- a bonus gamma patch for gen3
- cure CGM CSC underruns on CHV (new in v2)
Test-with: 20230411161555.10001-1-ville.syrj...@linux.intel.com
Ville Syrjälä (7):
From: Ville Syrjälä
In order to validate LUT programming more thoroughly let's
do a state check for all color management updates as well.
Not sure we really want this outside CI. It is rather heavy
and color management updates could become rather common
with all the HDR/etc. stuff happening.
From: Ville Syrjälä
The CHV CGM CSC coefficients are in s4.12 two's complement
format. Fix the CTM->CGM conversion to handle that correctly
instead of pretending that the hw coefficients are also
in some sign-magnitude format.
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
Apparently desktop gen3 parts don't support the
10bit gamma mode at all. Stop claiming otherwise.
As is the case with pipe A on gen3 mobile parts, the
PIPECONF gamma mode bit can be set but it has no
effect on the output.
PNV seems to be the only slight exception, but
From: Ville Syrjälä
VLV has a so called "wide gamut color correction" unit (WGC).
What it is is a 3x3 matrix similar to the later CHV CGM
CSC, which less precisions/range. In fact CHV also has the WGC
but using it there doesn't reall make sense when you have the
superior CGM CSC around.
Hook up
From: Ville Syrjälä
The ilk/snb code is internally fully capable of handling the
CTM property, so expose it.
Note that we still choose not to expose DEGAMMA_LUT though.
The hardware is capable if degamma or gamma, but not both
similtanously due to lack of the split gamma mode. Exposing
both
From: Ville Syrjälä
Document in which order the CTM matrix elements are stored.
Signed-off-by: Ville Syrjälä
---
include/uapi/drm/drm_mode.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index 46becedf5b2f..43691058d28f
From: Ville Syrjälä
Mostly some CTM stuff:
- document the uapi better
- fix CHV CSC negative coefficients
- expose CTM on ilk/snb/vlv
- a bonus gamma patch for gen3
Test-with: 20230411161555.10001-1-ville.syrj...@linux.intel.com
Ville Syrjälä (6):
drm/uapi: Document CTM matrix better
From: Ville Syrjälä
Reduce the 'intel_dp' stuff a bit by introducing local
cpu_transcoder variables.
Ideally I'd like the whole PSR code to stop using intel_dp
except during a full modeset, but dunno yet if that's
possible. But the less 'intel_dp' we have sprad around
the easier that should be
From: Ville Syrjälä
The fact that DC states reset the PSR perofrmance counter
is no reason not to include it in the debug output.
But let's keep the comment there to remind people about
that caveat.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_psr.c | 10 --
1
From: Ville Syrjälä
Modernize a bunch of display chicken registers by using
REG_BIT() & co.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 114 +---
1 file changed, 59 insertions(+), 55 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h
From: Ville Syrjälä
We need to disable PSR when we are doing AUX by hand, otherwise
it's possible that the PSR hardware could be using the AUX CH
while we try to do our manual stuff. Add a FIXME for now.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dp_aux.c | 5 +
1
From: Ville Syrjälä
Replace some hand rolled RMW stuff with intel_de_rmw().
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_psr.c | 32 ++--
1 file changed, 13 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
From: Ville Syrjälä
Define more of the PSR mask bits, and describe in detail
what some of them do. Even if we don't set them all from
the driver they can be very useful during PSR debugging.
Having to trawl through bspec every time to find them is
not fun, and re-reverse engineering the
From: Ville Syrjälä
Use REG_BIT() & co. to make the PSR register definitions
nicer.
v2: Rebase due to intel_psr_regs.h
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_psr.c | 34 ++-
drivers/gpu/drm/i915/display/intel_psr_regs.h | 197 +-
2 files
From: Ville Syrjälä
Fix a bunch of whitespace issues in some display register
definitons. Only touching the bits alerayd using REG_BIT() &
co. here. The rest will come later.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 70 -
1 file
From: Ville Syrjälä
Some cleanups around mostly PSR/related registers.
v2: Improve the mask bit docs and rebase due to
intel_psr_regs.h
Ville Syrjälä (8):
drm/i915: Fix up whitespace in some display chicken registers
drm/i915: Clean up various display chicken registers
drm/i915/psr:
From: Ville Syrjälä
Most places in the vblank code use min() to clamp scanline
counters below vtotal. But we missed one in the gen3/4
pixel counter based codepath.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_vblank.c | 3 +--
1 file changed, 1 insertion(+), 2
From: Ville Syrjälä
The transcoder M/N values are double buffered on the transcoder's
undelayed vblank. So when doing seamless M/N fastsets we need to
evade also that.
Not that currently the pipe's delayed vblank == transcoder's
undelayed vblank, so this is still a nop change. But in the
future
From: Ville Syrjälä
If the panel supports VRR it must be capable of accepting
timings with arbitrary vblank length, within the valid VRR
range. Use that fact to allow the user to request any refresh
rate they like. We simply pick the next highest fixed mode
from our list, and adjust the vblank
From: Ville Syrjälä
Include the device and connector information in the SCDC
debugs. Makes it easier to figure out who did what.
v2: Rely on connector->ddc (Maxime)
Cc: Andrzej Hajda
Cc: Neil Armstrong
Cc: Robert Foss
Cc: Laurent Pinchart
Cc: Jonas Karlman
Cc: Jernej Skrabec
Cc: Thierry
From: Ville Syrjälä
Define CUR_CHICKEN so we don't have to remember the offset.
Looks like it's getting introduced in mtl.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h
From: Ville Syrjälä
Add tgl+ comments to the PLANE_CHICKEN registers which
I apparently forgot to add when defining the registers.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
From: Ville Syrjälä
Cursor is not a universal plane and thus doesn't have the
PLANE_CHICKEN register. Skip it.
Fixes: c5de248484af ("drm/i915/dpt: Add a modparam to disable DPT via the
chicken bit")
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dpt.c | 6 +-
1 file
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