[Intel-gfx] [CI 6/7] drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported

2018-10-30 Thread Manasi Navare
When DSC is supported we need to validate the modes based on the maximum supported compressed BPP and maximum supported slice count. This allows us to allow the modes with pixel clock greater than the available link BW as long as it meets the compressed BPP and slice count requirements. v3: * Use

[Intel-gfx] [CI 6/7] drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported

2018-10-29 Thread Manasi Navare
When DSC is supported we need to validate the modes based on the maximum supported compressed BPP and maximum supported slice count. This allows us to allow the modes with pixel clock greater than the available link BW as long as it meets the compressed BPP and slice count requirements. v3: * Use

[Intel-gfx] [CI 6/7] drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported

2018-10-25 Thread Manasi Navare
When DSC is supported we need to validate the modes based on the maximum supported compressed BPP and maximum supported slice count. This allows us to allow the modes with pixel clock greater than the available link BW as long as it meets the compressed BPP and slice count requirements. v3: * Use