On Wednesday 26 August 2015 01:36 AM, Animesh Manna wrote:
While display engine entering into low power state no need to disable
cdclk pll as CSR firmware of dmc will take care. If pll is already
enabled firmware execution sequence will be blocked. This is one
of the criteria for dmc to work
On Mon, Aug 31, 2015 at 01:03:03AM +, Hindman, Gavin wrote:
> Unless I'm misreading that would imply that we are moving away from our
> previous position that DMC FW is optional, correct?Would this not
> render power-sequencing broken if a distro chose not to include DMC FW?
For upstream
Unless I'm misreading that would imply that we are moving away from our
previous position that DMC FW is optional, correct?Would this not render
power-sequencing broken if a distro chose not to include DMC FW?
Gavin Hindman
Senior Program Manager
SSG/OTC – Open Source Technology Center
On 8/26/2015 6:41 PM, Daniel Vetter wrote:
On Wed, Aug 26, 2015 at 01:36:08AM +0530, Animesh Manna wrote:
While display engine entering into low power state no need to disable
cdclk pll as CSR firmware of dmc will take care. If pll is already
enabled firmware execution sequence will be
On Wed, Aug 26, 2015 at 01:36:08AM +0530, Animesh Manna wrote:
While display engine entering into low power state no need to disable
cdclk pll as CSR firmware of dmc will take care. If pll is already
enabled firmware execution sequence will be blocked. This is one
of the criteria for dmc to
While display engine entering into low power state no need to disable
cdclk pll as CSR firmware of dmc will take care. If pll is already
enabled firmware execution sequence will be blocked. This is one
of the criteria for dmc to work properly.
v1: Initial version.
v2: Based on review comment
