[Intel-gfx] [PATCH] drm/i915/dg2: Invalidate LSC L1 cache

[Anusha Srivatsa]

Set the chicken bit to invalidate LSC L1 operation due to UAV
coherency barrier.

Cc: Matt Roper <matthew.d.ro...@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h     | 1 +
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +++++++
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h 
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index a6f0220c2e9f..43945661ad28 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1088,6 +1088,7 @@ enum {
 
 #define GEN12_HDC_CHICKEN0                                     _MMIO(0xE5F0)
 #define   LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK       REG_GENMASK(13, 
11)
+#define   INVALIDATE_UNTYPED_L1                                        
REG_FIELD_PREP(LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK, 0x2)
 
 #define SARB_CHICKEN1                          _MMIO(0xe90c)
 #define   COMP_CKN_IN                          REG_GENMASK(30, 29)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index b146a393cd79..deba076f74d8 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2049,6 +2049,13 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, 
struct i915_wa_list *wal)
        if (IS_DG2(i915)) {
                /* Wa_14015227452:dg2 */
                wa_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE);
+
+               /* This is not an actual workaround, but a hardware requirement
+                * done to override the default value.
+                */
+               wa_masked_en(wal,
+                            GEN12_HDC_CHICKEN0,
+                            INVALIDATE_UNTYPED_L1);
        }
 
        if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) {
-- 
2.25.1