> -Original Message-
> From: Auld, Matthew
> Sent: Wednesday, October 12, 2022 3:19 PM
> To: Gupta, Anshuman ; intel-
> g...@lists.freedesktop.org
> Cc: joonas.lahti...@linux.intel.com; tvrtko.ursu...@linux.intel.com; Vivi,
> Rodrigo
> Subject: Re: [PATCH] drm/i915/dgfx: Temporary
> -Original Message-
> From: Vivi, Rodrigo
> Sent: Wednesday, October 12, 2022 8:31 PM
> To: Joonas Lahtinen
> Cc: Gupta, Anshuman ; intel-
> g...@lists.freedesktop.org; tvrtko.ursu...@linux.intel.com; Auld, Matthew
>
> Subject: Re: [PATCH] drm/i915/dgfx: Temporary hammer to keep
> -Original Message-
> From: Dixit, Ashutosh
> Sent: Wednesday, October 12, 2022 8:49 PM
> To: Auld, Matthew
> Cc: Gupta, Anshuman ; intel-
> g...@lists.freedesktop.org; Vivi, Rodrigo
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/dgfx: Temporary hammer to keep
On Wed, 12 Oct 2022 02:48:30 -0700, Matthew Auld wrote:
>
> So with this change all the runtime pm stuff is disabled on dgfx? i.e
> intel_runtime_pm_get() always returns zero or so?
I guess it should always return non-zero (or the wakeref) since the device
is always on...
On 12/10/2022 15:57, Rodrigo Vivi wrote:
On Wed, Oct 12, 2022 at 10:48:30AM +0100, Matthew Auld wrote:
On 12/10/2022 09:34, Anshuman Gupta wrote:
DGFX platforms has lmem and cpu can access the lmem objects
via mmap and i915 internal i915_gem_object_pin_map() for
i915 own usages. Both of these
On Wed, Oct 12, 2022 at 01:26:45PM +0300, Joonas Lahtinen wrote:
> I think I commented on this already, but the patch subject should really be as
> informative as possible like: "Disable PCI runtime PM on dGPUs" as that is
> exactly
> what the patch does.
+1 here.
>
> Also bit unsure if the
On Wed, Oct 12, 2022 at 10:48:30AM +0100, Matthew Auld wrote:
> On 12/10/2022 09:34, Anshuman Gupta wrote:
> > DGFX platforms has lmem and cpu can access the lmem objects
> > via mmap and i915 internal i915_gem_object_pin_map() for
> > i915 own usages. Both of these methods has pre-requisite
> >
On Wed, Oct 12, 2022 at 11:21:59AM +0200, Andi Shyti wrote:
> Hi Anshuman,
>
> On Wed, Oct 12, 2022 at 02:04:02PM +0530, Anshuman Gupta wrote:
> > DGFX platforms has lmem and cpu can access the lmem objects
> > via mmap and i915 internal i915_gem_object_pin_map() for
> > i915 own usages. Both of
I think I commented on this already, but the patch subject should really be as
informative as possible like: "Disable PCI runtime PM on dGPUs" as that is
exactly
what the patch does.
Also bit unsure if the Fixes: tag should really point to the runtime PM
commit but maybe instead to the
On 12/10/2022 09:34, Anshuman Gupta wrote:
DGFX platforms has lmem and cpu can access the lmem objects
via mmap and i915 internal i915_gem_object_pin_map() for
i915 own usages. Both of these methods has pre-requisite
requirement to keep GFX PCI endpoint in D0 for a supported
iomem transaction
Hi Anshuman,
On Wed, Oct 12, 2022 at 02:04:02PM +0530, Anshuman Gupta wrote:
> DGFX platforms has lmem and cpu can access the lmem objects
> via mmap and i915 internal i915_gem_object_pin_map() for
> i915 own usages. Both of these methods has pre-requisite
> requirement to keep GFX PCI endpoint
DGFX platforms has lmem and cpu can access the lmem objects
via mmap and i915 internal i915_gem_object_pin_map() for
i915 own usages. Both of these methods has pre-requisite
requirement to keep GFX PCI endpoint in D0 for a supported
iomem transaction over PCI link. (Refer PCIe specs 5.3.1.4.1)
12 matches
Mail list logo
