Re: [Intel-gfx] [PATCH] drm/i915/gen9_lp: Increase DDI PHY0 power well enabling timeout

2018-04-09 Thread Ville Syrjälä
On Mon, Apr 09, 2018 at 03:27:16PM +0300, Imre Deak wrote: > On GLK sporadic timeouts occur during PHY0 enabling. Based on logs it looks > like they happen sometime after a system suspend/resume cycle, with the > same power well enabling succeeding both before and after the failed > one and no

[Intel-gfx] [PATCH] drm/i915/gen9_lp: Increase DDI PHY0 power well enabling timeout

2018-04-09 Thread Imre Deak
On GLK sporadic timeouts occur during PHY0 enabling. Based on logs it looks like they happen sometime after a system suspend/resume cycle, with the same power well enabling succeeding both before and after the failed one and no other problems observed. The current timeout in the code is not