Hi Jonathan,
On Thu, Nov 02, 2023 at 10:58:31AM -0700, Jonathan Cavitt wrote:
> FIXME: It is suspected that some Address Translation Service (ATS)
> issue on IOMMU is causing CAT errors to occur on some MTL workloads.
> Applying a write barrier to the ppgtt set entry functions appeared
> to have n
> > > Sent: Thursday, November 2, 2023 10:59 AM
> > > To: intel-gfx@lists.freedesktop.org
> > > Cc: Gupta, saurabhg ; Cavitt, Jonathan
> > > ; chris.p.wil...@linux.intel.com
> > > Subject: [Intel-gfx] [PATCH] drm/i915/gt: Temporarily disable CPU caching
>
vitt, Jonathan
> > ; chris.p.wil...@linux.intel.com
> > Subject: [Intel-gfx] [PATCH] drm/i915/gt: Temporarily disable CPU caching
> > into
> > DMA for MTL
> >
> > FIXME: It is suspected that some Address Translation Service (ATS)
> > issue on IOMMU is cau
el-gfx] [PATCH] drm/i915/gt: Temporarily disable CPU caching into
> DMA for MTL
>
> FIXME: It is suspected that some Address Translation Service (ATS)
> issue on IOMMU is causing CAT errors to occur on some MTL workloads.
> Applying a write barrier to the ppgtt set entry function
FIXME: It is suspected that some Address Translation Service (ATS)
issue on IOMMU is causing CAT errors to occur on some MTL workloads.
Applying a write barrier to the ppgtt set entry functions appeared
to have no effect, so we must temporarily use I915_MAP_WC in the
map_pt_dma class of functions o
