On Thu, 02 Dec 2021, Ville Syrjälä wrote:
> On Thu, Dec 02, 2021 at 04:44:56PM +0200, Jani Nikula wrote:
>> The mode set sequence for 128b/132b requires setting the div32 version
>> of MPLLB clock.
>>
>> Bspec: 53880, 54128
>
> Weird place for that information when all the other bits are listed
>
On Thu, Dec 02, 2021 at 04:44:56PM +0200, Jani Nikula wrote:
> The mode set sequence for 128b/132b requires setting the div32 version
> of MPLLB clock.
>
> Bspec: 53880, 54128
Weird place for that information when all the other bits are listed
in the clock programming section :/
> Signed-off-by:
The mode set sequence for 128b/132b requires setting the div32 version
of MPLLB clock.
Bspec: 53880, 54128
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_snps_phy.c | 2 ++
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/driv
