On Tue, Mar 24, 2015 at 01:01:54PM +, Michel Thierry wrote:
> On 3/24/2015 12:54 PM, Mika Kuoppala wrote:
> >The faulting virtual address is >32bits and has been moved
> >to different registers. Add to error state and output upper
> >register first, in the same line for easy reconstruction of
>
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6039
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -2 275/275
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6038
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 275/275
On 3/24/2015 12:54 PM, Mika Kuoppala wrote:
The faulting virtual address is >32bits and has been moved
to different registers. Add to error state and output upper
register first, in the same line for easy reconstruction of
the fault address.
v2: correct gen masking (Michel)
v3: s/TBL/TLB (Ville)
The faulting virtual address is >32bits and has been moved
to different registers. Add to error state and output upper
register first, in the same line for easy reconstruction of
the fault address.
v2: correct gen masking (Michel)
v3: s/TBL/TLB (Ville)
Signed-off-by: Mika Kuoppala
---
drivers/g
On Tue, Mar 24, 2015 at 02:06:57PM +0200, Mika Kuoppala wrote:
> The faulting virtual address is >32bits and has been moved
> to different registers. Add to error state and output upper
> register first, in the same line for easy reconstruction of
> the fault address.
>
> v2: correct gen masking (
The faulting virtual address is >32bits and has been moved
to different registers. Add to error state and output upper
register first, in the same line for easy reconstruction of
the fault address.
v2: correct gen masking (Michel)
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_drv.h
