Re: [Intel-gfx] [PATCH] drm/i915: Apply alignment restrictions on scanout surfaces for VT-d

2013-03-26 Thread Daniel Vetter
On Tue, Mar 26, 2013 at 11:15:38PM +, Damien Lespiau wrote: > On Tue, Mar 05, 2013 at 02:52:39PM +, Chris Wilson wrote: > > From the w/a database: > > > > 'To prevent false VT-d type 6 error: > > > > The primary display plane must be 256KiB aligned, and require an extra > > 128 PTEs o

Re: [Intel-gfx] [PATCH] drm/i915: Apply alignment restrictions on scanout surfaces for VT-d

2013-03-26 Thread Damien Lespiau
On Tue, Mar 05, 2013 at 02:52:39PM +, Chris Wilson wrote: > From the w/a database: > > 'To prevent false VT-d type 6 error: > > The primary display plane must be 256KiB aligned, and require an extra > 128 PTEs of padding afterward; > > The sprites planes must be 128KiB aligned, and req

Re: [Intel-gfx] [PATCH] drm/i915: Apply alignment restrictions on scanout surfaces for VT-d

2013-03-05 Thread Daniel Vetter
On Tue, Mar 05, 2013 at 02:52:39PM +, Chris Wilson wrote: > From the w/a database: > > 'To prevent false VT-d type 6 error: > > The primary display plane must be 256KiB aligned, and require an extra > 128 PTEs of padding afterward; > > The sprites planes must be 128KiB aligned, and req

[Intel-gfx] [PATCH] drm/i915: Apply alignment restrictions on scanout surfaces for VT-d

2013-03-05 Thread Chris Wilson
>From the w/a database: 'To prevent false VT-d type 6 error: The primary display plane must be 256KiB aligned, and require an extra 128 PTEs of padding afterward; The sprites planes must be 128KiB aligned, and require an extra 64 PTEs of padding afterward; The cursors must be 64KiB al