Facilitates creating Gen-specific versions of these functions later on.
v2: Move everything into guc.interrupts (Michal)
Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursu...@intel.com>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Signed-off-by: Oscar Mateo <oscar.ma...@intel.com>
---
drivers/gpu/drm/i915/i915_guc_submission.c | 4 ++--
drivers/gpu/drm/i915/i915_irq.c | 18 ++++++++++++------
drivers/gpu/drm/i915/intel_drv.h | 3 ---
drivers/gpu/drm/i915/intel_guc_log.c | 6 +++---
drivers/gpu/drm/i915/intel_uc.c | 8 ++++----
drivers/gpu/drm/i915/intel_uc.h | 7 ++++++-
6 files changed, 27 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 48a1e93..b469326 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -1302,7 +1302,7 @@ int intel_guc_suspend(struct drm_i915_private *dev_priv)
if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
return 0;
- gen9_disable_guc_interrupts(dev_priv);
+ guc->interrupts.disable(dev_priv);
ctx = dev_priv->kernel_context;
@@ -1329,7 +1329,7 @@ int intel_guc_resume(struct drm_i915_private *dev_priv)
return 0;
if (i915.guc_log_level >= 0)
- gen9_enable_guc_interrupts(dev_priv);
+ guc->interrupts.enable(dev_priv);
ctx = dev_priv->kernel_context;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 5d391e6..9649df4 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -413,29 +413,29 @@ void gen6_disable_rps_interrupts(struct drm_i915_private
*dev_priv)
gen6_reset_rps_interrupts(dev_priv);
}
-void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv)
+static void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv)
{
spin_lock_irq(&dev_priv->irq_lock);
gen6_reset_pm_iir(dev_priv, dev_priv->pm_guc_events);
spin_unlock_irq(&dev_priv->irq_lock);
}
-void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv)
+static void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv)
{
spin_lock_irq(&dev_priv->irq_lock);
- if (!dev_priv->guc.interrupts_enabled) {
+ if (!dev_priv->guc.interrupts.enabled) {
WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
dev_priv->pm_guc_events);
- dev_priv->guc.interrupts_enabled = true;
+ dev_priv->guc.interrupts.enabled = true;
gen6_enable_pm_irq(dev_priv, dev_priv->pm_guc_events);
}
spin_unlock_irq(&dev_priv->irq_lock);
}
-void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv)
+static void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv)
{
spin_lock_irq(&dev_priv->irq_lock);
- dev_priv->guc.interrupts_enabled = false;
+ dev_priv->guc.interrupts.enabled = false;
gen6_disable_pm_irq(dev_priv, dev_priv->pm_guc_events);
@@ -4164,6 +4164,12 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
if (INTEL_GEN(dev_priv) >= 8)
dev_priv->rps.pm_intrmsk_mbz |=
GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
+ if (INTEL_GEN(dev_priv) >= 9) {
+ dev_priv->guc.interrupts.reset = gen9_reset_guc_interrupts;
+ dev_priv->guc.interrupts.enable = gen9_enable_guc_interrupts;
+ dev_priv->guc.interrupts.disable = gen9_disable_guc_interrupts;
+ }
+
if (IS_GEN2(dev_priv)) {
/* Gen2 doesn't have a hardware frame counter */
dev->max_vblank_count = 0;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 74c1860..442d378 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1234,9 +1234,6 @@ void gen8_irq_power_well_post_enable(struct
drm_i915_private *dev_priv,
u8 pipe_mask);
void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
u8 pipe_mask);
-void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
-void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
-void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
/* intel_crt.c */
void intel_crt_init(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c
b/drivers/gpu/drm/i915/intel_guc_log.c
index 16d3b87..a067bba 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -506,7 +506,7 @@ static void guc_flush_logs(struct intel_guc *guc)
return;
/* First disable the interrupts, will be renabled afterwards */
- gen9_disable_guc_interrupts(dev_priv);
+ guc->interrupts.disable(dev_priv);
/* Before initiating the forceful flush, wait for any pending/ongoing
* flush to complete otherwise forceful flush may not actually happen.
@@ -623,7 +623,7 @@ int i915_guc_log_control(struct drm_i915_private *dev_priv,
u64 control_val)
}
/* GuC logging is currently the only user of Guc2Host
interrupts */
- gen9_enable_guc_interrupts(dev_priv);
+ guc->interrupts.enable(dev_priv);
} else {
/* Once logging is disabled, GuC won't generate logs & send an
* interrupt. But there could be some data in the log buffer
@@ -656,7 +656,7 @@ void i915_guc_log_unregister(struct drm_i915_private
*dev_priv)
mutex_lock(&dev_priv->drm.struct_mutex);
/* GuC logging is currently the only user of Guc2Host interrupts */
- gen9_disable_guc_interrupts(dev_priv);
+ dev_priv->guc.interrupts.disable(dev_priv);
guc_log_runtime_destroy(&dev_priv->guc);
mutex_unlock(&dev_priv->drm.struct_mutex);
}
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 0178ba4..ff0f208 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -337,7 +337,7 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
return 0;
guc_disable_communication(guc);
- gen9_reset_guc_interrupts(dev_priv);
+ guc->interrupts.reset(dev_priv);
/* We need to notify the guc whenever we change the GGTT */
i915_ggtt_enable_guc(dev_priv);
@@ -393,7 +393,7 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
intel_guc_auth_huc(dev_priv);
if (i915.enable_guc_submission) {
if (i915.guc_log_level >= 0)
- gen9_enable_guc_interrupts(dev_priv);
+ guc->interrupts.enable(dev_priv);
ret = i915_guc_submission_enable(dev_priv);
if (ret)
@@ -413,7 +413,7 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
*/
err_interrupts:
guc_disable_communication(guc);
- gen9_disable_guc_interrupts(dev_priv);
+ guc->interrupts.disable(dev_priv);
err_log_capture:
guc_capture_load_err_log(guc);
err_submission:
@@ -452,7 +452,7 @@ void intel_uc_fini_hw(struct drm_i915_private *dev_priv)
guc_disable_communication(&dev_priv->guc);
if (i915.enable_guc_submission) {
- gen9_disable_guc_interrupts(dev_priv);
+ dev_priv->guc.interrupts.disable(dev_priv);
i915_guc_submission_fini(dev_priv);
}
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 22ae52b..0640a83 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -183,7 +183,12 @@ struct intel_guc {
struct drm_i915_gem_object *load_err_log;
/* intel_guc_recv interrupt related state */
- bool interrupts_enabled;
+ struct {
+ bool enabled;
+ void (*reset)(struct drm_i915_private *dev_priv);
+ void (*enable)(struct drm_i915_private *dev_priv);
+ void (*disable)(struct drm_i915_private *dev_priv);
+ } interrupts;
struct i915_vma *ads_vma;
struct i915_vma *stage_desc_pool;
--
1.9.1
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